Radiation Or Energy Treatment Modifying Properties Of Semiconductor Regions Of Substrate (e.g., Thermal, Corpuscular, Electromagnetic, Etc.) Patents (Class 438/308)
  • Patent number: 7629196
    Abstract: A method is disclosed for manufacturing an integrated circuit that has increased radiation hardness and reliability. A device active area of an integrated circuit is provided and a layer of radiation resistant material is applied to the device active area of the integrated circuit. In one advantageous embodiment the radiation resistant material is silicon carbide. In another advantageous embodiment a passivation layer is placed between the device active area and the layer of radiation resistant material. The integrated circuit of the present invention exhibits minimal sensitivity to (1) enhanced low dose rate sensitivity (ELDRS) effects of radiation, and (2) pre-irradiation elevated temperature stress (PETS) effects of radiation.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: December 8, 2009
    Assignee: National Semiconductor Corporation
    Inventor: Michael C. Maher
  • Patent number: 7625777
    Abstract: In an embodiment, a memory device, with a highly integrated cell stricture, includes a mold insulating layer disposed on a semiconductor substrate. At least one conductive line is disposed on the mold insulating layer. Data storage elements self-aligned with the conductive line are interposed between the conductive line and the mold insulating layer. In this case, each of the data storage elements may include a resistor pattern and a barrier pattern, which are sequentially stacked, and the resistor pattern may be self-aligned with the barrier pattern.
    Type: Grant
    Filed: July 3, 2006
    Date of Patent: December 1, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-Ho Lee, Jae-Hee Oh, Jae-Hyun Park
  • Patent number: 7622162
    Abstract: Using UV radiation, methods to modify shallow trench isolation (STI) film tensile stress to generate channel strain without adversely impacting the efficiency of the transistor fabrication process are disclosed. Methods involve a two phase process: a deposition phase, wherein silanol groups are formed in the silicon dioxide film, and a bond reconstruction phase, wherein UV radiation removes silanol bonds and induce tensile stress in the silicon dioxide film.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: November 24, 2009
    Assignee: Novellus Systems, Inc.
    Inventors: Bart van Schravendijk, Seon-Mee Cho
  • Publication number: 20090286374
    Abstract: A base layer is formed on an insulating substrate, and a semiconductor layer is formed in localized fashion thereon. A gate insulating film is then formed so as to cover the semiconductor layer, and a gate electrode is formed on a portion of the gate insulating film. An impurity is then implanted into the semiconductor layer via the gate insulating film, and a source region, a drain region, and an LDD region are formed. The gate insulating film is etched with dilute hydrofluoric acid. An electrode-protecting insulating film is then formed so as to cover the gate electrode, and the entire surface of the surface layer portion of the electrode-protecting insulating film is etched away using dilute hydrofluoric acid. Carrier traps introduced into the electrode-protecting insulating film and the gate insulating film are thereby removed.
    Type: Application
    Filed: July 24, 2009
    Publication date: November 19, 2009
    Applicants: NEC CORPORATION, NEC LCD TECHNOLOGIES, LTD
    Inventors: Shigeru MORI, Takahiro KORENARI, Tadahiro MATSUZAKI, Hiroshi TANABE
  • Publication number: 20090286375
    Abstract: A method of forming sidewall spacers for a gate in a semiconductor device includes re-oxidizing/annealing silicon of the substrate and silicon of the gate after formation of the gate. The substrate is re-oxidized by performing an anneal in an inert atmosphere or ambient. The substrate may be re-oxidized/annealing after depositing an oxide layer covering the substrate and gate. Additionally, the substrate may be re-oxidized/annealing after forming the gate without depositing the oxide layer.
    Type: Application
    Filed: May 19, 2008
    Publication date: November 19, 2009
    Inventors: Mahalingam Nandakumar, Said Ghneim, Frank Scott Johnson
  • Patent number: 7618904
    Abstract: When a laser beam is irradiated onto a semiconductor film, a steep temperature gradient is produced between a substrate and the semiconductor film. For this reason, the semiconductor film contracts, so that a warp in the film occurs. Therefore, the quality of a resulting crystalline semiconductor film sometimes deteriorates. According to the present invention, it is characterized in that, after laser beam crystallization on the semiconductor film, heat treatment is carried out so as to reduce the warp in the film. Since the substrate contracts by the heat treatment, the warp in the semiconductor film is lessened, so that the physical properties of the semiconductor film can be improved.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: November 17, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Mitsuki, Tamae Takano
  • Patent number: 7608516
    Abstract: A pixel structure is described, comprising at least two selection switches coupled in series to improve the yield of the pixel. Also an array comprising such pixel structures logically organized in rows and columns is described, as well as a method for selecting a row or column of pixel structures in such an array.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: October 27, 2009
    Assignee: Cypress Semiconductor Corporation
    Inventor: Guy Meynants
  • Patent number: 7608873
    Abstract: A 3-T buried-gated photodiode device that is suitable for use in a windowed array. The 3-T buried-gated photodiode device is configured such that the floating diffusion (FD) node of the device is held low when the device is not being specifically addressed, which ensures that the device cannot drive the corresponding pixel output line unless it is specifically addressed.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: October 27, 2009
    Assignee: Aptina Imaging Corporation
    Inventor: Jeffery S. Beck
  • Publication number: 20090263950
    Abstract: A semiconductor device includes: a p-channel MIS transistor including: a first insulating layer formed on a semiconductor region between a source region and a drain region, and containing at least silicon and oxygen; a second insulating layer formed on the first insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, and a first gate electrode formed on the second insulating layer. The first and second insulating layers have a first and second region respectively. The first and second regions are in a 0.3 nm range in the film thickness direction from an interface between the first insulating layer and the second insulating layer. Each of the first and second regions include aluminum atoms with a concentration of 1×1020 cm?3 or more to 1×1022 cm?3 or less.
    Type: Application
    Filed: June 25, 2009
    Publication date: October 22, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masato Koyama, Yoshinori Tsuchiya, Yuuichi Kamimuta, Reika Ichihara, Katsuyuki Sekine
  • Patent number: 7588990
    Abstract: A plasma enhanced physical vapor deposition process deposits an amorphous carbon layer on an ion-implanted wafer for use in dynamic surface annealing of the wafer with an intense line beam of a laser wavelength. The deposition process is carried out at a wafer temperature below the dopant clustering threshold temperature, and includes introducing the wafer into a chamber and furnishing a hydrocarbon process gas into the chamber, preferably propylene (C3H6) or toluene (C7H8) or acetylene (C2H2) or a mixture of acetylene and methane (C2H4). The process further includes inductively coupling RF plasma source power into the chamber while and applying RF plasma bias power to the wafer. The wafer bias voltage is set to a level at which the amorphous carbon layer that is deposited has a desired stress (compressive or tensile). We have discovered that at a wafer temperature less than or equal to 475 degrees C.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: September 15, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Vijay Parihar, Christopher Dennis Bencher, Rajesh Kanuri, Marlon E. Menezes
  • Patent number: 7585714
    Abstract: It is an object of the present invention to provide a laser irradiation apparatus being able to crystallize the semiconductor film homogeneously while suppressing the variation of the crystallinity in the semiconductor film and the unevenness of the state of the surface thereof. It is another object of the present invention to provide a method for manufacturing a semiconductor device using the laser irradiation apparatus which can suppress the variation of on-current, mobility, and threshold of TFT, and to further provide a semiconductor device manufactured with the manufacturing method.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: September 8, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Osamu Nakamura, Hironobu Shoji
  • Publication number: 20090206404
    Abstract: Reducing external resistance of a multi-gate device by silicidation is generally described. In one example, an apparatus includes a semiconductor substrate, a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin having a first surface, a second surface, and a third surface, the multi-gate fin also having a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions wherein the source and drain regions of the multi-gate fin are fully or substantially silicized with a metal silicide, and a spacer dielectric material coupled to the first surface and the second surface wherein the spacer dielectric material substantially covers the first surface and the second surface in the source and drain regions.
    Type: Application
    Filed: February 15, 2008
    Publication date: August 20, 2009
    Inventors: Ravi Pillarisetty, Jack T. Kavalieros, Titash Rakshit, Robert S. Chau, Uday Shah
  • Patent number: 7575985
    Abstract: In a manufacturing process of a semiconductor device using a substrate having low heat resistance, such as a glass substrate, there is provided a method of efficiently carrying out crystallization of a semiconductor film and gettering treatment of a catalytic element used for the crystallization by a heating treatment in a short time without deforming the substrate. A heating treatment method of the present invention is characterized in that a light source is controlled in a pulsed manner to irradiate a semiconductor film, so that a heating treatment of the semiconductor film is efficiently carried out in a short time, and damage of the substrate due to heat is prevented.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: August 18, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Tamae Takano, Koji Dairiki
  • Patent number: 7575986
    Abstract: Defects and fixed charge in a gate dielectric near the gate dielectric-substrate interface are reduced by performing a gate dielectric relaxation anneal step prior to source-drain ion implantation, in which the wafer temperature is ramped gradually to near a melting temperature of the substrate equal to a peak post-ion implantation anneal peak temperature. The ramping rates are sufficiently gradual so that the gate dielectric is held above its reflow temperature for a significant duration.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: August 18, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Christopher Sean Olsen, Sunderraj Thirupapuliyur
  • Patent number: 7575979
    Abstract: A method includes forming a fluid including an inorganic semiconductor material, depositing a layer of said fluid on a substrate to form a film, and curing said film to form a porous semiconductor film.
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: August 18, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: David Punsalan, Peter Mardilovich, Randy Hoffman
  • Patent number: 7569458
    Abstract: A method of non-thermal annealing of a silicon wafer comprising irradiating a doped silicon wafer with electromagnetic radiation in a wavelength or frequency range coinciding with lattice phonon frequencies of the doped semiconductor material. The wafer is annealed in an apparatus including a cavity and a radiation source of a wavelength ranging from 10-25 ?m and more particularly 15-18 ?m, or a frequency ranging from 12-30 THz and more particularly 16.5-20 THz.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: August 4, 2009
    Assignee: Atmel Corporation
    Inventors: Bohumil Lojek, Michael D. Whiteman
  • Patent number: 7566625
    Abstract: For manufacture of a semiconductor device using a low heat resistant substrate such as a glass substrate, a method of heat treatment for activating an impurity element that is used to dope a semiconductor film and for performing gettering on the semiconductor film in a short period of time without deforming the substrate, is provided. Also provided is a heat treatment apparatus for carrying out the above heat treatment. The heat treatment method of the present invention involves irradiating an object with light emitted from a lamp light source, and is characterized in that the lamp light source emits light for 0.1 to 20 seconds at a time and that light from the lamp light source irradiates the object several times. The method is also characterized in that the irradiated region is subjected to pulsating light from the lamp light source such that the irradiated region holds the temperature to its highest for 0.5 to 5 seconds.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: July 28, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Koji Dairiki
  • Patent number: 7560354
    Abstract: A process can include forming a doped semiconductor layer over a substrate. The process can also include performing an action that reduces a dopant content along an exposed surface of a workpiece that includes the substrate and the doped semiconductor layer. The action is performed after forming the doped semiconductor layer and before the doped semiconductor layer is exposed to a room ambient. In particular embodiments, the doped semiconductor layer includes a semiconductor material that includes a combination of at least two elements selected from the group consisting of C, Si, and Ge, and the doped semiconductor layer also includes a dopant, such as phosphorus, arsenic, boron, or the like. The action can include forming an encapsulating layer, exposing the doped semiconductor layer to radiation, annealing the doped semiconductor layer, or any combination thereof.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: July 14, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Stefan Zollner, Bich-Yen Nguyen
  • Publication number: 20090162985
    Abstract: Methods of fabricating a semiconductor device are provided. An insulating layer can be formed on a semiconductor substrate, a sacrificial layer can be formed on the insulating layer, and a trench can be formed in the sacrificial layer. A first gate material layer can be formed on the sacrificial layer and in the trench, and a second gate material layer can be formed on the first gate material layer. A gate electrode can be formed by reacting the first gate material layer and the second gate material layer.
    Type: Application
    Filed: October 27, 2008
    Publication date: June 25, 2009
    Inventor: Dae Young Kim
  • Publication number: 20090127584
    Abstract: Source and drain electrodes are each formed by an alternation of first and second layers made from a germanium and silicon compound. The first layers have a germanium concentration comprised between 0% and 10% and the second layers have a germanium concentration comprised between 10% and 50%. At least one channel connects two second layers respectively of the source electrode and drain electrode. The method comprises etching of source and drain zones, connected by a narrow zone, in a stack of layers. Then superficial thermal oxidation of said stack is performed so a to oxidize the silicon of the germanium and silicon compound having a germanium concentration comprised between 10% and 50% and to condense the germanium Ge. The oxidized silicon of the narrow zone is removed and a gate dielectric and a gate are deposited on the condensed germanium of the narrow zone.
    Type: Application
    Filed: May 23, 2006
    Publication date: May 21, 2009
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE, STMICROELECTRONICS SA
    Inventors: Yves Morand, Thierry Poiroux, Maud Vinet
  • Patent number: 7531459
    Abstract: Methods of forming a metal salicide layer can include forming a metal layer on a substrate and forming a metal silicide layer on the metal layer using a first thermal process at a first temperature. Then a second process is performed, in-situ with the first thermal process, on the metal layer at a second temperature that is less than the first temperature.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: May 12, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sug-woo Jung, Gil-heyun Choi, Byung-hee Kim, Jong-ho Yun, Hyun-su Kim, Eun-ji Jung
  • Patent number: 7521326
    Abstract: It is an object of the present invention to provide a semiconductor device superior in the decrease in leak current due to a short-channel effect and a manufacturing method thereof. In a process of forming a field-effect transistor over a single-crystal semiconductor substrate, an impurity is introduced to form an extension region and a single crystal lattice is broken to make the extension region amorphous. Alternatively, the impurity and an element having large mass number are introduced to break the single crystal lattice and make the extension region amorphous. Then, a laser beam with a pulse width of 1 fs to 10 ps and a wavelength of 370 to 640 nm is delivered to selectively activate the amorphous portion, so that the extension region is formed with a thickness of 20 nm or less.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: April 21, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Koichiro Tanaka
  • Patent number: 7514333
    Abstract: A CMOS power sensor is disclosed in the present invention. The CMOS power sensor includes a current coil, a high voltage device circuit, and a Hall device. The current coil is fabricated during the process steps of forming gold bumps of a CMOS device. One end of the current coil is connected to a voltage source, and the other end of the current coil is connected to a load. The high voltage device circuit is connected to the voltage source. The Hall device is connected to the high voltage device circuit and induces a Hall voltage in response to the magnetic field generated by the current coil.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: April 7, 2009
    Assignee: Himax Technologies Limited
    Inventor: Hung-Ming Yang
  • Publication number: 20090065880
    Abstract: In one aspect there is provided a method of manufacturing a semiconductor device comprising forming gate electrodes over a semiconductor substrate, forming source/drains adjacent the gate electrodes, depositing a stress inducing layer over the gate electrodes. A laser anneal is conducted on at least the gate electrodes subsequent to depositing the stress inducing layer at a temperature of at least about 1100° C. for a period of time of at least about 300 microseconds, and the semiconductor device is subjected to a thermal anneal subsequent to conducting the laser anneal.
    Type: Application
    Filed: September 11, 2007
    Publication date: March 12, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Amitabh Jain, Manoj Mehrotra
  • Patent number: 7498212
    Abstract: When the second harmonic of a YAG laser is irradiated onto semiconductor films, concentric-circle patterns are observed on some of the semiconductor films. This phenomenon is due to the non-uniformity of the properties of the semiconductor films. If such semiconductor films are used to fabricate TFTs, the electrical characteristics of the TFTs will be adversely influenced. A concentric-circle pattern is formed by the interference between a reflected beam 1 reflected at a surface of a semiconductor film and a reflected beam 2 reflected at the back surface of a substrate. If the reflected beam 1 and the reflected beam 2 do not overlap each other, such interference does not occur. For this reason, a laser beam is obliquely irradiated onto the semiconductor film to solve the interference. The properties of a crystalline silicon film formed by this method are uniform, and TFTs which are fabricated by using such crystalline silicon film have good electrical characteristics.
    Type: Grant
    Filed: October 20, 2006
    Date of Patent: March 3, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Koichiro Tanaka
  • Publication number: 20090042353
    Abstract: Post-laser annealing dopant deactivation is minimized by performing certain silicide formation process steps prior to laser annealing. A base metal layer of nickel is deposited on the source-drain regions and the gate electrode, followed by deposition of an overlying layer of a metal having a higher melting temperature than nickel. Thereafter, a rapid thermal process is performed to heat the substrate sufficiently to form metal silicide contacts at the top surfaces of the source-drain regions and of the gate electrode. The method further includes removing the remainder of the metal-containing layer and then depositing an optical absorber layer over the substrate prior to laser annealing.
    Type: Application
    Filed: August 9, 2007
    Publication date: February 12, 2009
    Inventors: Yi Ma, Philip Allan Kraus, Christopher Sean Olsen, Khaled Z. Ahmed, Abhilash J. Mayur
  • Publication number: 20090042352
    Abstract: Defects and fixed charge in a gate dielectric near the gate dielectric-substrate interface are reduced by performing a gate dielectric relaxation anneal step prior to source-drain ion implantation, in which the wafer temperature is ramped gradually to near a melting temperature of the substrate equal to a peak post-ion implantation anneal peak temperature. The ramping rates are sufficiently gradual so that the gate dielectric is held above its reflow temperature for a significant duration.
    Type: Application
    Filed: August 8, 2007
    Publication date: February 12, 2009
    Applicant: Applied Materials, Inc.
    Inventors: Christopher Sean Olsen, Sunderraj Thirupapuliyur
  • Publication number: 20090042354
    Abstract: Post-laser annealing dopant deactivation is minimized by performing certain silicide formation process steps prior to laser annealing. A base metal layer is deposited on the source-drain regions and the gate electrode, followed by deposition of an overlying compression cap layer, to prevent metal agglomeration at the silicon melting temperature. Thereafter, a rapid thermal process is performed to heat the substrate sufficiently to form metal silicide contacts at the top surfaces of the source-drain regions and of the gate electrode. The method further includes removing the remainder of the metal-containing layer and then depositing an optical absorber layer over the substrate prior to laser annealing near the silicon melting temperature.
    Type: Application
    Filed: August 9, 2007
    Publication date: February 12, 2009
    Inventors: YI Ma, Philip Allan Kraus, Christopher Sean Olsen, Khaled Z. Ahmed, Abhilash J. Mayur
  • Patent number: 7482587
    Abstract: The present invention disclosure relates to the use of a silicon substrate with a thin film membrane as a transparent substrate for the imaging of biological- and material-related specimens using a microscope such as a transmission electron microscope (TEM). More specifically, the present invention relates to an improved substrate design that incorporates the fabrication of a circular shape that allows easier insertion into traditional specimen holders used in TEMs. In addition to an improved shape, the present invention incorporates microscopic surface texture on the gripping surface that assists in handling. The invention also encompasses surface modification techniques for enhanced biocompatibility of the thin film membrane for biomedical applications.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: January 27, 2009
    Inventor: Dudley Sean Finch
  • Patent number: 7482552
    Abstract: A laser crystallizing device including a mask divided into two regions, having open parts of the same shape at complementary positions; and a light-shielding pattern selectively leaving one region of the mask open and masking the other region.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: January 27, 2009
    Assignee: LG Display Co., Ltd.
    Inventor: Yun Ho Jung
  • Patent number: 7479465
    Abstract: A strained semiconductor layer is achieved by a method for transferring stress from a dielectric layer to a semiconductor layer. The method comprises providing a substrate having a semiconductor layer. A dielectric layer having a stress is formed over the semiconductor layer. A radiation anneal is applied over the dielectric layer of a duration not exceeding 10 milliseconds to cause the stress of the dielectric layer to create a stress in the semiconductor layer. The dielectric layer may then be removed. At least a portion of the stress in the semiconductor layer remains in the semiconductor layer after the dielectric layer is removed. The radiation anneal can be either by using either a laser beam or a flash tool. The radiation anneal can also be used to activate source/drain regions.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: January 20, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gregory S. Spencer, Venkat R. Kolagunta, Narayanan C. Ramani, Vishal P. Trivedi
  • Publication number: 20090011566
    Abstract: After gate insulating films, gate electrodes, and n+ type semiconductor regions and p+ type semiconductor regions for source/drain are formed, a metal film and a barrier film are formed on a semiconductor substrate. And a first heat treatment is performed so as to make the metal film react with the gate electrodes, the n+ type semiconductor region, and the p+ type semiconductor region, thereby forming a metal silicide layer formed of a monosilicide of a metal element forming the metal film. After that, the barrier film and the unreacted metal film are removed, and then a second heat treatment is performed to stabilize the metal silicide layer. The heat treatment temperature is made lower than a temperature at which a lattice size of a disilicide of the metal element and that of the semiconductor substrate become same.
    Type: Application
    Filed: July 3, 2008
    Publication date: January 8, 2009
    Inventors: Shigenari Okada, Takuya Futase
  • Patent number: 7468304
    Abstract: A method for fabricating a device using an oxide semiconductor, including a process of forming the oxide semiconductor on a substrate and a process of changing the conductivity of the oxide semiconductor by irradiating a predetermined region thereof with an energy ray.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: December 23, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventors: Nobuyuki Kaji, Hisato Yabuta
  • Patent number: 7465614
    Abstract: A semiconductor device and method of fabricating the same are provided. The method includes: depositing a silicon layer containing amorphous silicon on a substrate; partially crystallizing the amorphous silicon by applying an annealing process to the silicon layer under an atmosphere of H2O at a predetermined temperature; forming a polycrystalline silicon layer by applying an laser annealing process to the partially crystallized amorphous silicon layer; forming a gate insulating layer on the polycrystalline silicon layer; and forming a gate electrode on the gate insulating layer, so that a substrate is prevented from being bent due to high temperature crystallization while the amorphous silicon is crystallized through an SPC process, thereby reducing defects of the thin film transistor.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: December 16, 2008
    Assignee: Samsung SDI Co., Ltd.
    Inventor: Ramesh Kakkad
  • Patent number: 7465635
    Abstract: The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among other steps, may include forming a gate structure over a substrate, forming at least a portion of gate sidewall spacers proximate sidewalls of the gate structure, and subjecting the at least a portion of the gate sidewall spacers to an energy beam treatment, the energy beam treatment configured to change a stress of the at least a portion of the gate sidewall spacers, and thus change a stress in the substrate therebelow.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: December 16, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Puneet Kohli, Manoj Mehrotra, Jin Zhao, Sameer Ajmera
  • Publication number: 20080305601
    Abstract: A composite dielectric layer including a nitride layer over an oxide layer serves the dual function of acting as an SMT (stress memorization technique) film while an annealing operation is carried out and then remains partially intact as it is patterned to further serve as an RPO film during a subsequent silicidation process. The need to form and remove two separate dielectric material layers is obviated. The nitride layer protects the oxide layer to alleviate oxide damage during a pre-silicidation PAI (pre-amorphization implant) process thereby preventing oxide attack during a subsequent HF dip operation and preventing nickel silicide spiking through the attacked oxide layer during silicidation.
    Type: Application
    Filed: June 6, 2007
    Publication date: December 11, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jyh-Huei Chen
  • Publication number: 20080305600
    Abstract: A method and an apparatus for fabricating a high tensile stress film includes providing a substrate, forming a poly stressor on the substrate, and performing an ultra violet rapid thermal process (UVRTP) for curing the poly stressor and adjusting its tensile stress status, thus the poly stressor serves as a high tensile stress film. Due to a combination of energy from photons and heat, the tensile stress status of the high tensile stress film is adjusted in a relatively shorter process period or under a relatively lower temperature.
    Type: Application
    Filed: June 5, 2007
    Publication date: December 11, 2008
    Inventors: Hsiu-Lien Liao, Neng-Kuo Chen, Teng-Chun Tsai, Yi-Wei Chen
  • Patent number: 7462542
    Abstract: A method of fabricating semiconductor devices is provided. A plurality of gate structures is formed over a substrate. A source region and a drain region are formed in the substrate and adjacent to sidewalls of each gate structure. A self-aligned salicide block (SAB) layer is formed over the substrate to cover the gate structures and the exposed surface of the substrate. An anneal process is performed. The SAB layer creates a tension stress during the anneal process so that the substrate under the gate structures is subjected to the tension stress. A portion of the SAB layer is removed to expose a portion of the gate structures and a portion of the surface of the substrate. A salicide process is performed.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: December 9, 2008
    Assignee: United Microelectronics Corp.
    Inventors: Alex Liu, Cheng-Tung Huang, Wei-Tsun Shiau, Kuan-Yang Liao
  • Patent number: 7460932
    Abstract: A computer implemented method, data processing system, and processor are provided for managing a thermal management system. A determination is made as to whether a plurality of digital thermal sensors is faulty or functional. A power savings mode of at least one unit within the integrated circuit associated with the functional digital thermal sensor is monitored in response to at least one of the plurality of digital thermal sensors being functional. A functional digital thermal sensor is disabled in response to the at least one unit being in a power savings mode.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: December 2, 2008
    Assignee: International Business Machines Corporation
    Inventors: Charles Ray Johns, Michael Fan Wang
  • Publication number: 20080293208
    Abstract: A method for fabricating a device using an oxide semiconductor, including a process of forming the oxide semiconductor on a substrate and a process of changing the conductivity of the oxide semiconductor by irradiating a predetermined region thereof with an energy ray.
    Type: Application
    Filed: July 29, 2008
    Publication date: November 27, 2008
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: NOBUYUKI KAJI, HISATO YABUTA
  • Publication number: 20080293193
    Abstract: Provided is a method for manufacturing a semiconductor device that includes forming a gate structure over a substrate, wherein the gate structure includes a gate dielectric and a gate electrode. The method further includes forming a metal layer over the gate electrode, and forming a fully silicided gate electrode using the metal layer. The fully silicided gate electrode may be formed by subjecting the gate electrode to a first anneal in a presence of the metal layer to form a silicided gate electrode, wherein a maximum temperature of the first anneal does not exceed about 340° C. The fully silicided gate electrode may further be formed by removing any unreacted portions of the metal layer after the first anneal, and subjecting the silicided gate electrode to a second anneal to form the fully silicided gate electrode subsequent to the removing. A maximum temperature of the second anneal exceeds about 400° C.
    Type: Application
    Filed: May 23, 2007
    Publication date: November 27, 2008
    Applicant: Texas Instruments Inc.
    Inventors: Mark Visokay, Jorge Adrian Kittl
  • Publication number: 20080268603
    Abstract: A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.
    Type: Application
    Filed: April 30, 2007
    Publication date: October 30, 2008
    Inventors: Hiroaki NIIMI, Jarvis Benjamin Jacobs, Ajith Varghese
  • Publication number: 20080268597
    Abstract: By performing multiple radiation-based anneal processes on the basis of less critical process parameters, the overall risk for creating anneal-induced damage, such as melting of gate portions, may be substantially avoided while nevertheless the respective degree of dopant activation may be enhanced for each individual anneal process. Consequently, the sheet resistance of advanced transistor devices may be reduced with a decreasing number of sequential anneal processes.
    Type: Application
    Filed: December 26, 2007
    Publication date: October 30, 2008
    Inventors: Andy Wei, Thomas Feudel, Casey Scott
  • Patent number: 7442615
    Abstract: Systems and methods are disclosed to perform semiconductor processing with a process chamber; a flash lamp adapted to be repetitively triggered; and a controller coupled to the control input of the flash lamp to trigger the flash lamp. The system can deploy a solid state plasma source in parallel with the flash lamp in wafer processing.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: October 28, 2008
    Assignee: Tegal Corporation
    Inventors: Tue Nguyen, Tai Dung Nguyen, Craig Alan Bercaw
  • Patent number: 7439114
    Abstract: For obtaining p-Si by irradiating a laser beam to an a-Si layer to polycrystallize, an energy level in a region to be irradiated by the laser beam is set such that a level at the rear area of the region along a scan direction of the laser beam is lower than that at the front area or the center area of the region. The energy level at the front area or the center area of the region is set such that it is substantially equal to or more than the upper limit energy level which maximizes a grain size of the p-Si obtained. Since an energy profile is set as described above, when the laser beam is scanned on the a-Si layer, an irradiated energy of the laser on the region is gradually lowered from the upper limit as the laser beam passes through, which allows the semiconductor layer to be annealed within an optimal energy level during the latter half of the annealing process.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: October 21, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hidenori Ogata, Ken Wakita, Kiyoshi Yoneda, Yoshihiro Morimoto, Tsutomu Yamada, Kazuhiro Imao, Takashi Kuwahara
  • Publication number: 20080254588
    Abstract: A method for forming a semiconductor structure includes forming a gate dielectric layer over a substrate. A top surface of the gate dielectric layer is treated so as to at least partially nitridize the gate dielectric layer. The treated gate dielectric layer is thermally treated with an oxygen-containing precursor such that the at least partially nitridized gate dielectric layer has a nitrogen concentration between about 0.5 atomic percentage (at. %) and about 20 at %.
    Type: Application
    Filed: April 16, 2007
    Publication date: October 16, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Harry Chuang, Kong-Beng Thei, Hung-Chih Tsai, M. Y. Wu, Mong-Song Liang
  • Patent number: 7435635
    Abstract: A semiconductor material and a method for forming the same, said semiconductor material having produced by a process comprising melting a noncrystal semiconductor film containing therein carbon, nitrogen, and oxygen each at a concentration of 5×1019 atoms·cm?3 or lower, preferably 1×1019 atoms·cm?3 or lower, by irradiating a laser beam or a high intensity light equivalent to a laser beam to said noncrystal semiconductor film, and then recrystallizing the thus molten amorphous silicon film. The present invention provides thin film semiconductors having high mobility at an excellent reproducibility, said semiconductor materials being useful for fabricating thin film semiconductor devices such as thin film transistors improved in device characteristics.
    Type: Grant
    Filed: April 14, 2005
    Date of Patent: October 14, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hongyong Zhang, Naoto Kusumoto, Yasuhiko Takemura
  • Patent number: 7435658
    Abstract: A method of manufacturing a MOS transistor is provided. A substrate having a gate structure thereon is provided. A first spacer is formed on the sidewall of the gate structure. A pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer. A doped source/drain region is formed in the substrate on each side of the second spacer. Thereafter, a solid phase epitaxial process is carried out to re-crystallize the amorphized portion of the substrate and activate the doped source/drain extension region and the doped source/drain region to form a source/drain terminal. Finally, a post-annealing operation is performed.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: October 14, 2008
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Ren Wang, Chin-Cheng Chien, Hsiang-Ying Wang, Neng-Hui Yang
  • Publication number: 20080242020
    Abstract: A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate and a gate structure positioned on the semiconductor substrate are prepared first. A source region and a drain region are included in the semiconductor substrate on two opposite sides of the gate structure. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure, the source region and the drain region. Next, an inert gas treatment is performed to change a stress value of the stressed cap layer. Because the stress value of the stressed cap layer can be adjusted easily by means of the present invention, one stressed cap layer can be applied to both the N-type MOS transistor and the P-type MOS transistor.
    Type: Application
    Filed: March 28, 2007
    Publication date: October 2, 2008
    Inventors: Jei-Ming Chen, Neng-Kuo Chen, Hsiu-Lien Liao, Teng-Chun Tsai, Chien-Chung Huang, Shih-Wei Sun
  • Publication number: 20080230841
    Abstract: An integrated circuit system that includes: providing a gate and a spacer formed over a substrate; performing an implant that amorphizes the gate and a source/drain region defined by the spacer; removing the spacer; depositing a stress memorization layer over the integrated circuit system; and transferring a stress from the stress memorization layer to the gate and the source/drain region.
    Type: Application
    Filed: March 21, 2007
    Publication date: September 25, 2008
    Applicant: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Elgin Kiok Boone Quek, Pradeep Ramachandramurthy Yelehanka