Abstract: A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The process relies on techniques for depositing semiconductors, dielectrics, and metals at low temperatures; crystallizing and doping semiconductor layers in the TFT with a pulsed energy source; and creating top-gate self-aligned as well as back-gate TFT structures. The process enables the fabrication of amorphous and polycrystalline channel silicon TFTs at temperatures sufficiently low to prevent damage to plastic substrates. The process has use in large area low cost electronics, such as flat panel displays and portable electronics.

Abstract: In a substrate having an insulating surface in which an amorphous semiconductor film is deposited on the insulating surface, a predetermined under-heating portion of the amorphous semiconductor film is partially heated with a heating source emitting heating rays. While heating, the under-heating portion is shifted by moving the heating source or the substrate. Accordingly, the amorphous semiconductor film is sequentially heat-treated and polycrystallized. As the under-heating portion shifts, the polycrystallization sequentially proceeds using the already polycrystallized portion by irradiation with the heating rays, which is adjacent to the under-heating portion, as seed crystal. Thus, the growth condition of crystal grains is uniformly controlled in the shifting direction of the under-heating portion.

Abstract: In a thin film transistor (TFT), a part of a surface or a whole surface of aluminum used as a gate electrode is covered by anodic oxide. In a process after anodization process, ultraviolet light is irradiated to a gate electrode in an oxidizing atmosphere containing oxygen, ozone, or nitrous oxide. Or, in a process after anodization process, a TFT is leaved (placed) in plasma in an oxidizing atmosphere. Or, ultraviolet light is irradiated to a gate electrode in plasma in an oxidizing atmosphere. A substrate temperature is a room temperature (50.degree. C.) to 500.degree. C., for example, 200.degree. to 300.degree. C. By ultraviolet light irradiation or plasma processing, metallic aluminum contained in anodic oxide is oxidized.

Abstract: The present invention relates to a process for the production of a random access memory of the preloading static type, in which use is made of a static random access memory constituted by MOS transistors formed from the memory flip-flop array and in which a particle or photon beam is applied to the said MOS transistors in such a way that the accumulated dose received exceeds a predetermined value.

Abstract: This invention relates to a semiconductor device and method for fabricating the semiconductor device, for forming a source and drain structure having no side diffusion. The semiconductor device includes a silicon substrate, a gate formed on the silicon substrate with a gate insulation film in between, and a source and drain formed of conductive material layers buried in the substrate to a designated depth at opposite sides of the gate, thereby providing a source with no side diffusion, preventing reduction of channel length, and improving element integration.

Abstract: This invention describes a manufacturing method for MOSFET devices that are free from reverse short channel effect usually found in such devices made by prior art processes. In contrast to the prior art process sequence, the channel implant is made after the source and drain already formed by implantation and its damage already annealed out. The enhanced diffusion of the channel implant, caused by damage generated point defects and responsible for the reverse short channel effect, is therefore avoided. The channel implantation uses high energy ions to penetrate through the polysilicon gate, forming a threshold voltage adjustment and punch-through barrier layer under the gate. The channel implant through the source/drain regions is deeper than the source/drain junctions so that the junction capacitance is reduced in comparison with the prior art.

Abstract: First, a non-doped AlGaAs layer and an n-GaAs layer serving as a conductive layer are formed in order on the surface of a semi-insulating GaAs substrate. Then, a photoresist film having an opening in its predetermined position is formed on the surface of the n-GaAs layer. Then, an electron beam is applied from the upside of the photoresist film by using the photoresist film as a mask. Thereby, a melted layer made of uniform AlGaAs is formed in a region of the n-GaAs layer, non-doped AlGaAs layer and upper portion of the GaAs substrate, which is under the opening 24a. Thereafter, the melted layer is recrystallized. In this case, the melted layer is formed into an amorphous or polycrystalline layer on the GaAs substrate and an device isolation layer is formed.

Abstract: There is disclosed a method for forming an ultra-shallow junction of a semiconductor device, comprising a four-stage RTA process following the ion implantation of dopants for source/drain junction, the RTA process being carried out with high temperature-elevating and -quenching rates between the stages, in such a way that relatively low temperatures are used for a short time in the first three stages in order to eliminate only the point defects, which greatly affect the diffusion of dopants, without diffusion of dopants while a relatively high temperature is taken in the last stage with the aim of allowing the dopants to diffuse a little to p.sup.+ and n.sup.+ shallow junctions, thereby obtaining an improvement in electrical activity and reducing junction current leakage and thus, improving the properties and reliability of the resulting semiconductor device.

Abstract: A crystalline silicon thin film transistor having an LDD (lightly doped drain) structure and a process for fabricating the same, which comprises establishing an LDD by forming a gate insulating film and a gate electrode on an island-like semiconductor region and implanting thereafter impurities in a self-aligned manner to establish an LDD, anodically oxidizing the gate electrode and introducing impurities to form source and drain regions, partially or wholly removing the anodic oxide from the surface of the island-like semiconductor region to expose the LDD region, and irradiating a laser beam or an intense light having an intensity equivalent to that of the laser beam to activate the impurity region inclusive of the LDD.

Abstract: A method for forming a polycrystalline semiconductor thin film according to the present invention includes the steps of: forming a semiconductor thin film partially containing microcrystals serving as crystal nuclei for polycrystallization on an insulating substrate; and polycrystallizing the semiconductor thin film by laser annealing.

Abstract: In producing a semiconductor device using silicon semiconductor, thermal processing is performed in an atmosphere containing hydrogen. At this time, active hydrogen is generated by contacting the hydrogen to a heated nickel material. For example, a pipe which an inner surface thereof is covered with the nickel material is heated by a heater and a hydrogen gas is introduced into the pipe, in order to generate the active hydrogen, so that a semiconductor device formed on a resin substrate having a low heat resistance is annealed using the active hydrogen while maintaining at 150.degree. C. .+-.20.degree. C. for a desired period of time.

Abstract: A semiconductor material and a method for forming the same, said semiconductor material having produced by a process comprising melting a noncrystal semiconductor film containing therein carbon, nitrogen, and oxygen each at a concentration of 5.times.10.sup.19 atoms.cm.sup.-3 or lower, preferably 1.times.10.sup.19 atoms.cm.sup.-3 or lower, by irradiating a laser beam or a high intensity light equivalent to a laser beam to said noncrystal semiconductor film, and then recrystallizing the thus molten amorphous silicon film. The present invention provides thin film semiconductors having high mobility at an excellent reproducibility, said semiconductor materials being useful for fabricating thin film semiconductor devices such as thin film transistors improved in device characteristics.

Abstract: A method of forming a bottom gated TFT includes, a) providing a transistor gate relative to a substrate which projects outward thereof; b) providing a dielectric layer over the gate; c) providing a TFT layer of semiconductive material over the dielectric layer; the thin film transistor layer comprising a source area, a channel area, a drain area, and a drain offset area; d) providing a masking layer over the TFT layer; e) anisotropically etching the masking layer to define a masking sidewall spacer laterally adjacent the transistor gate over the drain offset area and leave the channel area outwardly exposed; f) with the masking sidewall spacer in place, implanting a conductivity enhancing impurity of a first type into the thin film channel area to provide a thin film channel region; and g) masking the channel area and the drain offset area while implanting conductivity enhancing impurity of a second type into the thin film source and drain areas to define thin film source and channel regions.

Abstract: A process is provided in which silicon thin film transistors fabricated with polycrystalline silicon, silicon oxide, and silicon conductive layers are exposed to microwave plasmas containing water vapor and to subsequent annealing steps to bring about an improvement in the ratio of device drain current in the conductive state to that in the non-conductive state, and a lower device subthreshold voltage swing.

Abstract: A gate structure in a transistor and method for fabricating the structure. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure.

Abstract: The failure rate of semiconductor devices containing UPROM transistors is improved by erasing the UPROM transistors using X-rays. The semiconductor devices are subsequently exposed to UV radiation to erase other transistors charged during X-ray exposure.

Abstract: A method of forming a field effect transistor relative to a monocrystalline silicon substrate, where the transistor has an elevated source and an elevated drain, includes: a) providing a transistor gate over the monocrystalline silicon substrate, the gate being encapsulated in electrically insulative material; b) providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; c) cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; d) within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing a conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and e) after chemical vapor depositing, exposing the doped non-polycrystalline silico

Abstract: A semiconductor device having shallow junction, in which carrier concentration will not be reduced, sheet resistance will not be increased, and contact characteristic at a surface will not become inferior, is provided. A gate electrode is provided on a semiconductor substrate. At a surface of semiconductor substrate, a pair of source/drain layers having top and bottom surfaces are provided on both sides of gate electrode. In source/drain layer, a secondary-defect layer which extends horizontally is formed between top surface and bottom surface.

Abstract: A process for fabricating a non-volatile memory cell (10) in a semiconductor device includes the formation of a doped region (28) in a semiconductor substrate (40) underlying a floating gate electrode (16) and separated therefrom by a tunnel dielectric layer (44). Stress induced failure of the tunnel dielectric layer (44) is avoided by laterally diffusing dopant atoms under the floating gate electrode (16) after completely fabricating both the floating gate electrode (16) and the underlying tunnel dielectric layer (44).

Abstract: Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.