Abstract: Rapid thermal anneal with a gaseous dopant species for formation of a shallow lightly doped region is disclosed. In one embodiment of the invention, a method includes four steps. In the first step, at least one layer is applied over at least one gate over a semiconductor substrate. In the second step, an ion implantation is performed to form source and drain regions within the substrate. In the third step, the layers are removed. In the fourth step, a rapid thermal anneal with a gaseous dopant species is performed to form lightly doped regions within the substrate.

Abstract: An embodiment of the instant invention is a method of fabricating an electronic device over a semiconductor substrate, the method comprising the steps of: forming a doped polycrystalline silicon layer insulatively disposed over the semiconductor substrate; and subjecting the doped polycrystalline silicon layer to a temperature of around 700 to 1100 C. in an oxidizing ambient for a period of around 5 to 120 seconds. Preferably, the oxidizing ambient is comprised of: O2,O3, NO, N2O, H2O, and any combination thereof. The temperature is, preferably, around 950 to 1050 C. (more preferably around 1000 C.). The step of subjecting the doped polycrystalline silicon layer to a temperature of around 700 to 1100 C. in an oxidizing ambient for a period of around 5 to 120 seconds, preferably, forms an oxide layer on the polycrystalline silicon layer, which has a thickness which is, preferably, greater than the thickness of a native oxide layer.

Abstract: This invention comprises improvements in the ways in which spin-on dielectric layers are cured. A semiconductor wafer is coated with a precursor for a spin-on dielectric material, and after the solution is thinned and evened, the wafer is placed in a curing oven, optionally containing an inert gas, and pre-heated to a temperature below which excessive thermomechanical stresses and/or oxidation are not created in the semiconductor wafer. The temperature within the curing oven is then raised to a curing temperature, and thereafter the temperature is slowly lowered to prevent the formation of stress cracks and the loss of dielectric function of the thin film. The curing method of this invention is useful for the manufacture of semiconductor devices employing a variety of spin-on materials.

Abstract: A purchased silicon substrate 10 is subjected to D-HF treatment, SC-1 treatment, etc. to expose the surface of the silicon substrate 10. Then, the silicon substrate 10 having the surface exposed and containing grown-in defects 12 and micro oxygen precipitates 14 is subjected to oxygen out-diffusion annealing in an argon gas ambient. The annealing is performed, e.g., in an argon gas ambient, at a temperature of about 1000 to about 1300° C. for about 1 hour. Thus, the defects 12, 14 which are near the surface of the silicon substrate 10 are reduced, and the defects in the substrate surface can be decreased.

Abstract: A P-type impurity layer, a silicon monocrystal film, a silicon oxide film and a crystal silicon film are successively formed on a semiconductor substrate by introducing appropriate functional gases on the semiconductor substrate, while irradiating the semiconductor substrate with ionizing radiation or light at a temperature lower than 250° C. After forming a photoresist on the crystal silicon film at a temperature lower than 250° C., the resultant semiconductor substrate is subjected to etching by using the photoresist as a mask, so as to form a gate electrode B out of the silicon oxide film and a gate insulating film out of the silicon oxide film. Then, the resultant semiconductor substrate is subjected to etching again by using the gate electrode as a mask, so as to form a channel region out of the P-type impurity layer. A source electrode and a drain electrode are formed on the respective sides of the gate electrode on the semiconductor substrate by introducing an appropriate functional.

Abstract: In producing TFT by crystallizing an amorphous silicon film by the action of nickel, the influence of nickel on the TFT produced is inhibited. A mask 104 is formed over an amorphous silicon film 102, and a nickel-containing solution is applied thereover. In that condition, nickel is kept in contact with the surface of the amorphous silicon film at the opening 103 of the mask. Then, this is heated to crystallize the amorphous silicon film. Next, a phosphorus-containing solution is applied thereto, so that phosphorus is introduced into the silicon film in the region of the opening 103. This is again heated, whereby nickel is gettered in the region into which phosphorus has been introduced. In this process, the nickel concentration in the silicon film is reduced.

Abstract: A method for forming a polycide/oxide/polysilicon capacitor on a silicon wafer with improved dielectric stability and reliability is described wherein an in-situ high temperature anneal is applied to the wafer within a CVD reactor immediately prior to the deposition of the silicon oxide capacitor dielectric layer. The in-situ anneal causes sufficient fluorine outgassing of the polycide layer to prevent fluorine degradation of the subsequently deposited oxide capacitor dielectric. The capacitance of the completed capacitor is increased by as much as 10% when compared to a comparable not in-situ anneal conducted prior to the insertion of the wafer into the CVD reactor.

Abstract: In a semiconductor circuit using a silicon film in which crystals grow in the direction parallel to a substrate, the distance between the position of a starting region of crystal growth and the position of the respective active layers are made the same. Thus, the difference of the characteristics due to the difference of the distance of crystal growth is corrected.

Abstract: A method for forming a MOSFET device on a semiconductor substrate is disclosed here. First, a gate oxide layer, a polysilicon layer, a metal silicide layer and a silicon oxynitride layer are formed on the semiconductor substrate in sequence. Then, the silicon oxynitride layer, the metal silicide layer, the polysilicon layer and the gate oxide layer are etched to define a gate pattern. The sidewall spacers are formed on the sidewalls of the gate structure. The source and drain areas are defined by forming the doping areas in the semiconductor substrate. Next, a non-doped dielectric layer is formed above the semiconductor substrate to cover the gate structure, the sidewall spacers and the source/drain areas. An annealing procedure is next performed about 10 to 15 minutes at a temperature of about 800 to 850.degree. C. Then, a dielectric layer is formed on said non-doped dielectric layer.

Abstract: A transistor and a method of making the same are provided. The transistor includes a substrate that has an upper surface and a gate dielectric layer positioned on the substrate that has a first quantity of nitrogen therein. A gate electrode is positioned on the gate dielectric layer. First and second source/drain regions are positioned in the substrate and laterally separated to define a channel region beneath the gate dielectric layer. The gate dielectric layer may be composed of a high K material with a thin equivalent thickness of oxide, such as TiO.sub.2, Ta.sub.2 O.sub.5, CrO.sub.2 or SrO.sub.2. The nitrogen suppresses later oxide formation which may otherwise increase the equivalent thickness of oxide of the gate dielectric layer. Nitrogen may also be incorporated into the substrate and the gate electrode.

Abstract: A method of rapid thermal processing (RTP) of a silicon substrate is presented, where a very low partial pressure of reactive gas is used to control etching and growth of oxides on the silicon surface.

Abstract: Methods are disclosed for depositing an in situ polysilicon layer on the back of a semiconductor wafer to reduce the temperature at the edge of the wafer during rapid thermal annealing (RTA). The reduced temperature results in decreased boron penetration at the edge of the wafer and a more uniform silicide resistance and threshold voltage across the wafer.

Abstract: In one aspect, the invention includes a method of thermal processing comprising: a) providing a semiconductor substrate, the semiconductor substrate supporting a material that is to be thermally processed; b) forming a sacrificial mass over the material, the mass comprising an inner portion and an outer portion, the inner portion having a different composition than the outer portion and being nearer the material than the outer portion; c) exposing the mass to radiation to heat the mass, the exposing being for a period of time sufficient for the material to absorb heat from the mass and be thermally processed thereby; and d) removing the mass from over the material.

Abstract: The nickel element is provided selectively, i.e., adjacent to part of the surface of an amorphous silicon film in a long and narrow opening. The amorphous silicon film is irradiated with linear infrared light beams emitted from respective linear infrared lamps while scanned with the linear beams perpendicularly to the longitudinal direction of the opening. The longitudinal direction of the linear beams are set coincident with that of the opening. The infrared light beams are absorbed by the silicon film mainly as thermal energy, whereby a negative temperature gradient is formed in the silicon film. The temperature gradient moves as the lamps are moved for the scanning. The direction of the negative temperature gradient is set coincident with the lamp movement direction and an intended crystal growth direction, which enables crystal growth to proceed parallel with a substrate uniformly over a long distance.

Abstract: A method for rapid thermal processing (RTP) of a silicon substrate, the substrate having a surface with a plurality of areas implanted with dopant ions, comprising a) contacting the surface with a reactive gas, b) processing the substrate for a first process time and temperature sufficient to produce a significant protective layer upon the surface, and c) annealing the substrate for a second process time and temperature sufficient to activate the dopant material so that the sheet resistivity of the implanted areas is less than 500 ohms/square, where the first and second processing time and temperature are insufficient to move the implanted dopant ions to a depth of more than 80 nanometers from the surface.

Abstract: Laser anneal processing of a semiconductor layer is repeated in a number of steps. Grain size is increased using high energy ELA for a first step, and grain sizes are uniformed using ELA with low energy for a later step. As a defective crystallization region occurs in an excessive energy region during the ELA for the first step, in the ELA for the second time, excessive energy is removed and the defective crystallization region is eliminated by reducing the energy to an optimal value, thereby improving the crystallinity of a p-Si layer.

Abstract: A method of forming a polycrystalline silicon thin film improved in crystallinity and a channel of a transistor superior in electrical characteristics by the use of such a polycrystalline silicon thin film. An amorphous silicon layer of a thickness preferably of 30 nm to 50 nm is formed on a substrate. Next, substrate heating is performed to set the amorphous silicon layer to preferably 350.degree. C. to 500.degree. C., more preferably 350.degree. C. to 450.degree. C. Then, at least the amorphous silicon layer is irradiated with laser light of an excimer laser energy density of 100 mJ/cm.sup.2 to 500 mJ/cm.sup.2, preferably 280 mJ/cm.sup.2 to 330 mJ/cm.sup.2, and a pulse width of 80 ns to 200 ns, preferably 140 ns to 200 ns, so as to directly anneal the amorphous silicon layer and form a polycrystalline silicon thin film. The total energy of the laser used for the irradiation of excimer laser light is at least 5 J, preferably at least 10 J.

Abstract: A method of thermal processing of semiconductor wafers during device fabrication wherein there is provided a processing chamber for thermal processing of a semiconductor wafer having a component-containing surface and an opposing backside. A retainer is provided for retaining the wafer within the chamber whereby the wafer, when retained by the retainer, forms an enclosed space in the chamber with the backside. A wafer is retained in the chamber with the retainer and the wafer is heated. Concurrent with the heating of the wafer, the fluid content of the enclosed space is continually removed while the wafer is in the processing chamber. The fluid content of the space which was the enclosed space is continually removed while the wafer is removed from the chamber after completion of the heating cycle thereon. The continual removal of fluid content can comprise purging the enclosed space with a moving gas inert to the materials in the chamber or the application of a vacuum to the enclosed space.

Abstract: Stable suicides are formed utilizing excimer laser crystallization in place of a conventional second high temperature rapid thermal processing annealing step. Specifically, thermally unstable silicide having a metal-rich surface layer is conventionally formed utilizing deposition of refractory metal followed by low temperature annealing. After removal of unreacted refractory metal, an amorphous silicon film is deposited on top of the unstable silicide and exposed to radiation from an excimer laser, such that the amorphous silicon melts, reacts with refractory metal from the underlying unstable silicide, and reforms as thermally stable silicide evidencing low electrical resistance.

Abstract: A CMOS device and a method for forming the same is provided so as to overcome the problem of boron penetration through the thin gate oxide of P-channel devices. Silicon is implanted into the polysilicon gate electrode of the PMOS device functioning as a diffusion barrier for preventing boron penetration through the thin gate oxide and into the semiconductor substrate. As a result, the reliability of the CMOS device will be enhanced.

Abstract: A process for fabricating a semiconductor device comprising the step of, after patterning the silicon film crystallized to a low degree by thermally annealing an amorphous silicon film into an island by etching, irradiating an intense light of a visible light or a near infrared radiation to effect a short-period annealing (RTA) to the silicon film of low crystallinity. Thus, the crystallinity of the silicon film is improved and the silicon film is densified in a short-period.

Abstract: A process in accordance with the invention enables the manufacturability of raised source-drain MOSFETs. In accordance with the invention, a raised source-drain material, having a window therein, is formed over the substrate. A gate oxide and window sidewall oxides are subsequently formed. Dopants are diffused into the substrate. A gate is formed within the window.

Abstract: A method of fabricating a transistor having an improved salicided gate is provided. The method may include forming a gate (14) that is separated from a substrate (12) by a gate insulator (16). A spacer (22) may be formed proximate the gate (14) such that the spacer (22) exposes a top region (28) and a side region (30) of the gate (14). The top region (28) and the side region (30) of the gate (14) may be irradiated at an angle (38) to form a post amorphous region (32) within the gate (14). A reactive layer (42) may be formed adjacent the post amorphous region (32). A salicidation region (44) may be then formed between the post amorphous region (32) and the reactive layer (42). The reactive layer (42) may be removed to expose the salicidation region (44).

Abstract: A microscopic interconnection pattern and a gate electrode can be prevented from being deformed when a first region requiring high temperature heating, such as a source-drain region and a second region which should be prevented from being heated at high temperature, such as a microscopic interconnection pattern and a gate electrode are formed on the same semiconductor substrate. A first region which requires high temperature heating and a second region which should be avoided from being heated at high temperature are formed on a semiconductor substrate. In that case, the second region is composed of a narrow portion (1) and wide portions (2) wider than the narrow portion (1) formed on respective ends of the narrow portion 1. Then, the semiconductor substrate is photo-annealed.

Abstract: A preparation method of a semiconductor device comprising a substrate having formed thereon plural semiconductor elements formed in a matrix form and plural pixel electrodes each connected to each semiconductor element and a liquid crystal layer held on the substrate, comprisinga step of forming the plural pixel electrodes on an interlayer dielectric,a step of heat-treating the plural electrodes to form hillocks and whiskers on the surfaces of the electrodes, anda step of removing the hillocks and the whiskers to flatten the electrode surfaces.The semiconductor device is suitably used for, for example, a reflection type LCD apparatus with pixel electrodes having a good light reflectance and a high anti-brittleness.

Abstract: Method of forming a uniform polycrystalline semiconductor thin film by laser annealing. The method is started with preparing a substrate having an insulating layer which has a relatively low thermal conductivity and a thickness of more than 20 nm. Then, an amorphous silicon thin film having a relatively high thermal conductivity is formed to a thickness of less than 35 nm on the insulating layer. Thereafter, the amorphous silicon thin film is irradiated with laser beam to impart thermal energy to the film. In this way, the amorphous film is converted into a polysilicon thin film. Since the thickness of the amorphous silicon film is less than 35 nm, polysilicons having uniform grain diameters can be grown.

Abstract: It is intended to provide a technique of separately forming thin-film transistors disposed in a peripheral circuit area and those disposed in a pixel area in accordance with characteristics required therefor in a manufacturing process of semiconductor devices to constitute a liquid crystal display device. In an annealing step by laser light illumination, laser light is selectively applied to a semiconductor thin-film by partially masking it. For example, to illuminate the peripheral circuit area and the pixel area with laser light under different conditions in manufacture of an active matrix liquid crystal display device, laser light is applied at necessary illumination energy densities by using a mask. In this manner, a crystalline silicon film having a necessary degree of crystallinity in a selective manner can be obtained.

Abstract: A method for forming a metal oxide semiconductor field effect transistor (MOSFET). There is first provided a semiconductor substrate. There is then formed upon the semiconductor substrate a gate dielectric layer. There is then formed upon the gate dielectric layer a gate electrode. There is then implanted into the semiconductor substrate while employing the gate electrode as a mask a pair of unactivated source/drain regions at a pair of opposite edges of the gate electrode, where the gate dielectric layer, the gate electrode and the pair of unactivated source/drain regions form an unactivated metal oxide semiconductor field effect transistor (MOSFET).

Abstract: Method of forming a film for a semiconductor device in which a source material comprising a deuterated species is provided during formation of the film.

Abstract: A method of forming a transistor includes the steps of forming a gate structure (56) overlying a gate oxide layer (54), wherein the gate structure (56) and gate oxide layer (54) overlie a substrate (50), thereby separating the substrate (50) into a first region (90) and a second region (92) with a channel region therebetween. The method also includes doping the gate structure (56), the first region (90) and the second region (92) and annealing the doped gate structure (56) with a laser anneal, thereby driving the dopant through a substantial depth of the gate structure (56). Lastly, a source region (94) and a drain region (96) are formed in the first region (90) and the second region (92), respectively, wherein the dopant is further driven into the gate structure (56). Consequently, the dopant is driven substantially deeper in the gate structure (56) than in the shallow source region (94) and drain region (96) junctions to allow decoupling of poly depletion from the need for shallow junctions.

Abstract: Laser anneal processing of a semiconductor layer is repeated in a number of steps. Grain size is increased using high energy ELA for a first step, and grain sizes are uniformed using ELA with low energy for a later step. As a defective crystallization region occurs in an excessive energy region during the ELA for the first step, in the ELA for the second time, excessive energy is removed and the defective crystallization region is eliminated by reducing the energy to an optimal value, thereby improving the crystallinity of a p-Si layer.

Abstract: Thin-film semiconductor devices such as TFTs (thin-film transistors) and methods of fabricating the same. TFTs are formed on an insulating substrate. First, a substantially amorphous semiconductor coating is formed on the substrate. A protective coating transparent to laser radiation is formed on the semiconductor coating. The laminate is irradiated with laser radiation to improve the crystallinity of the semiconductor coating. Then, the protective coating is removed to expose the surface of the semiconductor coating. A coating for forming a gate-insulating film is formed. Subsequently, gate electrodes are formed. Another method relates to fabrication of semiconductor devices such as TFTs on an insulating substrate. After forming a first coating consisting mainly of aluminum nitride, a second coating consisting principally of silicon oxide is formed. Semiconductor devices such as TFTs or semiconductor circuits are built on the second coating serving as a base layer.

Abstract: Transistor drive current is controlled by controllably varying light exposure across a semiconductor substrate wafer based on an integrated circuit parameter. Integrated circuit parameters upon which the light exposure is varied include gate oxide thickness, rapid temperature annealing (RTA) temperature, polyetch bias and the like.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a semiconductor film containing silicon, implanting impurity elements to the semiconductor film, performing a dehydrogenation treatment to the semiconductor film, and activating the impurity elements in the dehydrogenated semiconductor film.

Abstract: A semiconductor process for forming a gate electrode of an MOS transistor. A gate dielectric is deposited on an upper surface of a semiconductor substrate. A dielectric constant of the gate dielectric layer is in the range of approximately 25 to 300. A thickness of the gate dielectric is in the range of approximately 50 to 1,000 angstroms. A conductive gate layer is then formed on the gate dielectric layer. A first nitrogen distribution is then introduced into the gate dielectric layer. The introduction of the first nitrogen distribution is typically accomplished by implanting a first nitrogen bearing species into the gate dielectric layer. Ideally, a peak impurity concentration of the first nitrogen distribution is located at an interface between the semiconductor substrate and the gate dielectric layer. Thereafter, a second nitrogen distribution is introduced into the gate dielectric layer.

Abstract: In the manufacture of a large-area electronic device, thin-film circuit elements such as TFTs are formed with separate islands (1a,1b) of a crystallized semiconductor film (1) on a device substrate (100,101). The method includes directing an energy beam (50) towards a grid (30) of masking stripes (32) and apertures (31) formed on the semiconductor film (1), to heat the semiconductor film (1) so as to crystallize it both at the apertures (31) and under the masking stripes (32). The masking stripes (32) are located over areas of the semiconductor film (1) where channel regions (11) of the TFT are to be formed. Each aperture (31) between the masking stripes (32) has a width (S1) of less than the wavelength (.lambda.) of the energy beam (50) of step (c). The length of the channel region (11) below each masking stripe (32) is crystallized by diffraction of the energy beam (50) at the apertures as well as by thermal diffusion from the areas heated by the energy beam (50).

Abstract: The preferred embodiment provides a method for fabricating field effect transistors that have different threshold voltages without requiring excessive masking and other fabrication steps. In particular, the method facilitates the formation of FETs with different threshold voltages by doping the gate dielectric with various amounts of ions. This provides a built in potential in the gate dielectric proportional to the amount of ions in the gate dielectric. This potential changes the threshold voltage of the FET. Thus, by selectively doping the gate dielectric with ions the threshold voltage of a FET can be changed. The selective doping of many FETs to many different threshold voltages can be done with only one additional masking step. Thus, the present invention provides the ability to form FETs having different threshold voltages without requiring excessive process complexity.

Abstract: The present invention is related to a thin film semiconductor which can be regarded as substantially a single crystal and a semiconductor device comprising an active layer formed by the thin film semiconductor. At least a concave or convex pattern is formed intentionally on a insulating film provided in contact with the lower surface of an amorphous silicon film, whereby at least a site is formed in which a metal element for accelerating crystallization can be segregated. Therefore, a crystal nuclei is selectively formed in a portion where the concave or convex pattern is located, which carries out controlling a crystal diameter. Thus, a crystalline silicon film is obtained. A crystallinity of the crystalline silicon film is improved by the irradiation of a laser light or an intense light having an energy equivalent to that of the laser light, whereby a monodomain region in which no grain boundary substantially exit is formed.

Abstract: The process described requires the formation of floating-gate non-volatile memory cells entirely similar in structure to those produced by known processes. The process comprises an annealing treatment at relatively low temperature (430.degree. C.) to repair damage due to plasma treatments. To obtain threshold voltage values for the cells close to the theoretical values, especially for cells with particularly extended interconnections, the cells are subjected to ultraviolet radiation before the annealing treatment, in order to neutralize any electrical charges present in the floating-gate electrodes of the cells.

Abstract: A method of making N-channel and P-channel IGFETs is disclosed. The method includes, in sequence, the steps of partially doping a first source and a first drain in a first active region of a semiconductor substrate, applying a first tube anneal while a second active region of the semiconductor substrate is devoid of source/drain doping, partially doping a second source and a second drain in the second active region, applying a second tube anneal, fully doping the first source and the first drain, applying a first rapid thermal anneal, fully doping the second source and the second drain, and applying a second rapid thermal anneal. Advantageously, the first and second tube anneals provide control over the channel junction locations, and the first and second rapid thermal anneals provide rapid drive-in for subsequent source/drain doping spaced from the channel junctions.

Abstract: A two step source/drain annealing process which permits a dopant to be ion implanted directly into the silicon without a protective oxide. The gate oxide is removed before the ion implantation of the dopant occurs, thus the dopant is implanted directly into bare silicon. In a first step of the annealing process, a thin oxide is grown over the source and drain regions at a relatively low temperature (e.g., 600.degree. C.) this temperature to prevent the evaporation of the dopant from the silicon substrate and polysilicon gate. The second step of the annealing process occurs at a higher temperature allowing the dopant to be driven into the substrate forming the source and drain regions.

Abstract: The present invention discloses a method of forming an oxide layer on a layer of gallium arsenide, including the steps of depositing a layer of aluminum arsenide on the layer of gallium arsenide, of exposing the layer of aluminum arsenide to an oxidizing gas mixture so that the aluminum arsenide is oxidized to aluminum oxide, and of controlling excess arsenic released in the aluminum oxide during the exposing step, so as to ensure enhanced electrical properties in the aluminum oxide. The method is used to provide an insulating gate layer for a GaAs field effect transistor by forming an oxide layer on GaAs and controlling excess arsenic so as to maintain high resistivity in the oxide layer and to avoid the formation of interface surface states which degrade transistor performance. The method is also used to provide complementary metal-insulator-semiconductor logic devices based on the gallium arsenide field effect transistor.

Abstract: An integrated circuit is formed with minimal encroachment of lightly doped drain (LDD) implants partially due to barrier atoms incorporated along the migration avenues. Nitrogen is incorporated either during the LDD implant or during an anneal cycle following the LDD implant. Nitrogen helps minimize segregation and diffusion of LDD dopants placed adjacent critical channel and gate dielectric areas. Nitrogen is incorporated within a chamber while under pressure so as to minimize the temperature needed to repair implant damage and activate the LDD dopants. High pressure indoctrination of nitrogen is believed to provide the same amount of lattice repair and activation achieved if anneal temperatures were substantially higher.

Abstract: A process is described for forming a heavily doped buried element below an active device region of a silicon wafer without the use of costly epitaxial layers and without incurring ion implantation damage within active device regions. The method is particularly applicable to active device regions which have small lateral dimensions. Thus, the technological trend towards shrinking devices favors the incorporation of the process of the invention. The process utilizes a silicon nitride hardmask to define a narrow band around the perimeter of the device active area. A deep implant is performed through this mask, placing a ring of dopant below and outside the active area. The silicon nitride hardmask is then patterned a second time to define the conventional field oxide isolation regions. The LOCOS field oxidation is then performed whereby the implanted dopant diffuses vertically, engaging the field oxide around the perimeter of the device region and laterally filling in the region under the device active area.

Abstract: N- and P-channel transistor characteristics are independently optimized for CMOS semiconductor devices with design features of 0.25 microns and under. Removable second sidewall spacers are formed on the N-channel transistor gate electrode having first sidewall spacers thereon. Ion implantation is conducted to form N-type moderately/heavily doped implants followed by activation annealing. The second sidewall spacer is then removed from the P-channel transistor leaving first sidewall spacers thereon serving as an ion implantation mask for the P-type lightly doped implants. Subsequently, third sidewall spacers are formed on the P-channel gate electrode having first sidewall spacers thereon followed by ion implantation to form the P-type moderately or heavily doped implants, with subsequent activation annealing. Embodiments enable complete independent control of the channel lengths of the N- and P-channel transistors by varying the width of the first, second and third sidewall spacers.

Abstract: A method for fabricating custom integrated circuits includes the steps of 1) patterning the layer to be customized with standard precision masking techniques to define all possible connections, vias or cut-points, and 2) using a non-precision targeting energy beam to select the desired connections, vias or cut-points for customization. Consequently, the present invention requires no custom mask so that application specific integrated circuits (ASICs) can be produced with lower lead-time and costs when compared to prior methods.In other embodiments, a non-precision configuration mask may replace the targeting energy beam, where the configuration mask can be made by conventional mask-making techniques or by applying an opaque layer to a mask blank and using a targeting energy beam to selectively remove the desired portions of the opaque areas.

Abstract: An integrated circuit is provided having both NMOS transistors and PMOS transistors. The NMOS transistor junction regions are preferably formed before the PMOS transistor junction regions with pre-defined anneal temperatures applied after select implant steps. Both the NMOS and PMOS transistor junction are graded such that the drain areas include a relatively large LDD implant area and the source junctions do not. Whatever LDD area pre-existing in the source implanted with a higher concentration source/drain or MDD implant. The ensuing integrated circuit is therefore a CMOS circuit having asymmetrical transistor junctions and carefully controlled implant and anneal sequences. The asymmetrical junctions are retained, or at least optimized, by controlling the anneal temperatures such that diffusivity distances of n-type implants are relatively similar to p-type implants. Diffusivity is controlled by regulating the post-implant anneal temperatures of p-type implants lesser than previous n-type implants.

Abstract: A method of fabricating a chalcogenide memory cell wherein a layer of chalcogenide material is deposited in an amorphous state. The layer of amorphous chalcogenide material is then etched to its final geometry while maintaining its amorphous structure. The final geometry of the chalcogenide material is then annealed thereby transforming it to a crystalline form.

Abstract: A method for crystallizing a portion of a semiconductor thin film while forming a semiconductor device comprises providing a transparent substrate supporting a metallic gate electrode and an amorphous semiconductor thin film which are separated from each other by a gate insulating film, heating the gate electrode by subjecting it to light rays, and applying a laser beam to the amorphous semiconductor thin film so that the portion of the semiconductor thin film adjacent the metallic gate electrode is heated by both the laser beam and the heat of the gate electrode to cause a crystallization of a portion of the amorphous thin film and then processing the remaining amorphous portions of the thin film to form the transistor structure.

Abstract: A P-type impurity layer, a silicon monocrystal film, a silicon oxide film and a crystal silicon film are successively formed on a semiconductor substrate by introducing appropriate functional gases on the semiconductor substrate, while irradiating the semiconductor substrate with ionizing radiation or light at a temperature lower than 250.degree. C. After forming a photoresist on the crystal silicon film at a temperature lower than 250.degree. C., the resultant semiconductor substrate is subjected to etching by using the photoresist as a mask, so as to form a gate electrode B out of the silicon oxide film and a gate insulating film out of the silicon oxide film. Then, the resultant semiconductor substrate is subjected to etching again by using the gate electrode as a mask, so as to form a channel region out of the P-type impurity layer.