Optical Waveguide Structure Patents (Class 438/31)
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Patent number: 8483529Abstract: Systems, devices, and techniques are disclosed relating to dispersion devices that include a slot waveguide coupled with another waveguide such as a strip waveguide. For example, one or more structural parameters can be obtained for a dispersion device, including a slot waveguide coupled to a strip waveguide, to cause the dispersion device to produce dispersion, having a dispersion profile, for an electromagnetic wave propagated through the dispersion device, the one or more structural parameters including one or more of a slot thickness for a slot of the slot waveguide or a spacing thickness between the slot waveguide and the other waveguide; and making the dispersion device, including the slot waveguide and the other waveguide, according to the structural parameters.Type: GrantFiled: February 4, 2011Date of Patent: July 9, 2013Assignee: University of Southern CaliforniaInventors: Lin Zhang, Yang Yue, Alan E. Willner
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Patent number: 8478097Abstract: Various embodiments include photonic bandgap fibers (PBGF). Some PBGF embodiments have a hollow core (HC) and may have a square lattice (SQL). In various embodiments, SQL PBGF can have a cladding region including 2-10 layers of air-holes. In various embodiments, an HC SQL PBGF can be configured to provide a relative wavelength transmission window ??/?c larger than about 0.35 and a minimum transmission loss in a range from about 70 dB/km to about 0.1 dB/km. In some embodiments, the HC SQL PBGF can be a polarization maintaining fiber. Methods of fabricating PBGF are also disclosed along with some examples of fabricated fibers. Various applications of PBGF are also described.Type: GrantFiled: September 11, 2012Date of Patent: July 2, 2013Assignee: IMRA America, Inc.Inventors: Liang Dong, Brian K. Thomas, Shigeru Suzuki, Libin Fu
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Patent number: 8476657Abstract: To provide a light emitting device easy to produce and extracting light to its outside with high efficiency, the light-emitting device 70 of the present invention includes an insulating base 10; a light-emitting element 1 mounted on a side of the base 10; and a protection element 2 mounted on the side and protecting the light-emitting element 1. The element 2 is covered with a light-reflecting filler-containing resin 5, which is prepared by causing a flexible silicone resin to contain, before being cured, light-reflecting or light-scattering fillers 5a having a particle diameter larger than the wavelength of light emitted by the element 1. This causes light emitted from the element 1 to be reflected by the resin 5, instead of being absorbed by the element 2, so that such light is released to the outside of the light-emitting device 70. This allows the device 70 to extract light to the outside with high efficiency, and also allows for easy formation of the resin 5 having a desired pattern and position.Type: GrantFiled: November 25, 2009Date of Patent: July 2, 2013Assignee: Sharp Kabushiki KaishaInventors: Osamu Kawasaki, Toshio Hata
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Publication number: 20130163916Abstract: Disclosed are an optical waveguide platform with integrated active transmission device and monitoring photodiode. The optical waveguide platform with hybrid integrated optical transmission device and optical active device includes an optical waveguide region formed by stacking a lower cladding layer, a core layer and an upper cladding layer on a substrate; a trench region formed by etching a portion of the optical waveguide region; and a spot expanding region formed on the core layer in the optical waveguide region, in which the optical transmission device is mounted in the trench region and the optical active device is flip-chip bonded to the spot expanding region. The monitoring photodiode is flip-chip bonded to the spot expanding region of the core layer of the optical waveguide, thereby monitoring output light including an optical coupling loss that occurs during flip-chip bonding.Type: ApplicationFiled: June 4, 2012Publication date: June 27, 2013Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hyun Soo KIM, Jong Sool Jeong, Mi-Ran Park, Byungseok Choi, O-Kyun Kwon
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Publication number: 20130163918Abstract: A method of manufacture of an integrated circuit coupling system includes: forming a waveguide assembly, having a top clad over an open end of an optical core; forming a first photoresist having a base photoresist pattern shape with sloped photoresist sidewalls tapered down to expose a portion of the top clad; forming a recess having clad sidewalls from the portion of the top clad exposed by the base photoresist pattern shape, the clad sidewalls having a shape replicating a shape of the base photo resist pattern shape; and forming an optical vertical insertion area, from the clad sidewalls forming the recess, having a pocket trench, a horizontal step, and a mirror with a reflective material selectively applied to a section of the clad sidewalls and exposing the open end opposite to the mirror, the horizontal step between the mirror and the pocket trench.Type: ApplicationFiled: December 27, 2012Publication date: June 27, 2013Applicant: NEOPHOTONICS CORPORATIONInventor: NeoPhotonics Corporation
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Patent number: 8472766Abstract: A solid state waveguide coupler is provided including a first coupler end disposed on a solid state material substrate for connection to a first solid state waveguide located on the substrate and a second coupler end disposed on the substrate for connection to a second waveguide located on the substrate. A coupling span, comprising a waveguide material layer on the substrate, is disposed between the first and second coupler ends and tapers between a height of the first waveguide and a height of the second waveguide, tapers between a width of the first waveguide and a width of the second waveguide, and includes curved sidewalls along at least a portion of the tapered coupling span. In a method for fabricating the waveguide coupler, material is isotropically removed from a waveguide material layer on the substrate to produce tapered surfaces between the first waveguide and the second waveguide.Type: GrantFiled: August 12, 2010Date of Patent: June 25, 2013Assignee: Massachusetts Institute of TechnologyInventors: Steven Jay Spector, Reuel Bennett Swint, Milos Popovic
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Publication number: 20130156364Abstract: A device includes a passive photonic layer located over a substrate and including at least one passive photonic element configured to propagate an optical signal therein. An electronic layer located between said substrate and said passive photonic layer includes at least one electronic device configured to propagate an electrical signal therein. An active photonic layer located over said passive photonic layer includes an active photonic device optically coupled to said passive photonic element and configured to convert between said electrical signal and said optical signal.Type: ApplicationFiled: December 15, 2011Publication date: June 20, 2013Applicant: Alcatel-Lucent USA, Inc.Inventors: Long Chen, Pietro Bernasconi, Po Dong, Liming Zhang, Young-Kai Chen
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Patent number: 8465993Abstract: A vertical cavity surface emitting laser that includes: a substrate; a first semiconductor multilayer reflector; an active region; a second semiconductor multilayer reflector; a columnar structure formed from the second semiconductor multilayer reflector to the first semiconductor multilayer reflector; a current narrowing layer formed inside of the columnar structure and having a conductive region surrounded by an oxidization region; a first electrode formed at a top of the columnar structure, electrically connected to the second semiconductor multilayer reflector and defining a beam window; a first insulating film comprised of a material with a first refractive index and formed on the first electrode to cover the beam window; and a second insulating film comprised of a material with a second refractive index and formed on the first insulating film, of which a radius is smaller than a radius of the conductive region.Type: GrantFiled: October 12, 2012Date of Patent: June 18, 2013Assignee: Fuji Xerox Co., Ltd.Inventors: Kazutaka Takeda, Masahiro Yoshikawa, Kazuyuki Matsushita
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Patent number: 8467639Abstract: The present disclosure includes methods, devices, and systems for zinc oxide diodes for optical interconnections. One system includes a ZnO emitter confined within a circular geometry in an oxide layer on a silicon substrate. An optical waveguide is formed in the oxide layer and has an input coupled to the ZnO emitter. A detector is coupled to an output of the optical waveguide.Type: GrantFiled: July 18, 2011Date of Patent: June 18, 2013Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Kie Y. Ahn
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Patent number: 8461050Abstract: A method of taper-etching a layer to be etched that is made of SiO2 or SiON and has a top surface. The method includes the step of forming an etching mask with an opening on the top surface of the layer to be etched, and the step of taper-etching a portion of the layer to be etched, the portion being exposed from the opening, by reactive ion etching so that a groove having two wall faces that intersect at a predetermined angle is formed in the layer to be etched. The etching mask is formed of a material containing elemental Al. The step of taper-etching employs an etching gas that contains a main component gas, which contributes to the etching of the layer to be etched, and N2.Type: GrantFiled: June 10, 2011Date of Patent: June 11, 2013Assignee: Headway Technologies, Inc.Inventors: Hironori Araki, Yoshitaka Sasaki, Hiroyuki Ito, Kazuki Sato, Shigeki Tanemura, Yukinori Ikegawa
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Patent number: 8455278Abstract: N-V centers in diamond are created in a controlled manner. In one embodiment, a single crystal diamond is formed using a CVD process, and then annealed to remove N-V centers. A thin layer of single crystal diamond is then formed with a controlled number of N-V centers. The N-V centers form Qubits for use in electronic circuits. Masked and controlled ion implants, coupled with annealing are used in CVD formed diamond to create structures for both optical applications and nanoelectromechanical device formation. Waveguides may be formed optically coupled to the N-V centers and further coupled to sources and detectors of light to interact with the N-V centers.Type: GrantFiled: November 14, 2011Date of Patent: June 4, 2013Assignee: Apollo Diamond, IncInventors: Robert C. Linares, Patrick J. Doering, William W. Dromeshauser, Bryant Linares, Alfred R. Genis
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Publication number: 20130137202Abstract: Current may be passed through an n-doped semiconductor region, a recessed metal semiconductor alloy portion, and a p-doped semiconductor region so that the diffusion of majority charge carriers in the doped semiconductor regions transfers heat from or into the semiconductor waveguide through Peltier-Seebeck effect. Further, a temperature control device may be configured to include a metal semiconductor alloy region located in proximity to an optoelectronic device, a first semiconductor region having a p-type doping, and a second semiconductor region having an n-type doping. The temperature of the optoelectronic device may thus be controlled to stabilize the performance of the optoelectronic device.Type: ApplicationFiled: January 23, 2013Publication date: May 30, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: International Business Machines Corporation
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Patent number: 8450186Abstract: Optical modulator utilizing wafer bonding technology. An embodiment of a method includes etching a silicon on insulator (SOI) wafer to produce a first part of a silicon waveguide structure on a first surface of the SOI wafer, and preparing a second wafer, the second wafer including a layer of crystalline silicon, the second wafer including a first surface of crystalline silicon. The method further includes bonding the first surface of the second wafer with a thin oxide to the first surface of the SOI wafer using a wafer bonding technique, wherein a second part of the silicon waveguide structure is etched in the layer of crystalline silicon.Type: GrantFiled: September 25, 2009Date of Patent: May 28, 2013Assignee: Intel CorporationInventors: Haisheng Rong, Ansheng Liu
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Patent number: 8450749Abstract: A light emitting element includes a substrate, a GaN layer formed on the substrate, a first low refractive index semiconductor layer formed on the GaN layer, and a lighting structure having a high refractive index formed on the first low refractive index semiconductor layer. A second low refractive index semiconductor layer is embedded in the first low refractive index semiconductor layer. The first low refractive index semiconductor layer and the GaN layer exhibit a lattice mismatch therebetween.Type: GrantFiled: January 7, 2011Date of Patent: May 28, 2013Assignee: Advanced Optoelectronics Technology, Inc.Inventors: Po-Min Tu, Shih-Cheng Huang, Shun-Kuei Yang, Chia-Hung Huang
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Publication number: 20130128911Abstract: A diode laser having aluminum-containing layers and a Bragg grating for stabilizing the emission wavelength achieves an improved output/efficiency. The growth process is divided into two steps for introducing the Bragg grating, wherein a continuous aluminum-free layer and an aluminum-free mask layer are continuously deposited after the first growth process such that the aluminum-containing layer is completely covered by the continuous aluminum-free layer. Structuring is performed outside the reactor without unwanted oxidation of the aluminum-containing semiconductor layer. Subsequently, the pre-structured semiconductor surface is further etched inside the reactor and the structuring is impressed into the aluminum-containing layer.Type: ApplicationFiled: November 21, 2012Publication date: May 23, 2013Applicant: Forschungsverbund Berlin E.V.Inventor: Forschungsverbund Berlin E.V.
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Patent number: 8447147Abstract: Some embodiments include communication methods, methods of forming an interconnect, signal interconnects, integrated circuit structures, circuits, and data apparatuses. In one embodiment, a communication method includes accessing an optical signal comprising photons to communicate information, accessing an electrical signal comprising electrical data carriers to communicate information, and using a single interconnect, communicating the optical and electrical signals between a first spatial location and a second spatial location spaced from the first spatial location.Type: GrantFiled: December 12, 2011Date of Patent: May 21, 2013Assignee: Micron Technology, Inc.Inventor: Chandra Mouli
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Patent number: 8442364Abstract: An optical waveguide device includes an optical branch device for branching a first input light and outputting the branched first input light to a first and a second optical waveguides, another optical branch device, arranged between the first and the second optical waveguides, for branching a second input light and outputting the branched second input light to a third and a fourth optical waveguides, an optical coupler which couples the lights traveling along the first and the third optical waveguides, then branches the coupled lights, and outputs them; and another optical coupler which couples the lights traveling along the second and the fourth optical waveguides, then branches the coupled lights, and outputs them, wherein optical path lengths of either a pair of the first and the second optical waveguides or a pair of the third and the fourth optical waveguides are set to be equal.Type: GrantFiled: March 15, 2011Date of Patent: May 14, 2013Assignee: NEC CorporationInventor: Shinya Watanabe
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Patent number: 8435815Abstract: A manufacturing method of a surface-emitting semiconductor laser includes the steps of: forming a stacked structure having a lower-multilayer film reflector including a lower oxidizable layer having at least one layer, an active layer having a light emitting region, an upper-multilayer film reflector including an upper oxidizable layer and an upper layer on a substrate in this order; providing a first groove in the upper layer; and providing a second groove including a portion overlapping the first groove in a planar shape and a portion not overlapping the first groove in the stacked structure.Type: GrantFiled: December 17, 2010Date of Patent: May 7, 2013Assignee: Sony CorporationInventors: Masaki Shiozaki, Osamu Maeda, Takahiro Arakida, Susumu Sato
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Patent number: 8435809Abstract: A vertical total internal reflection (TIR) mirror and fabrication thereof is made by creating a re-entrant profile using crystallographic silicon etching. Starting with an SOI wafer, a deep silicon etch is used to expose the buried oxide layer, which is then wet-etched (in HF), opening the bottom surface of the Si device layer. This bottom silicon surface is then exposed so that in a crystallographic etch, the resulting shape is a re-entrant trapezoid with facets These facets can be used in conjunction with planar silicon waveguides to reflect the light upwards based on the TIR principle. Alternately, light can be coupled into the silicon waveguides from above the wafer for such purposes as wafer level testing.Type: GrantFiled: September 25, 2009Date of Patent: May 7, 2013Assignee: Intel CorporationInventors: John Heck, Ansheng Liu, Michael T. Morse, Haisheng Rong
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Publication number: 20130108207Abstract: A method includes fabricating a circuit element and a connection to the circuit element for a photonic integrated circuit. The method includes associating a configurable material with the circuit element and activating the configurable material via a poling rail and the connection to the circuit element during production of the integrated circuit.Type: ApplicationFiled: October 28, 2011Publication date: May 2, 2013Inventors: Lars Helge Thylen, Michael Renne Ty Tan, Shih-Yuan Wang, Alexandre M. Bratkovski, Wayne V. Sorin, Michael Josef Stuke
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Patent number: 8431950Abstract: A light emitting device package structure is described. The light emitting device package structure includes a substrate serving as a carrier supporting a light emitting device chip. The substrate and the light emitting device chip have a chip side and a substrate side separately. A first electrode layer is disposed on a first surface of the light emitting device chip and a second electrode layer is disposed on a second surface of the light emitting device chip, in which the first surface and the second surface are not coplanar. A first conductive trace is electrically connected to the first electrode layer and a second conductive trace is electrically connected to the second electrode layer. At least the first conductive trace or the second conductive trace is formed along the chip side and the substrate side simultaneously.Type: GrantFiled: May 22, 2009Date of Patent: April 30, 2013Inventors: Chia-Lun Tsai, Ching-Yu Ni, Wen-Cheng Chien, Shang-Yi Wu, Cheng-Te Chou
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Publication number: 20130093352Abstract: A method for amplifying an input optical signal includes the following steps: providing a light-emitting transistor device having a base region between collector and emitter regions; applying electrical signals with respect to the base, collector, and emitter regions to produce light emission from the base region of the light-emitting transistor device; and applying the input optical signal to the base region of the light-emitting transistor device to produce an amplified optical output from the base region.Type: ApplicationFiled: October 2, 2012Publication date: April 18, 2013Applicant: The Board Of Trustees Of The University of IllinoisInventor: The Board Of Trustees Of The Univ. of Illinois
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Patent number: 8415185Abstract: In a process for fabrication of an optical slot waveguide on silicon, a thin single-crystal silicon film is deposited on a substrate covered with an insulating buried layer; a local thermal oxidation is carried out over the entire depth of the thin single-crystal silicon film in order to form an insulating oxidized strip extending along the desired path of the waveguide; an insulating or semi-insulating layer is deposited on the silicon film; two openings having vertical sidewalls are excavated over the entire thickness of this insulating or semi-insulating layer, said openings being separated by a narrow gap constituting an insulating or semi-insulating vertical wall that will be the material of the slot; single-crystal silicon is grown in the openings and right to the edges of the insulating or semi-insulating wall; and then the upper part of the silicon is etched in order to complete the geometry of the waveguide.Type: GrantFiled: December 13, 2011Date of Patent: April 9, 2013Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, Alcatel Lucent, Centre National de la Recherche Scientifique, Universite Paris-SUD 11Inventors: Jean-Marc Fedeli, Guang-Hua Duan, Delphine Marris-Morini, Gilles Rasigade, Laurent Vivien, Melissa Ziebell
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Publication number: 20130084039Abstract: A photonic integrated circuit apparatus is disclosed. The apparatus includes a photonic chip and a lens array coupling element. The photonic chip includes a waveguide at a side edge surface of the photonic chip. The lens array coupling element is mounted on a top surface of the photonic chip and on the side edge surface. The coupling element includes a lens array that is configured to modify spot sizes of light traversing to or from the waveguide. The coupling element further includes an overhang on a side of the coupling element that opposes the lens array and that abuts the top surface of the photonic chip. The overhang includes a vertical stop surface that has a depth configured to horizontally align an edge of the waveguide with a focal length of the lens array and that vertically aligns focal points of the lens array with the edge of the waveguide.Type: ApplicationFiled: August 16, 2011Publication date: April 4, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: FUAD E. DOANY, Benjamin G. Lee, Clint L. Schow
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Patent number: 8411718Abstract: The present invention provides a nitride semiconductor light-emitting device capable of preventing shortening of the device lifetime due to increase in the driving voltage of the device and internal heat generation, and also providing uniform laser characteristics, even if the device has a ridge stripe structure. On a GaN substrate 1, an n-type GaN layer 2, an n-type AlGaN layer 3, an active layer 4, a p-type AlGan layer 5 and a p-type GaN layer 6 are laminated sequentially. On the p-type GaN layer 6, an insulating film 7 and a transparent electrode 8 are formed. A portion of the transparent electrode 8 is formed in contact with the p-type GaN layer 6. A ridge stripe portion D to form a waveguide is configured of a transparent film 9. A region, where the transparent electrode 8 and the p-type GaN layer 6 are in contact with each other, serves as a stripe-shaped current injection region.Type: GrantFiled: December 19, 2008Date of Patent: April 2, 2013Assignee: Rohm Co., Ltd.Inventor: Yukio Shakuda
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Patent number: 8405098Abstract: An organic light emitting device includes a first electrode and second electrode on a substrate. Light emitting units are positioned between the first and second electrodes. A first light emitting unit includes a first light emitting layer, and a second light emitting unit includes a second light emitting layer. The first electrode reflects light from at least one of the light emitting units to generate an interference pattern with light emitted from the first light emitting layer. The interference pattern has a plurality of interference positions such that a first interference position is located within the first light emitting layer, and a second interference position is located within the second light emitting layer.Type: GrantFiled: May 17, 2010Date of Patent: March 26, 2013Assignee: Sony CorporationInventors: Shigeyuki Matsunami, Toshihiro Fukuda, Jiro Yamada
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Patent number: 8405095Abstract: The embodiment is to provide a light emitting device and a method for manufacturing the same, in which the light emitting device includes a first conductive semiconductor layer; an active layer formed on the first conductive semiconductor layer; a second conductive semiconductor layer formed on the active layer; and a phosphor layer formed on the second conductive semiconductor layer; in which the phosphor layer includes a phosphor receiving member including a plurality of cavities and phosphor particles fixed in the cavities.Type: GrantFiled: August 30, 2010Date of Patent: March 26, 2013Assignee: LG Innotek Co., Ltd.Inventor: Jang Kee Youn
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Patent number: 8404506Abstract: In a method for the production of a single photon source with a given operational performance, the given operational performance for the individual photon source may be fixed by a directed setting of the fine structure gap of the excitonic energy level for at least one quantum dot. The at least one quantum dot is produced with a quantum dot size corresponding to the fine structure gap for setting.Type: GrantFiled: November 20, 2006Date of Patent: March 26, 2013Assignee: Technische Universitaet BerlinInventors: Anatol Lochmann, Robert Seguin, Dieter Bimberg, Sven Rodt, Vladimir Gaysler
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Publication number: 20130071058Abstract: An optical modulator and a method for manufacturing an optical modulator are provided.Type: ApplicationFiled: March 10, 2011Publication date: March 21, 2013Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCHInventors: Eu-Jin Andy Lim, Kah Wee Ang, Qing Fang, Tsung-Yang Jason Liow, Mingbin Yu, Guo Qiang Patrick Lo
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Patent number: 8399949Abstract: Some embodiments include photonic systems. The systems may include a silicon-containing waveguide configured to direct light along a path, and a detector proximate the silicon-containing waveguide. The detector may comprise a detector material which has a lower region and an upper region, with the lower region having a higher concentration of defects than the upper region. The detector material may comprise germanium in some embodiments. Some embodiments include methods of forming photonic systems.Type: GrantFiled: June 30, 2011Date of Patent: March 19, 2013Assignee: Micron Technology, Inc.Inventor: Roy E. Meade
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Publication number: 20130064497Abstract: Provided is an optical integrated device comprising a first waveguide that is formed on a substrate and includes a first optical path; an electrode formed on the first waveguide; a second waveguide that is formed on the substrate and includes a second optical path; and a transparent waveguide that is formed on the substrate between the first waveguide and the second waveguide, and includes a transparent core that serves as an optical path and is formed of a material having higher bandgap energy than the first optical path. The electrode is formed above the first waveguide and is not formed above the transparent waveguide, and elements including the first waveguide are optically active elements that operate according to current injected thereto.Type: ApplicationFiled: August 27, 2012Publication date: March 14, 2013Applicant: FURUKAWA ELECTRIC CO., LTD.Inventors: Norihiro IWAI, Hirotatsu ISHII
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Publication number: 20130064491Abstract: To provide an optical modulator having a reduced size and reduced power consumption and capable of being easily connected to a waveguide and a method of manufacturing the optical modulator. The optical modulator has at least semiconductor layer (8) having a rib-shaped portion and doped so as to be of a first conduction type, dielectric layer (11) laid on first-conduction-type semiconductor layer (8), and semiconductor layer (9) laid on dielectric layer (11), having the width at the side opposite from dielectric layer (11) increased relative to the width of the rib-shaped portion, and doped so as to be of a second conduction type.Type: ApplicationFiled: March 1, 2011Publication date: March 14, 2013Applicant: NEC CORPORATIONInventors: Junichi Fujikata, Motofumi Saitoh, Jun Ushida, Akio Toda
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Patent number: 8394705Abstract: Provided is a method of manufacturing a semiconductor device. According to the method, a first buried oxide layer is formed in the semiconductor substrate in a first region, such that a first semiconductor layer is defined on the first buried oxide layer. An active portion is defined by forming a trench in the semiconductor substrate in a second region. A capping semiconductor pattern is formed on a top surface and an upper portion of a sidewall of the active portion. An oxide layer is formed by oxidizing the capping semiconductor pattern and an exposed lower portion of the sidewall of the active portion, such that the oxide layer surrounds a non-oxidized portion of the active portion. The non-oxidized portion of the active portion is a core and one end of the core is connected to a first optical device formed at the first semiconductor.Type: GrantFiled: May 19, 2010Date of Patent: March 12, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: In Gyoo Kim, Dae Seo Park, Jun Taek Hong, Gyungock Kim
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Publication number: 20130058606Abstract: An electro-optic device, comprising an insulating layer and a layer of light-carrying material adjacent the insulating layer. The layer of light-carrying material, such as silicon, comprises a first doped region of a first type and a second doped region of a second, different type abutting the first doped region to form a pn junction. The first doped region has a first thickness at the junction, and the second doped region has a second thickness at the junction, the first thickness being greater than the second thickness, defining a waveguide rib in the first doped region for propagating optical signals. Since the position of the junction coincides with the sidewall of the waveguide rib a self-aligned process can be used in order to simplify the fabrication process and increase yield.Type: ApplicationFiled: January 20, 2011Publication date: March 7, 2013Inventors: David Thomson, Frederic Gardes, Graham Reed
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Patent number: 8390014Abstract: Disclosed is a light emitting device including a second conductive semiconductor layer; an active layer on the second conductive semiconductor layer; a first semiconductor layer on the active layer, the first semiconductor layer having at least one lateral side with a step portion; and a lateral electrode on the step portion formed at the at least one lateral side of the first semiconductor layer.Type: GrantFiled: November 30, 2010Date of Patent: March 5, 2013Assignee: LG Innotek Co., Ltd.Inventor: Hyo Kun Son
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Patent number: 8383435Abstract: A photonic semiconductor device and method are provided that ensure that the surface of the device upon completion of the SAG process is planar, or at least substantially planar, such that performance of the subsequent processes is facilitated, thereby enabling higher manufacturing yield to be achieved. A photonic semiconductor device and method are also provided that ensure that the isolation region of the device will have high resistance and low capacitance, without requiring the placement of a thick dielectric material beneath each of the contact pads. Eliminating the need to place thick dielectric materials underneath the contact pads eliminates the risk that the contact pads will peel away from the assembly.Type: GrantFiled: January 12, 2010Date of Patent: February 26, 2013Assignee: Avago Technologies Fiber IP (Singapore) Pte. LtdInventors: Marzia Rosso, Alessandro Stano, Ruiyu Fang, Paolo Valenti, Pietro Della Casa, Simone Codato, Cesare Rigo, Claudio Coriasso
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Publication number: 20130044782Abstract: Optical devices having a structured active region configured for selected wavelengths of light emissions are disclosed.Type: ApplicationFiled: July 13, 2012Publication date: February 21, 2013Applicant: SORAA, Inc.Inventor: James W. Raring
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Patent number: 8377320Abstract: A method of forming an undercut microstructure includes: forming an etch mask on a top surface of a substrate; forming, on a top surface of the etch mask, an ion implantation mask having a top surface that is smaller than the top surface of the etch mask and that does not extend beyond the top surface of the etch mask; ion implanting the substrate in the presence of the etch mask and the ion implantation mask so that a damaged region is generated at a depth below an area of the surface that is not masked by the ion implantation mask; and etching the surface of the substrate until the damaged region is removed.Type: GrantFiled: July 23, 2010Date of Patent: February 19, 2013Assignee: National Taipei University of TechnologyInventors: Tzyy-Jiann Wang, Yueh-Hsun Tsou
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Publication number: 20130039615Abstract: Three dimensionally integrated semiconductor systems include a photoactive device operationally coupled with a current/voltage converter on a semiconductor-on-insulator (SeOI) substrate. An optical interconnect is operatively coupled to the photoactive device. A semiconductor device is bonded over the SeOI substrate, and an electrical pathway extends between the current/voltage converter and the semiconductor device bonded over the SeOI substrate. Methods of forming such systems include forming a photoactive device on an SeOI substrate, and operatively coupling an waveguide with the photoactive device. A current/voltage converter may be formed over the SeOI substrate, and the photoactive device and the current/voltage converter may be operatively coupled with one another. A semiconductor device may be bonded over the SeOI substrate and operatively coupled with the current/voltage converter.Type: ApplicationFiled: August 9, 2011Publication date: February 14, 2013Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIESInventors: Bich-Yen Nguyen, Mariam Sadaka
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Publication number: 20130034922Abstract: A vertical cavity surface emitting laser that includes: a substrate; a first semiconductor multilayer reflector; an active region; a second semiconductor multilayer reflector; a columnar structure formed from the second semiconductor multilayer reflector to the first semiconductor multilayer reflector; a current narrowing layer formed inside of the columnar structure and having a conductive region surrounded by an oxidization region; a first electrode formed at a top of the columnar structure, electrically connected to the second semiconductor multilayer reflector and defining a beam window; a first insulating film comprised of a material with a first refractive index and formed on the first electrode to cover the beam window; and a second insulating film comprised of a material with a second refractive index and formed on the first insulating film, of which a radius is smaller than a radius of the conductive region.Type: ApplicationFiled: October 12, 2012Publication date: February 7, 2013Inventors: Kazutaka Takeda, Masahiro Yoshikawa, Kazuyuki Matsushita
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Patent number: 8367441Abstract: Example embodiments herein relate to a nitride semiconductor light emitting device including a coat film formed at a light emitting portion and including an aluminum nitride crystal or an aluminum oxynitride crystal, and a method of manufacturing the nitride semiconductor light emitting device. Also provided is a nitride semiconductor transistor device including a nitride semiconductor layer and a gate insulating film which is in contact with the nitride semiconductor layer and includes an aluminum nitride crystal or an aluminum oxynitride crystal.Type: GrantFiled: September 23, 2011Date of Patent: February 5, 2013Assignee: Sharp Kabushiki KaishaInventors: Takeshi Kamikawa, Yoshinobu Kawaguchi
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Patent number: 8367434Abstract: Method for fabricating a substrate comprising a nanostructured surface for an organic light emitting diode OLED, in which a layer of an organic resin or of a mineral material having a first nanostructuration is prepared by nano-imprint; the organic resin or mineral material is heated to a temperature equal to or higher than its glass transition temperature Tg or its melting point, and the organic resin or the mineral material is maintained at this temperature for a time tR called annealing time, whereby the organic resin or the mineral material flows and the first nanostructuration of the layer of organic resin or of mineral material is modified to produce a second nanostructuration; the organic resin or the mineral material is cooled.Type: GrantFiled: November 24, 2009Date of Patent: February 5, 2013Assignee: Commissariat a l'Energie AtomiqueInventors: Alexandre Mary, Luc Andre, Stefan Landis
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Patent number: 8367450Abstract: A light emitting system is disclosed. The system comprises an active region having a stack of bilayer quantum well structures separated from each other by barrier layers. Each bilayer quantum well structure is formed of a first layer made of a first semiconductor alloy for electron confinement and a second layer made of a second semiconductor alloy for hole confinement, wherein a thickness and composition of each layer is such that a characteristic hole confinement energy of the bilayer quantum well structure is at least 200 meV.Type: GrantFiled: February 21, 2011Date of Patent: February 5, 2013Assignee: Technion Research & Development Foundation Ltd.Inventors: Gad Bahir, Dan Fekete, Asaf Albo
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Publication number: 20130023077Abstract: A method for manufacturing a semiconductor optical device includes the steps of growing a stacked semiconductor layer on a substrate having a cleavage direction in a first direction; forming a first mask having a plurality of openings arranged in the first direction; forming a mark array by etching the stacked semiconductor layer using the first mask; forming a second mask having first and second openings extending in a second direction intersecting the first direction; forming first and second grooves, and a waveguide mesa by etching the stacked semiconductor layer using the second mask; and producing a laser diode bar by cleaving a substrate product including the waveguide mesa. First and second residual marks are formed on the upper surface of the waveguide mesa. First and second transfer marks are formed on the bottoms of the first and the second grooves, respectively.Type: ApplicationFiled: July 16, 2012Publication date: January 24, 2013Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Kenji HIRATSUKA
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Publication number: 20130016942Abstract: Waveguide designs and fabrication methods provide adiabatic waveguide eigen mode conversion and can be applied to monolithic vertical integration of active and passive elements in PICs. An advantage of the designs and methods is a simple fabrication procedure with only a single etching step in combination with subsequent well-controllable selective oxidation. As a result, improved manufacturability and reliability can be achieved.Type: ApplicationFiled: July 13, 2012Publication date: January 17, 2013Applicant: INNOLUME GMBHInventors: Alexey Gubenko, Igor Krestnikov, Sergey Mikhrin, Daniil Livshits, Greg Wojcik, Alexey Kovsh
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Patent number: 8355422Abstract: A GaN edge emitting laser is provided comprising a semi-polar GaN substrate, an active region, N-side and P-side waveguiding layers, and N-type and P-type cladding layers. The GaN substrate defines a 20 21 crystal growth plane and a glide plane. The N-side and P-side waveguiding layers comprise a GaInN/GaN or GaInN/GaInN superlattice (SL) waveguiding layers. The SL layers of the N-side and P-side SL waveguiding layers have layer thicknesses between approximately 1 nm and 5 nm that are optimized for waveguide planarity. In another embodiments, planarization is enhanced by ensuring that the N-side and P-side GaN-based waveguiding layers are grown at a growth rate that exceeds approximately 0.09 nm/s, regardless of whether the N-side and P-side GaN-based waveguiding layers are provided as a GaInN/GaN SL, GaInN/GaInN SL or as bulk layers. In further embodiments, planarization is enhanced by selecting optimal SL layer thicknesses and growth rates.Type: GrantFiled: June 11, 2012Date of Patent: January 15, 2013Assignee: Corning IncorporatedInventor: Rajaram Bhat
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Publication number: 20130001643Abstract: A process to form a photodiode (PD) with the waveguide structure is disclosed. The PD processes thereby reduces a scattering of the parasitic resistance thereof. The process includes steps to form a PD mesa stripe, to bury the PD mesa stripe by the waveguide region, to etch the PD mesa stripe and the waveguide region to form the waveguide mesa stripe. In the etching, the lower contact layer plays a role of the etching stopper.Type: ApplicationFiled: June 27, 2012Publication date: January 3, 2013Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Hideki YAGI
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Publication number: 20130003771Abstract: Provided are a distributed feedback laser diode and a manufacturing method thereof. The distributed feedback laser diode includes a first area having a first grating layer disposed in a longitudinal direction, a second area disposed adjacent to the first area and having a second grating layer disposed in the longitudinal direction, and an active layer disposed over the first and second areas. Coupling coefficients of the first and second grating layers are made different in the first and second areas by a selective area growth method. The distributed feedback laser diode includes grating layers each having an asymmetric coefficient and is implemented within an optimal range capable of obtaining both a high front facet output and stable single mode characteristics. Thus, high manufacturing yield and low manufacturing cost can be achieved.Type: ApplicationFiled: May 29, 2012Publication date: January 3, 2013Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Oh Kee KWON, Young Ahn Leem, Dong-Hun Lee, Chul-Wook Lee, Yongsoon Baek, Yun C. Chung
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Patent number: 8346025Abstract: An apparatus 100 that comprises a planar electro-optic modulator 110 being located on a substrate 105 and including a waveguide 115 and electrical contacts 120. The waveguide that includes first and second substantially straight segments 122, and a curved segment 126 that serially end-connects the first and second substantially straight segments such that light 130 travels in a substantially anti-parallel manner in the first and second substantially straight segments. The electrical contacts being located adjacent the first and second substantially straight segments and being connected to produce constructively adding phase modulations on an optical carrier passing through the segments.Type: GrantFiled: May 18, 2009Date of Patent: January 1, 2013Assignee: Alcatel LucentInventor: Douglas M. Gill
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Patent number: 8338200Abstract: A method of fabricating a frontside-illuminated inverted quantum well infrared photodetector may include providing a quantum well wafer having a bulk substrate layer and a quantum material layer, wherein the quantum material layer includes a plurality of alternating quantum well layers and barrier layers epitaxially grown on the bulk substrate layer. The method further includes applying at least one frontside common electrical contact to a frontside of the quantum well wafer, bonding a transparent substrate to the frontside of the quantum well wafer, thinning the bulk substrate layer of the quantum well wafer, and etching the quantum material layer to form quantum well facets that define at least one pyramidal quantum well stack. A backside electrical contact may be applied to the pyramidal quantum well stack. In one embodiment, a plurality of quantum well stacks is bonded to a read-out integrated circuit of a focal plane array.Type: GrantFiled: February 2, 2011Date of Patent: December 25, 2012Assignee: L-3 Communications Cincinnati Electronics CorporationInventors: David Forrai, Darrel Endres, Robert Jones, Michael James Garter