Abstract: According to one exemplary embodiment, a method for forming an NPN and a vertical PNP device on a substrate comprises forming an insulating layer over an NPN region and a PNP region of the substrate. The method further comprises forming a buffer layer on the insulating layer and forming an opening in the buffer layer and the insulating layer in the NPN region, where the opening exposes the substrate. The method further comprises forming a semiconductor layer on the buffer layer and in the opening in the NPN region, where the semiconductor layer has a first portion situated in the opening and a second portion situated on the buffer layer in the PNP region. The first portion of the semiconductor layer forms a single crystal base of the NPN device and the second portion of the semiconductor layer forms a polycrystalline emitter of the vertical PNP device.

Abstract: A semiconductor device for an integrated injection logic cell having a pnp bipolar transistor structure formed on a semiconductor substrate, wherein at least one layer of insulating films formed on a base region of the pnp bipolar transistor structure is comprised of a silicon nitride film. The semiconductor device of the present invention is advantageous in that the silicon nitride film constituting at least one layer of the insulating films formed on the base region of the pnp bipolar transistor prevents an occurrence of contamination on the surface of the base region, so that both the properties of the pnp bipolar transistor and the operation of the IIL cell can be stabilized. Further, by the process of the present invention, the above-mentioned excellent semiconductor device can be produced.

Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device.

Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device.

Abstract: A method of fabricating a bipolar transistor structure that provides unit current gain frequency (fT) and maximum oscillation frequency (fMAX) improvements of a raised extrinsic base using non-self-aligned techniques to establish a self-aligned structure. Accordingly, the invention eliminates the complexity and cost of current self-aligned raised extrinsic base processes. The invention forms a raised extrinsic base and an emitter opening over a landing pad, i.e., etch stop layer, then replaces the landing pad with a conductor that is converted, in part, to an insulator. An emitter is then formed in the emitter opening once the insulator is removed from the emitter opening. An unconverted portion of the conductor provides a conductive base link and a remaining portion of the insulator under a spacer isolates the extrinsic base from the emitter while maintaining self-alignment of the emitter to the extrinsic base. The invention also includes the resulting bipolar transistor structure.

Abstract: A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.

Abstract: A method for manufacturing a gate spacer for self-aligned contacts is provided. A gate stack is formed on a semiconductor substrate. A conformal dielectric layer is then formed over the gate stack. An etch-stop material layer, e.g., a photoresist layer, is formed over the conformal dielectric layer. Next, an upper portion of the etch stop material layer is removed to expose an upper portion of the conformal dielectric layer by techniques such as etching back. Subsequently, the exposed conformal dielectric layer is etched back using the remaining etch-stop material layer as an etch stopper. The remaining etch-stop material layer is removed and the etched-back conformal dielectric layer is again etched back to form a gate spacer.

Abstract: A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe) on the field. The self-aligned mask is fabricated by taking advantage of the fact that poly Si (or Si/SiGe) oxidizes faster than single crystal Si (or Si/SiGe). An oxide film is formed over both the poly Si (or Si/siGe) and the single crystal Si (or Si/siGe) by using an thermal oxidation process to form a thick oxidation layer over the poly Si (or Si/siGe) and a thin oxidation layer over the single crystal Si (or Si/siGe), followed by a controlled oxide etch to remove the thin oxidation layer over the single crystal Si (or Si/siGe) while leaving the self-aligned oxide mask layer over the poly Si (or Si/siGe). A raised extrinsic base is then formed following the self-aligned mask formation.

Abstract: The present invention provides a method of forming a TFT and a reflective electrode having recesses or projections with reduced manufacturing cost and a reduced number of manufacturing steps, and provides a liquid crystal display device to which the method is applied. A photosensitive film 8 is formed on a metal film 7. Then, remaining portions 81, 82 and 83 are formed from the photosensitive film 8. Then, the metal film 7 is etched by using the remaining portions 81, 82 and 83 as masks. And then, a photosensitive film 9 and a reflective electrode film 10 are formed without removing the remaining portions 81, 82 and 83.

Abstract: According to one exemplary embodiment, a method for fabricating a bipolar transistor, such as a heterojunction bipolar transistor (“HBT”), comprises fabricating a first inner spacer and a second inner spacer on a top surface of a base. The method further comprises forming a first outer spacer adjacent to the first inner spacer and a second outer spacer adjacent to the second inner spacer. According to this exemplary embodiment, the method further comprises depositing an emitter between the first and second inner spacers on the top surface of the base. The method may further comprise depositing an intermediate oxide layer on the first and second outer spacers after forming the first and second outer spacers. The method may further comprise depositing an amorphous layer on the intermediate oxide layer. The method may also comprise depositing an antireflective coating layer on the amorphous layer.

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises first and second link spacers situated on the top surface of the base. The bipolar transistor further comprises a sacrificial post situated on the top surface of the base between the first and second link spacers. The first and second link spacers may have a height, for example, approximately equal to or, in another embodiment, substantially less than a height of the sacrificial post. According to this exemplary embodiment, the bipolar transistor further comprises a non-sacrificial planarizing layer situated over the sacrificial post, first and second link spacers, and base. The non-sacrificial planarizing layer may comprise, for example, silicate glass. The sacrificial planarizing layer may have a height, for example, approximately equal to or, in another embodiment, greater than greater than a height of the first and second link spacers.

Abstract: A disclosed embodiment is a method for fabricating an emitter structure, comprising a step of conformally depositing an undoped polysilicon layer in an emitter window opening and over a base. Next, a doped polysilicon layer is non-conformally deposited over the undoped layer. Thereafter, the steps of conformally depositing an undoped polysilicon layer and non-conformally depositing a doped polysilicon layer are repeated until the emitter window opening is filled. The method can further comprise a step of activating dopants. In another embodiment, an emitter structure is fabricated according to the above method.

Abstract: A dielectric layer is etched to form an opening in dielectric layer. A gate oxide layer is formed on semiconductor substrate in said opening. A barrier conductor is formed along the surface of the opening. A metal layer is formed on the barrier conductor and refilled into the opening. A portion of the metal layer and the barrier conductor is removed to form a gate for said transistor. The dielectric layer is removed. The barrier conductor is removed on sidewall of the gate. Lightly doped drain region is formed in the semiconductor substrate. Next, Sidewall spacer is formed on sidewall of the gate. Then, source and drain is formed in the semiconductor substrate by ion implantation using the gate and spacer as masking.

Abstract: A low-power bipolar transistor is formed to have an intrinsic emitter region with a sub-lithographic width, and an oxide layer that is self aligned to an overlying extrinsic emitter. The small extrinsic emitter region reduces the maximum current that can flow through the transistor, while the self-aligned oxide layer and extrinsic emitter reduces the base-to-emitter junction size and device performance variability across the wafer.

Abstract: The present disclosure provides a process for producing a SiGe layer in a bipolar device having a reduced amount of gaps or discontinuities on a shallow trench isolation (STI) region use for a base electrode connection. The process is used for forming an SiGe layer for use in a semiconductor device. The process includes doping a single crystal substrate with a first dopant type, baking the doped single crystal substrate at a temperature less than 900° C., and at a pressure less than 100 torr; and depositing the SiGe layer on the baked single crystal substrate (epi SiGe) to serve as the base electrode and on the STI region (poly SiGe) to serve as a connection for the base electrode. The semiconductor device is thereby created from the combination of the doped single crystal substrate and the deposited SiGe layer.

Abstract: The present invention proposes a novel method to fabricate a Bipolar Junction Transistor device. The steps of the present invention include forming a shallow trench isolation structure in a substrate. An oxide layer is formed on the substrate. Subsequently, a polysilicon layer is next formed on the oxide layer, and the polysilicon layer has first type ion. Successively, a polysilicon layer is patterned on the oxide layer. The next step is to perform a second type ion implantation, thereby forming a collector region in the substrate and below the emitter window. The oxide layer is removed inside the emitter window. An expitaxy base is then formed on the polysilicon layer and substrate, thereby forming base region on the collector region, wherein the expitaxy base has the first type ion. After the expitaxy base is formed, a dielectric layer is formed over the expitaxy base. Next, the dielectric layer is etched to form inner spacer on sidewalls of the expitaxy base inside the emitter window.

Abstract: An Si/SiGe layer including an Si buffer layer, an SiGe spacer layer, a graded SiGe layer and an Si cap layer is epitaxially grown in a region corresponding to a collector opening while a polycrystalline layer is deposited on the upper surface of a nitride film, and side surfaces of an oxide film and the nitride film. In this case, the Si buffer layer is formed first and then other layers such as the SiGe spacer layer are formed, thereby ensuring non-selective epitaxial growth. Then, a polycrystalline layer is deposited over the nitride film.

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a top surface. The heterojunction bipolar transistor further comprises a first spacer and a second spacer situated on the top surface of the base. The heterojunction bipolar transistor further comprises an intermediate oxide layer situated on the first and second oxide spacers. The heterojunction bipolar transistor further comprises an amorphous layer situated on the intermediate oxide layer. The heterojunction bipolar transistor further comprises an antireflective coating layer on the amorphous layer. The heterojunction bipolar transistor further comprises an emitter window opening situated between the first and second spacers, where the emitter window opening is defined by the top surface of the base, the first and second spacers, the intermediate oxide layer, the amorphous layer, and the antireflective coating layer.

Abstract: A semiconductor device and method of fabricating the device. An emitter region is formed self centered and self aligned symmetrically with a base region. Using frontside processing techniques, a collector is formed symmetrically self-aligned with the base region and the emitter region. The collector region may be further formed self-centered with the base region using backside processing techniques. The self-aligned and self-centered symmetric structure virtually eliminates parasitic elements in the device significantly improving the device performance. The device is scalable on the order of approximately 0.1 microns. The method also provides reproduceability and repeatability of device characteristics necessary for commercial manufacture of the symmetric device.

Abstract: A method for manufacturing a semiconductor device having a non-volatile memory transistor may include the steps of forming a floating gate 22 over a semiconductor layer 10 through a first insulation layer 20, forming a second insulation layer 26 that contacts the floating gate 22, forming a control gate 28 over the second insulation layer 26, forming a source region 14 and a drain region 16 in the semiconductor layer 10, depositing a insulation layer 40 over the semiconductor layer 10, and etching the insulation layer 40 to form a sidewall insulation layer, wherein the etching of the insulation layer 40 is conducted such that the insulation layer 40 remains above the floating gate 40, and the floating gate 22 is not exposed.

Abstract: A transistor fabrication method comprises: sequentially forming a pad oxide film and a silicon nitride film on a semiconductor substrate; etching the substrate to form a trench; sequentially forming a first oxide film within the trench and a cylindrical insulation spacer at a lateral portion of the first oxide film; forming an insulation pattern; etching the silicon nitride film, the insulation pattern and the insulation spacer; removing the pad oxide film; removing the insulation spacer and the first oxide film; sequentially forming source/drain regions and LDD regions at both sides of the trench, under the remaining insulation pattern; forming a second oxide film; sequentially forming a channel stop layer between the LDD regions and a punch stop layer under the channel stop layer; and sequentially forming a gate insulation film and a gate region within the trench and the second oxide layer.

Abstract: A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has an emitter region characterized by a y-shaped structure formed from bilayer polysilicon. The bilayer polysilicon includes a first polysilicon emitter structure and a second polysilicon emitter structure. The method of forming the bipolar transistor includes forming an emitter stack on a substrate. The emitter stack comprises the first polysilicon emitter structure and a plug structure. The emitter stack defines the substrate into a masked portion and exposed adjacent portions. The exposed adjacent portions are selectively doped with a dopant to define an extrinsic base region, wherein the dopant is blocked from entering the masked portion. After selectively doping the extrinsic base region, the plug structure is removed from the emitter stack and the second polysilicon emitter structure is formed on the first polysilicon emitter structure to define the emitter region of the bipolar transistor.

Abstract: A method for forming a self-aligned bipolar transistor includes the steps of combination etching a silicon substrate in an opening to form a concave surface on the silicon substrate, and forming an intrinsic base and an associated emitter on the concave surface. The combination etching includes an isotropic etching and subsequent wet etching. The concave surface increases the distance between the external base for the intrinsic base and the emitter to thereby increase the emitter-base breakdown voltage.

Abstract: In the manufacture of integrated semiconductor structures, the problem frequently occurs that the resistance of polysilicon structures employed as interconnects must be selectively lowered. In order to reduce the resistance of a polysilicon structure, the structure is often provided with a silicide layer. However, the manufacturing problem occurs when siliconizing only specific polysilicon structures but not siliconizing others, for example those that are to be employed for resistors.

Abstract: Methods of constructing silicon carbide semiconductor devices in a self-aligned manner. According to one aspect of the invention, the method may include forming a mesa structure in a multi-layer laminate including at least a first and second layer of silicon carbide material. The mesa structure may then be utilized in combination with at least one planarization step to construct devices in a self-aligned manner. According to another aspect of the present invention, the mesa structure may be formed subsequent to an ion implantation and anneal steps to construct devices in a self-aligned manner. According to another aspect of the present invention, a high temperature mask capable of withstanding the high temperatures of the anneal process may be utilized to form devices in a self-aligned manner.

Abstract: A method for fabricating bipolar transistor having insitu-formed epitaxial base is disclosed herein, the method including the following steps. The first step of the key feature according to one preferred embodiment of the present invention is to use a first epitaxial process to selectively grow an epitaxial collector layer in the etched first oxide layer. The first oxide layer is formed on a buried layer, which is formed on the silicon substrate. Then utilize a second epitaxial process to subsequently grow a first epitaxial-base layer and a second epitaxial-base layer. Particularly the second epitaxial process and the first epitaxial process are performed insitu. Then a patterned oxide layer and poly silicon layer are formed on the second epitaxial-base layer. Followed by etching the poly silicon layer and the patterned oxide layer, the second epitaxial-base layer is implanted, which together with the first epitaxial-base layer are etched.

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a top surface. The heterojunction bipolar transistor further comprises a first spacer and a second spacer situated on the top surface of the base. The heterojunction bipolar transistor further comprises an intermediate oxide layer situated on the first and second oxide spacers. The heterojunction bipolar transistor further comprises an amorphous layer situated on the intermediate oxide layer. The heterojunction bipolar transistor further comprises an antireflective coating layer on the amorphous layer. The heterojunction bipolar transistor further comprises an emitter window opening situated between the first and second spacers, where the emitter window opening is defined by the top surface of the base, the first and second spacers, the intermediate oxide layer, the amorphous layer, and the antireflective coating layer.

Abstract: Disclosed are a method for manufacturing a homojunction or heterojunction bipolar device and a structure of the bipolar device manufactured by the method.

Abstract: A method for producing structures in chips is realized by carrying out a sequence of structuring steps in a self-adjusting manner. By structuring a first auxiliary layer applied on a substrate, a first masking structure is formed after a first masking procedure, which first masking structure has at least one partial region projecting beyond the surface of the substrate. After this, a further structuring step is carried out, for instance, by etching, implantation or CVD, using the previously produced first masking structure as a mask. After this, the first masking structure with a view to forming a second masking structure is inverted by applying at least one second auxiliary layer onto the first masking structure. The thus formed structure is at least partially taken off and the thus denuded first auxiliary layer is selectively removed, whereupon the second masking structure is used as a mask for a further structuring step.

Abstract: A Heterojunction Bipolar Transistor (HBT) is provided where the SiGe base region is formed through selective deposition, after the formation of the base electrode layer and the emitter window. A sacrificial oxide layer is deposited between the collector and base electrode. The contact to the SiGe base is made at an extrinsic area, underneath the base electrode, after removal of the sacrificial oxide. The SiGe is covered with a temporary oxide layer during further processes, and this protective layer is removed immediately before the deposition of the emitter material. The selective deposition of the SiGe at a relatively late stage of the fabrication process helps insure that the film remains free of the stresses which can degrade electron mobility. A process of fabricating the above-described HBT device is also provided.

Abstract: In a method for integrating a high-voltage device and a low-voltage device, a substrate includes a first isolation region separating a high-voltage device region and a low-voltage device region, a second isolation region formed in a scribe region, and a patterned insulating layer that exposes the first and second isolation regions. A patterned photoresist, formed over the substrate, exposes a portion of the patterned insulating layer in the high-voltage device region and a portion of the second isolation region in the scribe region. A doped region and a trench are respectively formed in the substrate under the exposed portion of the patterned insulating layer and in the exposed portion of the second isolation region. The patterned photoresist and the patterned insulating layer are subsequently removed. First and second gate structures are respectively formed in the high-voltage and low-voltage device regions by using the trench as an alignment mark.

Abstract: A method of forming an NPN semiconductor device includes the steps of forming a collector region within a substrate, forming a base region over the collector region, and forming an oxide-nitride-oxide stack over the base region. Once these three structures are formed, an opening is created through the oxide-nitride-oxide stack to expose the top surface of the base region. Then, a doped polysilicon material is used to fill the opening and make electrical contact to the base region. The use of the oxide-nitride-oxide stack with appropriate etching of the opening eliminates the exposure of the base region to reactive ion etch environment typical of prior art methods for forming NPN semiconductor devices. As an option, after the opening of the oxide-nitride-oxide stack is formed, a local oxidation of silicon (LOCOS) and etched can be preformed to create oxide spacers to line the opening wall above the base region.

Abstract: An improved gate electrode provides greater tolerances to higher temperature annealing treatments, and is useful in connection with the formation of self-aligned contacts as are needed for high density embedded DRAM applications. Consistent with one embodiment, a process for manufacturing a polycide transistor gate electrode involves forming a cap dielectric and dielectric spacer, with the electrode exhibiting a reduced diffusion transport of dopants between an underlying doped polysilicon layer and an overlying suicide layer. The reduced transport results from the presence of a thin barrier layer between the doped polysilicon layer and silicide layer, and the gate electrode process forms a thermally-oxidized thin polysilicon side-wall film against the polysilicon layer, the barrier layer, the silicide layer, and the cap dielectric layer. The polysilicon side-wall film is used for blocking substantial oxidation of the barrier film.

Abstract: This invention relates to a bi-polar transistor and a procedure for its manufacture. The task of the invention is to propose a bi-polar transistor and a procedure for its manufacture that eliminates the disadvantages of conventional arrangements for a simple polysilicon technology with differential epitaxy for the manufacture of the base, in order to further improve especially the high-speed properties of a bi-polar transistor, to produce highly conductive connections between the metal contacts and the active (inner) transistor region as well as a minimized passive transistor surface, and to simultaneously avoid any additional process complexity and increased contact resistance. This invention resolves the task in that, by creating suitable epitaxy process conditions, the polysilicon layer is deposited on the insulator zone with a greater thickness than the epitaxy layer in the active transistor zone.

Abstract: A memory cell is provided. The memory cell includes a field-effect transistor having a source region, a drain region and a gate coupled to a wordline. The memory cell also includes a vertical bipolar junction transistor that is biased for use of the reverse base current effect to store data. The bipolar junction transistor has an emitter region formed within a source/drain region of the field-effect transistor. The emitter region is self-aligned with a minimum dimension isolation region adjacent to the memory cell and is coupled to a ground line. A portion of the source/drain region acts as the base of the bipolar junction transistor.

Abstract: The process includes successively forming, over a base region of a semiconductor substrate, a poly-Ge or poly-SiGe layer, an etch-stop layer over a selected zone of the Ge or SiGe layer, a layer of poly-Si of the same conductivity type as the base region, then an outer layer of dielectric material. Etching the layers includes stopping at the stop layer to form an emitter window preform, removing the stop film and selectively removing the Ge or SiGe layer in the emitter window preform to form an emitter window and to form an emitter made of poly-Si of conductivity type the opposite of the base region in the window.

Abstract: A process used in the fabrication of a self-aligned non-selective thin-epi-base silicon germanium (SiGe) heterojunction bipolar transistor (HBT) BiCMOS. The process involves using TEOS or Spin-On-Glass (SOG) silicon dioxide etchback in the fabrication of the SiGe BiCMOS device.

Abstract: A method of forming a landed polysilicon plug in a self-aligned contact. A substrate having a plurality of gate electrodes thereon is provided. Before forming the self-aligned contact window, a dielectric liner layer conformal to a surface profile of the substrate and the gate electrodes is formed. An inter-layer dielectric layer is next formed over the dielectric liner layer. High etching selectivity ratio between the inter-layer dielectric layer and the dielectric liner layer is chosen, and thus the dielectric liner layer is used as an etching stop layer in the process of etching out the self-aligned contact window. After a polysilicon layer that fills the self-aligned contact window and covers the dielectric layer is formed, planarization is carried out to form the landed polysilicon plug having a desired thickness.

Abstract: The present invention is related to a bipolar transistor in which the in-situ doped epitaxial Si or SiGe base layer is used instead of using an ion-implanted Si base, in order to achieve higher cutoff frequency. The SiGe base having the narrower energy bandgap than the Si emitter allows to enhance the current gain, the cutoff frequency (fT), and the maximum oscillation frequency (fmax). The narrow bandgap SiGe base also allows to have higher base doping concentration. As a result, the intrinsic base resistance is lowered and the noise figure is thus lowered. Parasitic base resistance is also minimized by using a metallic silicide base ohmic electrode. The present invention is focused on low cost, high repeatability and reliability by simplifying the manufacturing process step.

Abstract: The invention relates to semiconductor devices having a bipolar transistor to form an isolation area within a base electrode contact area to ensure stable contact of the base electrode. The bipolar transistor formed in the transistor area is in the form of an island and is rectangular when view from above. The isolation area is formed of a dielectric material around the transistor area, and the base area is formed around the emitter area which forms the central area of the transistor area. A contact groove is formed at the inner interface of the isolation groove which faces the outer surface of the transistor area, and a part of the base electrode is buried in the contact groove and faces at least one of the upper surface of the transistor area and an inner surface of the contact groove.

Abstract: A synthetic polymer yarn comprising a bicomponent yarn and a second yarn combined to form a single yarn is disclosed. The bicomponent yarn is made up from a first component and a second component each comprised of a fiber-forming polymer and each having different shrinkages from the other to effectuate a bulking effect. This differential shrinkage may be obtained, for example, by using different polymers or similar polymers having different relative viscosities. The synthetic polymer yarn of the present invention has advantageously exhibited an improved visual effect, including a stratified effect, which improves the visual composition of products produced using the yarn. Moreover, the fabrics produced from the yarn have improved hand and stretch and recovery.

Abstract: A semiconductor device and method of fabricating the device. An emitter region is formed self centered and self aligned symmetrically with a base region. Using frontside processing techniques, a collector is formed symmetrically self-aligned with the base region and the emitter region. The collector region may be further formed self-centered with the base region using backside processing techniques. The self-aligned and self-centered symmetric structure virtually eliminates parasitic elements in the device significantly improving the device performance. The device is scalable on the order of approximately 0.1 microns. The method also provides reproduceability and repeatability of device characteristics necessary for commercial manufacture of the symmetric device.

Abstract: The present invention is related to a bipolar transistor in which the in-situ doped epitaxial Si or SiGe base layer is used instead of using an ion-implanted Si base, in order to achieve higher cutoff frequency. The SiGe base having the narrower energy bandgap than the Si emitter allows to enhance the current gain, the cutoff frequency (fT), and the maximum oscillation frequency (fmax). The narrow bandgap SiGe base also allows to have higher base doping concentration. As a result, the intrinsic base resistance is lowered and the noise figure is thus lowered. Parasitic base resistance is also minimized by using a metallic silicide base ohmic electrode. The present invention is focused on low cost, high repeatability and reliability by simplifying the manufacturing process step.

Abstract: A process for fabricating a bipolar junction transistor, featuring the use of multiple self-aligned collector regions, used to limit the width of the base region of the transistor, has been developed. The self-aligned collector regions are formed via multiple ion implantation procedures, performed through, and self-aligned to, an overlying emitter opening, in an oxide layer. The self-aligned collector regions, completely fill the space in the lighter doped collector region, located between the overlying base region, and the underlying subcollector region.

Abstract: A method of forming self aligned contacts in silicon integrated circuit wafers which has a reduced contact resistance is described. A contact hole formed in a layer of dielectric is filled with polysilicon using a split polysilicon process. A first polysilicon layer is deposited after the contact hole is opened. The first polysilicon is preferably, but not necessarily, high temperature film doped polysilicon. The first polysilicon is then treated using C2F6/O2. A second polysilicon layer, preferably furnace doped polysilicon, is then deposited to completely fill the contact hole. The wafer is then planarized, using chemical mechanical polishing or back etching, leaving polysilicon completely filling the contact hole and forming a low resistance contact.

Abstract: The process includes successively forming, over a base region of a semiconductor substrate, a poly-Ge or poly-SiGe layer, an etch-stop layer over a selected zone of the Ge or SiGe layer, a layer of poly-Si of the same conductivity type as the base region, then an outer layer of dielectric material. Etching the layers includes stopping at the stop layer to form an emitter window preform, removing the stop film and selectively removing the Ge or SiGe layer in the emitter window preform to form an emitter window and to form an emitter made of poly-Si of conductivity type the opposite of the base region in the window.

Abstract: A method of manufacturing a semiconductor device includes the step of doping an N-type impurity via a selective region formed on a semiconductor substrate by lithography, the step of doping a P-type impurity in the semiconductor substrate subsequent to the doping step without forming a selective region by lithography, and the step of self-aligningly forming an N-diffusion layer and a P-diffusion layer by performing wet oxidation with respect to the semiconductor substrate in which the N-type impurity and the P-type impurity are doped.

Abstract: In accordance with the above first embodiment of the present invention, after a base polysilicon film has been grown, a lump anneal is carried out because of an extremely small variation to the silicon dioxide film. Subsequently, a buffered fluorine acid is used which has a large selective etching ratio of the silicon oxide film to the polysilicon film to side-etch the silicon oxide film in the horizontal direction by a predetermined width before the base impurity BF2+ is implanted and then the emitter polysilicon film is formed. For those reasons, a variation in distance between the n+-substrate and a collector is small. The base width “WB” of the base region is not varied, whereby variations in high frequency performance of the bipolar transistor are suppressed.

Abstract: Bipolar junction transistors utilize trench-based base electrodes and lateral base electrode extensions to facilitate the use of preferred self-alignment processing techniques. A bipolar junction transistor is provided that includes an intrinsic collector region of first conductivity type in a semiconductor substrate. A trench is also provided in the substrate. This trench extends adjacent the intrinsic collector region. A base electrode of second conductivity type is provided in the trench and a base region of second conductivity type is provided in the intrinsic collector region. This base region is self-aligned to the base electrode and forms a P-N rectifying junction with the intrinsic collector region. An emitter region of first conductivity type is also provided in the base region and forms a P-N rectifying junction therewith.

Abstract: A semiconductor device including a current source having a first node coupled to a terminal, and a second node for extracting a current in response to an electrostatic discharge (ESD) on the terminal. The semiconductor device further including a transistor having a control electrode, a first current electrode coupled to the terminal, and a second current electrode coupled to the second node of the current source, and including a resistive element coupled to a first voltage reference node and the second node of the current source. The transistor of the semiconductor device is biased by detecting a negative voltage event (such as an ESD) at a first current electrode of the transistor and biasing a second current electrode of the transistor in response to detecting the negative voltage event, wherein the biasing of the second current electrode is for preventing a forward biasing of an p-n junction associated with the transistor.