Abstract: A process for fabricating a bipolar junction transistor, featuring an N type, polysilicon emitter structure, located in an emitter trench, and featuring a narrow width. P type base region, located directly underlying an N type, emitter region, which is formed in the semiconductor substrate, along the vertical and horizontal sides of the emitter trench, has been developed. The process features forming an emitter trench in a semiconductor substrate, followed by a large angle ion implantation procedure, used to form a P type, base region, in an area of the semiconductor substrate located along the sides of the emitter trench. Formation of a polysilicon emitter structure, followed by an anneal cycle, create a narrow width, emitter region, underlying the polysilicon emitter structure, also resulting in the formation of a narrow width, P type base region, located between the overlying N type emitter region, and an underlying N type, epitaxial silicon layer.

Abstract: A process is set forth for providing a self-aligned, vertical bipolar transistor. A controlled technique is provided for providing the base and emitter features of the transistor with appropriate dimensions and properties to be useful in high frequency microwave applications. A microwave transistor is provided by this technique.

Abstract: A method of fabricating a self-aligned bipolar junction transistor in a semiconductor structure having a first layer of silicon carbide generally having a first conductivity type and a second layer of silicon carbide generally having a second conductivity type, opposite to the first conductivity type. The method comprises forming a pillar in the second silicon carbide layer, the pillar having a side wall and defining an adjacent horizontal surface on the second layer, forming a dielectric layer having a predetermined thickness on the second semiconductor layer, including the side wall and the horizontal surface. After formation of the dielectric layer, the dielectric layer on a portion of the horizontal surface adjacent the side wall is anisotropically etched while at least a portion of the dielectric layer remains on the side wall, thereby exposing a portion of the horizontal surface.

Abstract: A bipolar transistor is described whose I-V curve is such that it operates in two regions, one having low gain and low power consumption and another having higher gain and better current driving ability. Said transistor has a base region made up of two sub regions, the region closest to the emitter having a resistivity about an order a magnitude lower than the second region (which interfaces with the collector). A key feature of the invention is that the region closest to the collector is very uniformly doped, i.e. there is no gradient or built-in field present. In order to produce such a region, epitaxial growth along with boron doping is used rather than more conventional techniques such as ion implantation and/or diffusion.

Abstract: The invention provides a method for fabricating ultra-shallow, low resistance junctions. In the preferred embodiment, a nitrogen containing screen oxide layer is formed on an undoped area of a substrate by poly re-oxidation using rapid thermal processing in a nitrogen containing atmosphere. Impurity ions are implanted into the substrate, in the undoped area, through the nitrogen containing screen oxide layer to form lightly doped source and drain regions. A post-implant anneal is performed on the lightly doped source and drain regions using a rapid thermal anneal in a nitrogen containing atmosphere. The nitrogen containing screen oxide layer: prevents surface dopant loss during post implant anneal; prevents gate oxide degradation during ion implantation and screen oxide stripping; and acts as a diffusion barrier, reducing oxygen enhanced diffusion. Alternatively, the poly re-oxidation can be performed in an O2 atmosphere followed by a rapid thermal anneal in a nitrogen containing atmosphere.

Abstract: A method for forming a self-aligned contact for a trench DMOS transistor comprises: providing a semiconductor substrate; etching a trench into the semiconductor substrate at a selected location on the surface of the semiconductor substrate; forming a first dielectric layer that covers the semiconductor substrate and walls of the trench; forming a plug in the trench, which comprises a step of depositing a semiconductor layer that covers the semiconductor substrate and fills in the trench, and a step of etching the semiconductor layer until the plug is below the trench for about 0.2 to 0.3 micron; forming a second dielectric layer on the plug; and forming a conductive layer over the second dielectric layer and the surface of the semiconductor substrate for ohmic contact regions.

Abstract: A process for fabricating a bipolar junction transistor, (BJT), featuring reduced junction capacitance, resulting from the decreased dimensions of extrinsic, and intrinsic base, regions, has been developed. The BJT device, is comprised with only a single polysilicon level, used for the emitter structure, while an extrinsic base, and intrinsic base region, are accommodated in an epitaxial silicon layer, grown on an underlying silicon, active device region, and grown on a silicon seed layer, which in turn overlays insulator isolation regions. A boron doped, intrinsic base region can be formed in an undoped version of the epitaxial silicon layer, or the boron doped, intrinsic base region can be contained in the as deposited, epitaxial silicon layer, or contained in an as deposited, epitaxial, silicon-germanium layer.

Abstract: A new method is provided for the creation of an ESD protection device for deep submicron semiconductor technology. An STI trench is created and filled with oxide. The surface of the STI region is polished after which a gate structure is created over the STI region. A high energy ESD implant is performed that is self-aligned with the created gate structure after which the EDS device structure is completed by implanting the source and drain regions of the ESD device.

Abstract: A process for forming a self-aligned BJT (bipolar junction transistor) is disclosed. Conventional front end processes are used to form an N+ layer on a substrate. An N-type collector region is then formed followed by formation of isolation regions on the substrate surface. A deep collection connector region is formed by ion implantation into the N-well. Next, a P base region is formed by ion implantation. An undoped polysilicon (polycide) layer is then deposited on the surface of the substrate. Thereafter, a dielectric layer, which preferably cannot be oxidized, is deposited on top of the undoped polysilicon (polycide) layer. The dielectric layer is then patterned to form a dielectric emitter. Nitride spacers are then formed on the sidewalls of the dielectric emitter. The polysilicon (polycide) layer is then heavily doped with P-type impurities except in the area of the dielectric emitter and nitride spacers.

Abstract: A process used in the fabrication of a self-aligned non-selective thin-epi-base silicon germanium (SiGe) heterojunction bipolar transistor (HBT) BiCMOS. The process involves using TEOS or Spin-On-Glass (SOG) silicon dioxide etchback in the fabrication of the SiGe BiCMOS device.

Abstract: A BiCMOS process where a base region is formed in a relatively highly doped n-type substrate region. Boron is implanted at two different energy levels to form the base region and a counter doped n region near the base collector junction to prevent impact ionization.

Abstract: A semiconductor stacked type dynamic random access memory device has a node contact hole formed in an inter-level insulating layer and a storage electrode held in contact with a source region of an access transistor through the node contact hole, and the node contact hole and the storage electrode are patterned by using a photo-lithography and an etching, wherein a photo-resist mask for the node contact hole is different in thickness from a photo-resist mask for the storage electrode by value equivalent to a half of the period of the periodicity representative of sensitized characteristics of the photo-resist in the presence of an optical standing wave in the photo-resist masks, thereby keeping the nesting tolerance between the two patterns.

Abstract: A method of manufacturing a bipolar transistor in an integrated circuit including the steps of forming a P-type base area, coating this base area with an isolating layer, and forming an opening in the isolating layer at a location where it is desired to form the emitter region. The method further includes coating the structure with an N-type doped polysilicon layer, etching the polysilicon layer to delimit a portion therefrom, forming spacers at a periphery of the polysilicon portion, and implanting a P-type dopant to form a base contact making region, after masking the polysilicon portion, above the area where it is in contact with the base area.

Abstract: A method for making self-aligned sub-micrometer bipolar transistors and FETs on a substrate for BiFET and BiCMOS circuits was achieved using a novel LOCOS structure as a self-aligned implant mask. This LOCOS structure uses a silicon nitride mask comprised of stripes with well defined widths and spacings to form a punchthrough oxide mask of varying thicknesses over the emitter, base, and collector of the bipolar transistor, while providing a thick field oxide elsewhere on the substrate. The oxide mask serves as a self-aligned implant mask for implanting the emitter, base, and collector of the bipolar transistor. The nitride mask can be patterned concurrently to form an implant mask for the FET. A series of ion implants is then used to form the emitter, base, and collector without requiring separate photoresist masks. An array of nitride stripes with well defined widths and spacings can be used to make larger transistors, such as bipolar power transistors.

Abstract: A bipolar fabrication process, illustratively suited for integration into a conventional CMOS process to thereby form a BiCMOS integrated circuits is disclosed. The collector and base are formed through multiple implants and a single masking step to thereby provide a continuous low resistance collector region.

Abstract: In a bipolar transistor and the manufacturing method thereof, the bipolar transistor includes a first conductive well, an emitter impurity layer formed in the center of the well, a base impurity layer formed in the form of completely surrounding the emitter impurity layer, and a first conductive high-concentration collector impurity layer having an annular shape along the edge of the well, and maintaining a constant interval from the base impurity layer. The first conductive layer formed to be parallel with the high-concentration collector impurity layer is connected therewith through a contact hole, and is connected with the collector electrode through another contact hole. Owing to a simple manufacturing process, the processing time and cost can be reduced. Also, parasitic bipolar transistors are not generated nor is increased collector resistance produced, thereby increasing reliability.

Abstract: A high-strength and highly wet-heat-resistant polyvinyl-alcohol-based fiber--in which the crosslinking agent has hardly been oxidized by the heat at the drawing time upon preparation of the fiber, the crosslinking agent has not exhaled so much at the time of dry heat drawing, and the crosslinking agent has penetrated even inside of the fiber so that not only the surface but also the inside of the fiber has sufficiently been crosslinked--can be obtained by the steps of: preparing a polyvinyl-alcohl-based fiber by spinning the polyvinyl-alcohol-based solution, wet drawing the fiber, applying an acetalization compound of an aliphatic dialdehyde having at least 6 carbon atoms to the fiber, subjecting the fiber which contains above compound to dry heat drawing to a total draw ratio of at least 15, and then crosslinking the drawn filament with an acid under mild crosslinking treatment conditions.

Abstract: A vertical PNP transistor and method for making it provide a transistor in a surface layer (12), which may be an epitaxial layer, of P- type conductivity at a surface of a substrate (11) of P+ type conductivity. An isolation region (14) of N- type conductivity in the P- surface layer (12) contains a collector region (25) of P- type conductivity. A base region (30) of N type conductivity is contained in the collector region (25), and an emitter region (40) of P+ type conductivity is contained in the base region (30). The base region (30) may be provided with a higher N type impurity concentration than a P type impurity concentration of the collector region (25). At least the collector region (25) and the base region (30) may be self aligned. The collector region (25) may be of thickness of about 2.2 .mu.m, the base region (30) of thickness of about 0.1 .mu.m, and the emitter region (40) of thickness of about 0.4 .mu.m.

Abstract: A reduced mask set, implant complexity process for manufacturing a (high frequency application) complementary bipolar transistor structure uses the fast lateral diffusion characteristic of a layer of material, that is at least an order of magnitude higher for emitter dopants than in single crystal semiconductor material. Separate base and emitter poly layers are formed undoped. Then, the emitter poly of one device and the edges of the base poly of the other device are exposed through a dopant mask and simultaneously doped. The emitter dopant goes directly into the surface of the emitter poly where it lies over and is in contact with the base. The base contact dopant goes into the edges of the base poly, including the layer of material having the high diffusion coefficient, rapidly diffuses laterally throughout that layer, and then diffuses down into the collector material (e.g. island) surface, to form the extrinsic base.

Abstract: In a method of fabricating a self-aligned bipolar junction transistor with silicide extrinsic base contacts and selective epitaxial grown intrinsic base region, the sinker and buried N+ layer regions are formed in a semiconductor substrate with trench oxide isolation. Thin oxide is then formed on the structure. Next, metal silicide is deposited on the thin oxide and p-dopant implanted into the silicide. LTO is then deposited on the doped silicide followed by deposition of nitride. Next, the nitride, LTO and silicide layers are etched, stopping on the thin oxide layer. The thin oxide is then etched to expose the silicon. The etch undercuts the thin oxide under the nitride. A thin p+ epitaxial base is then selectively grown on the silicon and the metal silicide only. The base can be silicon or a silicon germanium layer to form a heterojunction transistor. Next, thin LTO is deposited followed by deposition of nitride. An RIE of the nitride is then performed to form nitride spacers, stopping on the thin LTO.

Abstract: A method of manufacturing a semiconductor device includes the steps of: depositing a semiconductor film onto a semiconductor substrate, the semiconductor film having a main component which is the same material as the semiconductor substrate; and forming a first insulating layer on the semiconductor substrate. This method also includes the steps of: removing predetermined areas from the first insulating layer and the semiconductor film so as to form an opening; forming a second insulating layer inside the opening and on the first insulating layer; and removing the second insulating layer by anisotropic etching so that the side wall of the opening remains.