Dopant Implantation Or Diffusion Patents (Class 438/369)
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Publication number: 20040082136Abstract: Devices and methods are disclosed related to a bipolar transistor device and methods of fabrication. A top region is formed at a surface of and within a base region. The top region is formed by implanting a dopant of an opposite conductivity to that of the base region. However, the top region remains of the same conductivity type as the base region (e.g., n-type or p-type). This implanting, also referred to as counterdoping, increases resistivity of the top region and thus improves an emitter-base breakdown voltage. Additionally, this implanting does not have a substantial detrimental affect on a beta value, also referred to as an amplification property, or a collector emitter breakdown voltage, also referred to as BVceo, for the transistor. The beta value and the collector emitter breakdown voltage are mainly a function of a bottom portion of the base region.Type: ApplicationFiled: October 24, 2002Publication date: April 29, 2004Inventor: Billy Bradford Hutcheson
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Patent number: 6716712Abstract: During the production of integrated semiconductor structures, it is often necessary to differently dope immediately adjacent regions. A method is provided for producing two adjacent regions of a predetermined area in an integrated semiconductor, whereby a first region of the two adjacent regions includes a doping with a lower target concentration than a second region. The predetermined area of a semiconductor blank is doped with a dopant until a concentration of the dopant is obtained that is at least as high as the target concentration of the second region. A protective layer is applied to the second region, and the dopant is out-diffused from the first region until a concentration of dopant is obtained that corresponds to the target concentration of the first region.Type: GrantFiled: January 22, 2002Date of Patent: April 6, 2004Assignee: Infineon Technologies AGInventor: Josef Böck
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Patent number: 6716713Abstract: Silicon alloys and doped silicon films are prepared by chemical vapor deposition and ion implantation processes using Si-containing chemical precursors as sources for Group III and Group V atoms. Preferred dopant precursors include (H3Si)3-xMRx, (H3Si)3N, and (H3Si)4N2, wherein R is H or D, x=0, 1 or 2, and M is selected from the group consisting of B, P, As, and Sb. Preferred deposition methods produce non-hydrogenated silicon alloy and doped Si-containing films, including crystalline films.Type: GrantFiled: November 13, 2002Date of Patent: April 6, 2004Assignee: Asm America, Inc.Inventor: Michael A. Todd
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Patent number: 6713351Abstract: A double diffused field effect transistor and a method of forming the same is provided. The method begins by providing a substrate of a first conductivity type. Next, at least one dopant species, also of the first conductivity type, is introduced into a surface of the substrate so that the substrate has a nonuniform doping profile. An epitaxial layer of the first conductivity type is formed over the substrate and one or more body regions of a second conductivity type are formed within the epitaxial layer. A plurality of source regions of the first conductivity type are then formed within the body regions. Finally, a gate region is formed, which is adjacent to the body regions.Type: GrantFiled: March 28, 2001Date of Patent: March 30, 2004Assignee: General Semiconductor, Inc.Inventor: Richard A. Blanchard
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Patent number: 6709941Abstract: In a method for manufacturing a semiconductor device, an N type single-crystal silicon substrate having a first silicon oxide film and a P type poly-crystal silicon layer is provided. A silicon nitride film is formed on the P type poly-crystal silicon layer. A side wall of the silicon nitride film is formed in an opening in the P type poly-crystal silicon layer above a portion expected to provide an active region. The first silicon oxide film has an opening therein which is larger than the opening formed in the P type poly-crystal silicon layer. Then, an N type IV-group semiconductor mixed crystal layer having a smaller band gap than silicon to a desired thickness is grown on the single-crystal silicon substrate on which a surface of the portion expected to provide said active region is exposed. A non-doped single-crystal silicon layer is grown on the IV-group semiconductor mixed crystal layer to a desired thickness.Type: GrantFiled: November 6, 2002Date of Patent: March 23, 2004Assignee: Oki Electric Industry Co., Ltd.Inventor: Hirokazu Fujimaki
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Publication number: 20040033671Abstract: A bipolar transistor, and manufacturing method therefor, with a substrate having a collector region and a base structure provided thereon. An emitter structure is formed over the base structure and an extrinsic base structure is formed over the base structure and over the collector region beside and spaced from the emitter structure. A dielectric layer is deposited over the substrate and connections are formed to the extrinsic base structure, the emitter structure and the collector region.Type: ApplicationFiled: August 19, 2002Publication date: February 19, 2004Inventors: Purakh Raj Verma, Shao-fu Sanford Chu
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Patent number: 6686250Abstract: A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has an emitter region characterized by a y-shaped structure formed from bilayer polysilicon. The bilayer polysilicon includes a first polysilicon emitter structure and a second polysilicon emitter structure. The method of forming the bipolar transistor includes forming an emitter stack on a substrate. The emitter stack comprises the first polysilicon emitter structure and a plug structure. The emitter stack defines the substrate into a masked portion and exposed adjacent portions. The exposed adjacent portions are selectively doped with a dopant to define an extrinsic base region, wherein the dopant is blocked from entering the masked portion. After selectively doping the extrinsic base region, the plug structure is removed from the emitter stack and the second polysilicon emitter structure is formed on the first polysilicon emitter structure to define the emitter region of the bipolar transistor.Type: GrantFiled: November 20, 2002Date of Patent: February 3, 2004Assignee: Maxim Integrated Products, Inc.Inventors: Alexander Kalnitsky, Michael Rowlandson, Fanling H. Yang, Sang Park, Robert F. Scheer
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Patent number: 6677215Abstract: There is provided a method including the steps of: forming spaced gate patterns on a main surface of a semiconductor substrate; forming sidewall films on the gate patterns, respectively, at their respective sidewalls facing each other; and, with the gate patterns and the sidewall films used as a mask, implanting a dopant in the semiconductor substrate to form a doped region. The doped region and a substrate region adjacent thereto together form a diode protecting a gate electrode of a field effect transistor. The doped region as a constituent of the diode can be minimized in size to be smaller than a limit of resolution.Type: GrantFiled: December 4, 2002Date of Patent: January 13, 2004Assignee: Renesas Technology Corp.Inventor: Yasuo Yamaguchi
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Patent number: 6660608Abstract: A CMOS device (10) having p-channel and n-channel transistors with aluminum implanted gates (20). When making the device (10), aluminum is non-selectively implanted to form a source and drain for the n-channel transistor and to reduce the resistivity of the gates (20). The aluminum diffuses through an upper polysilicon layer (22) of the gate, thereby reducing its resistivity, but does not diffuse through a lower oxide layer (24) of the gate, thereby preventing penetration problems. Thereafter, a compensating implant (e.g., phosphorus or arsenic) is selectively implanted to overcompensate the boron previously implanted in the p-type tub.Type: GrantFiled: February 25, 2002Date of Patent: December 9, 2003Assignee: Advanced Micro Devices, Inc.Inventor: Matthew Buynoski
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Publication number: 20030224576Abstract: There is provided a method including the steps of: forming spaced gate patterns on a main surface of a semiconductor substrate; forming sidewall films on the gate patterns, respectively, at their respective sidewalls facing each other; and, with the gate patterns and the sidewall films used as a mask, implanting a dopant in the semiconductor substrate to form a doped region. The doped region and a substrate region adjacent thereto together form a diode protecting a gate electrode of a field effect transistor. The doped region as a constituent of the diode can be minimized in size to be smaller than a limit of resolution.Type: ApplicationFiled: December 4, 2002Publication date: December 4, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Yasuo Yamaguchi
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Patent number: 6653189Abstract: One aspect of the present invention relates to a method of making a flash memory cell, involving the steps of providing a substrate having a flash memory cell thereon; forming a self-aligned source mask over the substrate, the self aligned source mask having openings corresponding to source lines; implanting a source dopant of a first type in the substrate through the openings in the self-aligned source mask corresponding to source lines; removing the self-aligned source mask from the substrate; forming a MDD mask over the substrate, the MDD mask covering the source lines and having openings corresponding to drain lines; and implanting a medium dosage drain implant of a second type to form a drain region in the substrate adjacent the flash memory cell.Type: GrantFiled: October 30, 2000Date of Patent: November 25, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Sameer Haddad, Yue-song He, Timothy Thurgate, Chi Chang, Mark W. Randolph, Ngaching Wong
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Patent number: 6645820Abstract: An ESD protection circuit protects integrated circuits having multiple power supply voltage sources from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage sources. The ESD protection circuit has a string of serially connected lateral polycrystalline silicon diodes characterized by consistent turn-on threshold voltage level such that as the number of stage of the ESD protection circuit increase, the turn-on voltage threshold of the ESD protection circuit increase linearly.Type: GrantFiled: April 9, 2002Date of Patent: November 11, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Kuo Reay Peng, Jian-Hsing Lee, Shui-Hung Chen
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Patent number: 6642096Abstract: A method of manufacturing a bipolar transistor in a single-crystal silicon substrate of a first conductivity type, including a step of carbon implantation at the substrate surface followed by an anneal step, before forming, by epitaxy, the transistor base in the form of a single-crystal semiconductor multilayer including at least a lower layer, a heavily-doped median layer of the second conductivity type, and an upper layer that contacts a heavily-doped emitter of the first conductivity type.Type: GrantFiled: September 5, 2001Date of Patent: November 4, 2003Assignee: STMicroelectronics S.A.Inventors: Didier Dutartre, Alain Chantre, Michel Marty, Sébastien Jouan
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Patent number: 6620719Abstract: A method for forming ohmic contacts for semiconductor devices, in accordance with the present invention, includes forming a layer containing metal which includes dopants integrally formed therein. The layer containing metal is patterned to form components for a semiconductor device, and a semiconductor layer is deposited for contacting the layer containing metal. The semiconductor device is annealed to outdiffuse dopants from the layer containing metal into the semiconductor layer to form ohmic contacts therebetween.Type: GrantFiled: March 31, 2000Date of Patent: September 16, 2003Assignee: International Business Machines CorporationInventors: Paul Stephen Andry, Evan George Colgan, John C. Flake, Peter Fryer, William Graham, Eugene O'Sullivan
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Patent number: 6610578Abstract: A bipolar transistor of type NPN has an active region at the surface of the component, which is surrounded, as seen along the surface of the component, in the conventional way by thick field oxide areas. The active region is partly covered by an electrically isolating surface layer, preferably comprising a nitride layer. A base region in the active region is defined by a well-defined opening, which is lithographically produced, in the electrically isolating surface layer. For a bipolar lateral transistor of type PNP, which instead has emitter and collector regions surrounded by such thick field oxide areas, the emitter and collector regions can in the corresponding way be defined by a lithographically defined opening in an electrically isolating surface layer. Owing to the well defined openings the base-collector capacitance and the emitter-collector capacitance respectively can be reduced in these cases, what results in better high frequency characteristics of the transistors.Type: GrantFiled: July 13, 1998Date of Patent: August 26, 2003Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Hans Norström, Stefan Nygren, Ola Tylstedt
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Patent number: 6602747Abstract: Within both a method for fabricating a bipolar transistor device and a method for fabricating a BiCMOS device there is: (1) formed contacting a base contact region a polysilicon base contact of a second polarity; and (2) formed contacting an emitter contact region a polysilicon emitter contact of a first polarity. Within the methods, there is then implanted into the polysilicon base contact a dose of a dopant of the second polarity while masking the polysilicon emitter contact. The methods provide for enhanced performance of the bipolar transistor device and the BiCMOS device.Type: GrantFiled: June 26, 2002Date of Patent: August 5, 2003Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Fu-Chih Yang, Guan-Jie Shen, Yung-Yen Shieh
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Patent number: 6579773Abstract: In the fabrication of a transistor device, particularly a low-voltage high-frequency transistor for use in mobile telecommunications, a method for improving the transistor performance and the high-frequency characteristics of the device is described. The method includes providing a semiconductor substrate (1) with an n-doped collector layer (5) surrounded by isolation areas (4), implanting antimony ions into the collector layer such that a thin highly n-doped layer (18) is formed in the uppermost portion of the collector layer, and forming a base on top of said thin highly n-doped layer (18).Type: GrantFiled: June 25, 2001Date of Patent: June 17, 2003Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Hans Norström, Torkel Arnborg, Ted Johansson
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Patent number: 6573133Abstract: A sidewall spacer is formed in a CMOS device by depositing a layer of silicon nitride on a wafer and anisotropically etching away the silicon nitride layer with a chorine-based plasma etchant.Type: GrantFiled: May 4, 2001Date of Patent: June 3, 2003Assignee: Dalsa Semiconductor Inc.Inventors: Marc Roy, Manon Daigle, Bruno Lessard, Ginette Couture
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Patent number: 6562547Abstract: A method for producing structures in chips is realized by carrying out a sequence of structuring steps in a self-adjusting manner. By structuring a first auxiliary layer applied on a substrate, a first masking structure is formed after a first masking procedure, which first masking structure has at least one partial region projecting beyond the surface of the substrate. After this, a further structuring step is carried out, for instance, by etching, implantation or CVD, using the previously produced first masking structure as a mask. After this, the first masking structure with a view to forming a second masking structure is inverted by applying at least one second auxiliary layer onto the first masking structure. The thus formed structure is at least partially taken off and the thus denuded first auxiliary layer is selectively removed, whereupon the second masking structure is used as a mask for a further structuring step.Type: GrantFiled: December 1, 2000Date of Patent: May 13, 2003Assignee: Austria Mikro Systeme International AktiengesellschaftInventors: Jochen Kraft, Martin Schatzmayr, Hubert Enichlmair
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Patent number: 6509243Abstract: In a method for integrating a high-voltage device and a low-voltage device, a substrate includes a first isolation region separating a high-voltage device region and a low-voltage device region, a second isolation region formed in a scribe region, and a patterned insulating layer that exposes the first and second isolation regions. A patterned photoresist, formed over the substrate, exposes a portion of the patterned insulating layer in the high-voltage device region and a portion of the second isolation region in the scribe region. A doped region and a trench are respectively formed in the substrate under the exposed portion of the patterned insulating layer and in the exposed portion of the second isolation region. The patterned photoresist and the patterned insulating layer are subsequently removed. First and second gate structures are respectively formed in the high-voltage and low-voltage device regions by using the trench as an alignment mark.Type: GrantFiled: June 25, 2001Date of Patent: January 21, 2003Assignee: United Microelectronics Corp.Inventor: Yung-Chieh Fan
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Patent number: 6506655Abstract: A method of manufacturing a bipolar transistor in an N-type semiconductor substrate, including the steps of depositing a first base contact polysilicon layer and doping it; depositing a second silicon oxide layer; forming in the first and second layers an opening; annealing to form a third thin oxide layer and harden the second oxide layer; implanting a P-type dopant; depositing a fourth silicon nitride layer; depositing a fifth silicon oxide layer and etching it; anisotropically etching the fifth, fourth, and third layers; performing cleanings during which the fifth layer is reetched and takes a flared profile; depositing a sixth polysilicon layer; and implanting an N-type dopant.Type: GrantFiled: March 2, 2000Date of Patent: January 14, 2003Assignee: STMicroelectronics S.A.Inventors: Yvon Gris, Germaine Troillard
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Publication number: 20030008466Abstract: In order to provide a method of fabricating a semiconductor device improved to be capable of attaining a high refresh property, a gate electrode is formed on a semiconductor substrate through a gate oxide film. Impurity ions for forming source/drains on both sides of the gate electrode are implanted into the surface of the semiconductor substrate. Inert ions are implanted into the surface of the semiconductor substrate. The semiconductor substrate is heat-treated in a nitrogen atmosphere, for forming an SiN layer on the surface of the gate electrode. The semiconductor substrate is heat-treated in an oxidizing atmosphere, for forming an additional oxide film.Type: ApplicationFiled: May 2, 2002Publication date: January 9, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Toshihiro Inada
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Publication number: 20020197812Abstract: A method for integrating a high-voltage device and a low-voltage device. A substrate having a patterned insulating layer is provided. A first isolation region and a second isolation region are formed on the substrate exposed by the patterned insulating layer. The second isolation region is located on the substrate in the scribe region. A patterned photoresist is formed over the substrate to expose a portion of the patterned insulating layer in the high-voltage device region and a portion of the second isolation region in the scribe region. A doped region is formed in the substrate under the portion of the patterned insulating layer exposed by the patterned photoresist. A trench is formed in the second isolation region exposed by the patterned photoresist in the scribe region. The patterned photoresist and the patterned insulating layer are removed in sequence. A drive-in process is performed to transform the doped region into a grade region.Type: ApplicationFiled: June 25, 2001Publication date: December 26, 2002Applicant: Unite Microelectronics Corp.Inventor: Yung-Chieh Fan
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Patent number: 6479362Abstract: An improved gate electrode provides greater tolerances to higher temperature annealing treatments, and is useful in connection with the formation of self-aligned contacts as are needed for high density embedded DRAM applications. Consistent with one embodiment, a process for manufacturing a polycide transistor gate electrode involves forming a cap dielectric and dielectric spacer, with the electrode exhibiting a reduced diffusion transport of dopants between an underlying doped polysilicon layer and an overlying suicide layer. The reduced transport results from the presence of a thin barrier layer between the doped polysilicon layer and silicide layer, and the gate electrode process forms a thermally-oxidized thin polysilicon side-wall film against the polysilicon layer, the barrier layer, the silicide layer, and the cap dielectric layer. The polysilicon side-wall film is used for blocking substantial oxidation of the barrier film.Type: GrantFiled: February 14, 2001Date of Patent: November 12, 2002Assignee: Koninklijke Philips Electronics N.V.Inventor: James A. Cunningham
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Patent number: 6472288Abstract: Bipolar transistors of different designs, particularly designs optimized for different high frequency applications are formed on the same substrate by separate base layer formation processes for epitaxial growth including different material concentration profiles of germanium, boron and/or carbon. Epitaxial growth of individual growth layers by low temperature processes is facilitated by avoiding etching of the silicon substrate including respective collector regions through use of an etch stop that can be etched selectively to silicon. Annealing processes can be performed between growth of respective base layers and/or performed collectively after all transistors are substantially completed.Type: GrantFiled: December 8, 2000Date of Patent: October 29, 2002Assignee: International Business Machines CorporationInventors: Gregory G. Freeman, K. T. Schonenberg, Kenneth J. Stein, Seshadri Subbanna
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Publication number: 20020155674Abstract: A tetra-ethyl-ortho-silicate (TEOS) layer is first deposited on the surface of a MOS transistor followed by the deposition of a borophosposilicate glass (BPSG) layer atop the TEOS layer. Thereafter, an ion implantation process of BF2+ is performed to alter the dopant concentration in the gate conduction layer of the PMOS transistor. Both the TEOS layer and the BPSG layer suppress both free fluorine and boron ions from entering the gate during the ion implantation process of BF2+ to prevent boron penetration of the MOS transistor and stabilize the threshold voltage of the MOS transistor.Type: ApplicationFiled: April 18, 2001Publication date: October 24, 2002Inventors: Chi-King Pu, Yi-Fan Chen
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Patent number: 6461927Abstract: In the case of a semiconductor device where a base electrode 11 in a collector top heterojunction bipolar transistor is disposed so as to contact with the side face of a base layer 5 in which no ion is implanted and the surface of a high resistance extrinsic emitter area 14 in which ion is implanted, the dependence of the current gain in the collector top HBT on the collector size can be diminished.Type: GrantFiled: August 28, 2001Date of Patent: October 8, 2002Assignee: Hitachi, Ltd.Inventors: Kazuhiro Mochizuki, Tohru Oka, Isao Ohbu, Kiichi Yamashita
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Publication number: 20020132440Abstract: During the production of integrated semiconductor structures, it is often necessary to differently dope immediately adjacent regions. A method is provided for producing two adjacent regions of a predetermined area in an integrated semiconductor, whereby a first region of the two adjacent regions includes a doping with a lower target concentration than a second region. The predetermined area of a semiconductor blank is doped with a dopant until a concentration of the dopant is obtained that is at least as high as the target concentration of the second region. A protective layer is applied to the second region, and the dopant is out-diffused from the first region until a concentration of dopant is obtained that corresponds to the target concentration of the first region.Type: ApplicationFiled: January 22, 2002Publication date: September 19, 2002Inventor: Josef Bock
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Patent number: 6444551Abstract: A method of driving-in antimony into a wafer, including the following steps. A wafer is loaded into an annealing furnace/tool. The wafer having an area of implanted antimony ions. The wafer is annealed a first time at a first temperature in the presence of only a first nitrogen gas flow rate. The wafer is ramped-down from the first temperature to a second temperature in the presence of only an oxygen gas flow rate. The wafer is maintained in the presence of the of oxygen gas flow rate at the second temperature. The wafer is ramped-up from the second temperature to a third temperature in the presence of only the oxygen gas flow rate. The wafer is annealed a second time at the third temperature in the presence of only a second nitrogen gas flow rate to drive-in the antimony ions within the area of implanted antimony.Type: GrantFiled: July 23, 2001Date of Patent: September 3, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Wen-Yu Ku, Fang-Cheng Lu, Ting-Pang Li, Cheng-Chung Wang
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Patent number: 6440812Abstract: Method and apparatus for improving the high current operation of bipolar transistors while minimizing adverse affects on high frequency response are disclosed. A local implant to increase the doping of the collector at the collector to base interface is achieved by the use of an angled ion implant of collector impurities through the emitter opening. The resulting area of increased collector doping is larger than the emitter opening, which minimizes carrier injection from the emitter to the collector, but is smaller than the area of the base.Type: GrantFiled: November 8, 1999Date of Patent: August 27, 2002Assignee: Micron Technology, Inc.Inventor: Michael Violette
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Publication number: 20020105054Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.Type: ApplicationFiled: March 6, 2002Publication date: August 8, 2002Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Jun-Lin Tsai, Ruey-Hsin Liu, Jei-Feng Hwang, Kuo-Chio Liu
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Publication number: 20020102805Abstract: A method for forming shallow junction, at least includes following steps: provides a substrate; forms a dielectric layer and a conductor layer in sequence on the substrate; removes part of the conductor layer and part of the dielectric layer to form a gate on the substrate; forms a spacer on the sidewall of the gate; forms a poly-silicon-germanium layer on the bare surface of the substrate and the top of the gate; implants numerous ions into the poly-silicon-germanium layer and forms a metal layer on both the poly-silicon-germanium layer and the spacer; performs a thermal process; and removes residual the metal layer. Whereby, the sequences for ions implantation and formation of poly-silicon-germanium layer are exchangeable.Type: ApplicationFiled: January 26, 2001Publication date: August 1, 2002Inventors: Huang-Chung Cheng, Cheng-Jer Yang, Ting-Chang Chang
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Patent number: 6423605Abstract: A practical, low-cost method for forming an ultra-shallow junction in a semiconductor material is provided. The method is directed to an initial RTA process using a heat source at a selected temperature and time sufficient to eliminate lattice defects without significant diffusion of the dopants, along with subsequent exposure to electromagnetic radiation having a frequency in the range of the resonance frequency of interstitial impurity ions. The intensity of the electric field is selected to be proportional to the value of the activation barrier potential of the impurity ions. The method may be used for any dopant material.Type: GrantFiled: November 9, 2000Date of Patent: July 23, 2002Assignee: Gyrotron Technology, Inc.Inventors: Vladislav Sklyarevich, Michael Shevelev
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Patent number: 6410974Abstract: The present invention provides for a method of manufacturing a simplified high Q inductor substrate and a semiconductor device having that substrate. The method for manufacturing the simplified high Q inductor substrate preferably includes forming a base substrate over a semiconductor wafer, wherein the base substrate has a given dopant concentration and then forming an epitaxial (EPI) layer over the base substrate. The EPI layer includes epitaxially forming a first doped region in the EPI layer over the base substrate and then epitaxially forming a second doped region in the EPI layer over the first doped region. The first doped region has a dopant concentration greater than the given dopant concentration of the base substrate, and the second doped region has a dopant concentration less than the first doped region.Type: GrantFiled: March 5, 2001Date of Patent: June 25, 2002Assignee: Agere Systems Guardian Corp.Inventors: Jerome Tsu-Rong Chu, John D. LaBarre, Wen Lin, Blair Miller
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Patent number: 6399455Abstract: A method of fabricating a small bipolar transistor emitter in an integrated circuit structure is provided. The integrated circuit structure includes a trench isolation structure formed in a semiconductor substrate to define a substrate active device region. A collector region having a first conductivity type is formed in the substrate active device region beneath a surface thereof. A base region having a second conductivity type opposite the first conductivity type is formed in the substrate active device region above the collector region and extending to the surface of the substrate active device region such that the surface of the active device region forms a surface of the base region. A layer of dielectric material is formed to extend at least partially over the surface of the base region to define an edge of the layer of dielectric material that is formed over the surface of the base region.Type: GrantFiled: June 15, 2001Date of Patent: June 4, 2002Assignee: National Semiconductor CorporationInventor: Abdalla Aly Naem
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Publication number: 20020058361Abstract: In a silicon layer formed on an insulator layer, a lattice defect region is formed to be adjacent to a channel region and source/drain regions, and the lower part of the channel region functions as a high-concentration channel region. The holes of hole-electron pairs generated in the channel region are eliminated by recombination in the lattice defect region, thereby suppressing the bipolar operation resulting from the accumulation of holes and increasing the source/drain breakdown voltage. The threshold value of a parasitic transistor is increased by the high-concentration channel region so as to reduce the leakage current in the OFF state. Alternatively, the holes may be moved to the source region to disappear therein by providing, instead of the lattice defect region, a high-concentration diffusion layer constituting and operating as a pn diode between the channel and source regions.Type: ApplicationFiled: December 28, 2001Publication date: May 16, 2002Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroaki Nakaoka, Hiromasa Fujimoto, Atsushi Hori, Takashi Uehara, Takehiro Hirai
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Publication number: 20020042178Abstract: A method of manufacturing a bipolar transistor in a single-crystal silicon substrate of a first conductivity type, including a step of carbon implantation at the substrate surface followed by an anneal step, before forming, by epitaxy, the transistor base in the form of a single-crystal semiconductor multilayer including at least a lower layer, a heavily-doped median layer of the second conductivity type, and an upper layer that contacts a heavily-doped emitter of the first conductivity type.Type: ApplicationFiled: September 5, 2001Publication date: April 11, 2002Inventors: Didier Dutartre, Alain Chantre, Michel Marty, Sebastien Jouan
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Patent number: 6333222Abstract: In the method of manufacturing the DRAM mixed logic memory, first, a pattern of one gate electrode is formed, and then a pattern of another gate electrode is formed. A step of oxidizing a polycrystalline silicon residue is performed thereafter. Therefore, the polycrystalline silicon residue is prevented from being left and prevention of electric short circuit is allowed.Type: GrantFiled: September 20, 1999Date of Patent: December 25, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masashi Kitazawa, Masayoshi Shirahata, Kazunobu Ohta
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Publication number: 20010053582Abstract: This invention provides a semiconductor device having dual gate wherein impurity implanted into one gate is prevented from reaching the other gate and diffusing there. A wide gate separating region is secured between a p+ gate 22 and an n+ gate 23. This gate separating region is a non-doped polysilicone region in which the impurity such as B, P, As is not implanted. The wide gate separating region secures a wide gap between the p+ gate 22 and the n+ gate 23. Therefore, the probability that the impurity existing in one gate may reach the other gate through the gate electrode metal film 24 is extremely low. Consequently, the characteristic of the semiconductor device is maintained in an excellent condition.Type: ApplicationFiled: February 8, 2001Publication date: December 20, 2001Inventor: Hirotaka Mori
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Patent number: 6329260Abstract: An integrated circuit has an isolation structure in the form of a double diode moat. The P substrate has P+ buried layers 8601 and 8602 on opposite sides of N+ buried layer 8605. Analog devices are formed behind one diode moat, digital CMOS devices are formed behind the other moat.Type: GrantFiled: September 10, 1999Date of Patent: December 11, 2001Assignee: Intersil Americas Inc.Inventors: Glenn Alan DeJong, Akira Ito, Choong-Sun Rhee, Jeffrey Johnston, Michael D. Church, Kantilal Bacrania
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Patent number: 6316324Abstract: A method of manufacturing a semiconductor device includes the step of doping an N-type impurity via a selective region formed on a semiconductor substrate by lithography, the step of doping a P-type impurity in the semiconductor substrate subsequent to the doping step without forming a selective region by lithography, and the step of self-aligningly forming an N-diffusion layer and a P-diffusion layer by performing wet oxidation with respect to the semiconductor substrate in which the N-type impurity and the P-type impurity are doped.Type: GrantFiled: November 5, 1996Date of Patent: November 13, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Katsu Honna, Yasuhiro Dohi, Yasuko Anai, Takashi Kyuho, Kazuhiro Sato
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Patent number: 6309939Abstract: This invention discloses a method of manufacturing a semiconductor device which comprises the steps of: forming gate electrodes on a semiconductor substrate having a cell region and a peripheral region; forming spacers at both side walls of the gate electrodes; implanting impurity into the semiconductor substrate of the peripheral region; forming a growth suppression layer on gate electrodes and surface of the semiconductor substrate in the peripheral region; forming doped epitaxial layers over predetermined portions of the semiconductor substrate in the cell region so that the impurity implanted into the semiconductor substrate in the peripheral region is diffused in the semiconductor substrate to form junction regions and impurity existing in the doped epitaxial layers of the cell region is diffused into the semiconductor substrate; and removing the growth suppression layer.Type: GrantFiled: June 16, 2000Date of Patent: October 30, 2001Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Jung Ho Lee
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Patent number: 6287929Abstract: In accordance with the above first embodiment of the present invention, after a base polysilicon film has been grown, a lump anneal is carried out because of an extremely small variation to the silicon dioxide film. Subsequently, a buffered fluorine acid is used which has a large selective etching ratio of the silicon oxide film to the polysilicon film to side-etch the silicon oxide film in the horizontal direction by a predetermined width before the base impurity BF2+ is implanted and then the emitter polysilicon film is formed. For those reasons, a variation in distance between the n+-substrate and a collector is small. The base width “WB” of the base region is not varied, whereby variations in high frequency performance of the bipolar transistor are suppressed.Type: GrantFiled: August 16, 2000Date of Patent: September 11, 2001Assignee: NEC CorporationInventor: Hiroshi Kato
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Patent number: 6287930Abstract: Bipolar junction transistors utilize trench-based base electrodes and lateral base electrode extensions to facilitate the use of preferred self-alignment processing techniques. A bipolar junction transistor is provided that includes an intrinsic collector region of first conductivity type in a semiconductor substrate. A trench is also provided in the substrate. This trench extends adjacent the intrinsic collector region. A base electrode of second conductivity type is provided in the trench and a base region of second conductivity type is provided in the intrinsic collector region. This base region is self-aligned to the base electrode and forms a P-N rectifying junction with the intrinsic collector region. An emitter region of first conductivity type is also provided in the base region and forms a P-N rectifying junction therewith.Type: GrantFiled: October 25, 1999Date of Patent: September 11, 2001Assignee: Samsung Electronics Co., Ltd.Inventor: Kang-Wook Park
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Publication number: 20010013600Abstract: An improved gate electrode provides greater tolerances to higher temperature annealing treatments, and is useful in connection with the formation of self-aligned contacts as are needed for high density embedded DRAM applications. Consistent with one embodiment, a process for manufacturing a polycide transistor gate electrode involves forming a cap dielectric and dielectric spacer, with the electrode exhibiting a reduced diffusion transport of dopants between an underlying doped polysilicon layer and an overlying suicide layer. The reduced transport results from the presence of a thin barrier layer between the doped polysilicon layer and silicide layer, and the gate electrode process forms a thermally-oxidized thin polysilicon side-wall film against the polysilicon layer, the barrier layer, the silicide layer, and the cap dielectric layer. The polysilicon side-wall film is used for blocking substantial oxidation of the barrier film.Type: ApplicationFiled: February 14, 2001Publication date: August 16, 2001Applicant: Philips Semiconductors, Inc.Inventor: James A. Cunningham
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Publication number: 20010009795Abstract: The present invention provides for a method of manufacturing a simplified high Q inductor substrate and a semiconductor device having that substrate. The method for manufacturing the simplified high Q inductor substrate preferably comprising forming a base substrate over a semiconductor wafer, wherein the base substrate has a given dopant concentration and then forming an epitaxial (EPI) layer over the base substrate. The EPI layer includes epitaxially forming a first doped region in the EPI layer over the base substrate and then epitaxially forming a second doped region in the EPI layer over the first doped region. The first doped region has a dopant concentration greater than the given dopant concentration of the base substrate, and the second doped region has a dopant concentration less than the first doped region.Type: ApplicationFiled: March 5, 2001Publication date: July 26, 2001Inventors: Jerome Tsu-Rong Chu, John D. LaBarre, Wen Lin, Blair Miller
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Patent number: 6251739Abstract: The present invention relates to a collector pin and a trench in an integrated circuit intended for high speed communication, and to a manufacturing method for these items. The collector pin is achieved by creating an area which is implantation damaged or made amorphous and at least partially doped (139) by means of ion implantation from an upper silicon surface comprised in a semiconductor structure (144) down to a depth lower than the depth of the surrounding field oxide (120), and that the semiconductor structure (144) is then heat treated.Type: GrantFiled: May 22, 1998Date of Patent: June 26, 2001Assignee: Telefonaktiebolaget LM EricssonInventors: Hans Erik Norstrom, Sam-Hyo Hong, Bo Anders Lindgren, Torbjorn Larsson
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Patent number: 6228702Abstract: In a semiconductor device fabricated according to a method of the present invention, a microelectronic capacitor is provided with a double-layered tantalum oxide film serving as a capacitance insulation film. The double-layered tantalum oxide film is constructed of: a first tantalum oxide film formed at a temperature of about 510° C. under a high pressure of about 3.0 Torr in an atmosphere containing oxygen in a first film forming step; and, a second tantalum oxide film formed on the first tantalum oxide film at a temperature of about 510° C. under a low pressure of about 0.3 Torr in an atmosphere free from oxygen in a second film forming step.Type: GrantFiled: November 29, 1999Date of Patent: May 8, 2001Assignee: NEC CorporationInventor: Toshiyuki Hirota
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Patent number: 6225182Abstract: The present invention provides for a method of manufacturing a simplified high Q inductor substrate and a semiconductor device having that substrate. The method for manufacturing the simplified high Q inductor substrate preferably comprises forming a base substrate over a semiconductor wafer, wherein the base substrate has a given dopant concentration and then forming an epitaxial (EPI) layer over the base substrate. The EPI layer includes epitaxially forming a first doped region in the EPI layer over the base substrate and then epitaxially forming a second doped region in the EPI layer over the first doped region. The first doped region has a dopant concentration greater than the given dopant concentration of the base substrate, and the second doped region has a dopant concentration less than the first doped region.Type: GrantFiled: August 30, 1999Date of Patent: May 1, 2001Assignee: Agere Systems Guardian Corp.Inventors: Jerome Tsu-Rong Chu, John D. LaBarre, Wen Lin, Blair Miller
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Patent number: 6225179Abstract: A bi-MOS circuit is fabricated on first active regions assigned to the bipolar transistor and on second active regions assigned to the field effect transistors, and the field effect transistors are fabricated after said bipolar transistor, because a high-temperature heat treatment for an emitter diffusion destroys the impurity profiles of the source/drain regions of the field effect transistors, wherein a part of the field oxide layer between the second active regions is covered with an etching stopper layer before deposition of a thick silicon oxide layer in order to widely space the emitter region from the emitter electrode, even though the thick silicon oxide layer is removed from the field oxide layer between the second active regions for fabricating the field effect transistors, the etching stopper layer prevents the field oxide layer from the etchant, and the field oxide layer between the second active regions maintains the original thickness, thereby never allowing a parasitic MOS transistor to turn onType: GrantFiled: March 2, 1999Date of Patent: May 1, 2001Assignee: NEC CorporationInventor: Hiroaki Yokoyama