Abstract: The present application provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of laminated structures arranged at intervals on the substrate, the laminated structure includes a first conductive layer, an insulating layer, and a second conductive layer, and at least one of the first conductive layer and the second conductive layer is a semi-metal layer; forming a channel layer covering the laminated structures, and a dielectric layer covering the channel layer; and forming word lines (WLs) extending along a first direction, the WL includes a plurality of contact parts and a connecting part connecting adjacent contact parts, the contact part surrounds and is in contact with a side surface of the dielectric layer, and the contact part is opposite to at least a part of the insulating layer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.

Abstract: A semiconductor structure includes a semiconductor substrate, n-type source and drain stressors, and a gate stack. The semiconductor substrate has source and drain recesses therein. The n-type source and drain stressors are respectively present in the source and drain recesses. At least one of the n-type source and drain stressors has a hydrogen terminated surface. A gate stack is present on the semiconductor substrate and between the n-type source and drain stressors.

Abstract: A magnetoresistive random access memory (MRAM) structure includes a bottom electrode structure. A magnetic tunnel junction (MTJ) element is over the bottom electrode structure. The MTJ element includes an anti-ferromagnetic material layer. A ferromagnetic pinned layer is over the anti-ferromagnetic material layer. A tunneling layer is over the ferromagnetic pinned layer. A ferromagnetic free layer is over the tunneling layer. The ferromagnetic free layer has a first portion and a demagnetized second portion. The MRAM also includes a top electrode structure over the first portion.

Abstract: A method of forming a vertical transport fin field effect transistor, including, forming a bottom source/drain layer at the surface of the substrate, forming one or more channels on the bottom source/drain layer, where the channels extend away from the bottom source/drain layer, forming a gate structure on each of the one or more channels, and forming a top source/drain segment on the top surface of each of the one or more channels, wherein either each of the top source/drain segments or the bottom source/drain layer has a larger bandgap than the other of the bottom source/drain layer or each of the top source/drain segments.

Abstract: A process for fabricating a 3D memory is shown. Linear stacks, each of which includes alternately stacked gate lines and insulating layers, are formed. A charge trapping layer is formed covering the linear stacks. An amorphous semiconductor layer is formed on the charge trapping layer. An ultra-thin cap layer is formed on the amorphous semiconductor layer. The amorphous semiconductor layer is annealed to form a crystalline channel layer, wherein agglomeration of the material of the amorphous semiconductor layer is suppressed by then ultra-thin cap layer.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate comprising a groove. A buffer layer is formed on a surface of the groove. The buffer layer comprising at least one material chosen from AIN, GaN or AlxGa1-xN, where x is between zero and one. An epitaxially grown semiconductor material is disposed over the buffer layer, at least a portion of the epitaxially grown semiconductor material having a cubic crystalline phase structure. Methods of forming the semiconductor devices are also taught.

Abstract: Disclosed is a method for fabricating an array substrate, comprising: forming a pattern layer comprising a gate and a gate connection on a substrate; sequentially forming an insulation layer film and an active layer film on the substrate, and forming a pattern of a gate insulation layer having a first via hole and a pattern of an active layer through a single patterning process, wherein the first via hole is located above the gate connection; sequentially forming a transparent conductive film and a metal film on the substrate, and forming a pattern layer comprising a first electrode and a pattern layer comprising a data line, a source, a drain and a TFT channel through a single patterning process.

Abstract: A etchant composition that includes, based on a total weight of the etchant composition, about 0.5 wt % to about 20 wt % of a persulfate, about 0.5 wt % to about 0.9 wt % of an ammonium fluoride, about 1 wt % to about 10 wt % of an inorganic acid, about 0.5 wt % to about 5 wt % of a cyclic amine compound, about 0.1 wt % to about 10.0 wt % of a sulfonic acid, about 5 wt % to about 10 wt % of an organic acid or a salt thereof, and a remainder of water. The etchant composition may be configured to etch a metal layer including copper and titanium, to form a metal wire that may be included in a thin film transistor array panel of a display device.

Abstract: A group III nitride semiconductor light-emitting element having a pn junction hetero structure composed of: an n-type aluminum gallium indium nitride layer; a light-emitting layer disposed contacting the n-type aluminum gallium indium nitride layer and including a gallium indium nitride layer containing crystals having a larger lattice constant than the n-type aluminum gallium indium nitride layer; and a p-type aluminum gallium indium nitride layer provided on the light-emitting layer. Further, the relative atomic concentrations of donor impurities at either interface of the light-emitting layer and within respective layers of the light-emitting element are specified herein.

Abstract: There is provided a process for forming a contained second layer over a first layer, including the steps: forming the first layer including a fluorinated material and having a first surface energy; treating the first layer with a priming layer; exposing the priming layer patternwise with radiation having a wavelength greater than 300 nm, resulting in exposed areas and unexposed areas; developing the priming layer to effectively remove the priming layer from the unexposed areas resulting in a first layer having a patterned priming layer, wherein the patterned priming layer has a second surface energy that is higher than the first surface energy; and forming the second layer by liquid deposition on the patterned priming layer on the first layer. The priming layer includes an aromatic amine compound and a photoinitiator.

Abstract: The present disclosure discloses a method for manufacturing a TFT array substrate, comprising: depositing a gate metal layer, a gate insulating layer, a semiconductor layer and a source-drain electrode layer in this order on a base substrate, performing a first photolithograph process to form a common electrode line, a gate line, a gate electrode, a source electrode, a drain electrode and a channel defined between the source electrode and the drain electrode; depositing a passivation layer, performing a second photolithograph process to form a first via hole and a second via hole in the passivation layer; and depositing a pixel electrode layer and a data line layer in this order, perform a third photolithograph process to form a data line connected to the source electrode through the first via hole and a pixel electrode connected to the drain electrode through the second via hole.

Abstract: An organic light emissive device, which comprises: an anode; a cathode; and an organic light emissive region between the anode and the cathode, which region comprises: a layer of blue light electroluminescent organic material which emits light having first CIE co-ordinates by exciton radiative decay; and a layer of longer wavelength electroluminescent organic material which intrinsically emits light having second CIE co-ordinates by exciton radiative decay; wherein the layers of blue light and longer wavelength materials are selected so that the organic light emissive region emits white light falling within a region having a CIE ? coordinate equivalent to that emitted by a black body at 3000-9000K and CIE ? co-ordinate of said light emitted by a black body.

Abstract: A semiconductor substrate includes a first side and a second side opposite the first side. A semiconductor material extends between the first and second sides and is devoid of active device regions. The semiconductor material has a first region and a second region. The first region extends from the first side to a depth into the semiconductor material and includes chalcogen dopant atoms which provide a base doping concentration for the first region. The second region extends from the first region to the second side and is devoid of base doping. Further, a power semiconductor component is provided.

Abstract: A GaN-based semiconductor is epitaxially grown on a silicon substrate with a surface orientation of (111). The difference between the lattice constant of the GaN and the silicon (111) surface is approximately 17%, which is quite large. Therefore, the dislocation density of the grown GaN exceeds 1010 cm?2. Screw dislocation density causes the leak current of the transistor using GaN to increases. Furthermore, the mobility of the transistor is reduced. Provided is a semiconductor substrate comprising a silicon substrate and a nitride semiconductor layer that is epitaxially grown on a (150) surface of the silicon substrate.

Abstract: In one embodiment, a semiconductor component, such as a wavelength converter wafer, is described wherein the wavelength converter is bonded to an adjacent inorganic component with a cured bonding layer comprising polysilazane polymer. The wavelength converter may be a multilayer semiconductor wavelength converter or an inorganic matrix comprising embedded phosphor particles. In another embodiment, the semiconductor component is a pump LED component bonded to an adjacent component with a cured bonding layer comprising polysilazane polymer. The adjacent component may the described wavelength converter(s) or another component comprised of inorganic material(s) such as a lens or a prism. Also described are methods of making semiconductor components such as wavelength converters and LED's.

Abstract: A semiconductor light-emitting structure including a first conductive type semiconductor layer, a second conductive type semiconductor layer, a light-emitting layer, an electrode, an insulating layer, and an adhesive layer is provided. The light-emitting layer is disposed between the first conductive type semiconductor layer and the second conductive type semiconductor layer. The electrode is disposed on the first conductive type semiconductor layer. The insulating layer covers a part of the first conductive type semiconductor layer and the electrode. The adhesive layer is disposed between the electrode and the insulating layer so as to bond the electrode and the insulating layer.

Abstract: In an organic light emitting diode (OLED) display device and a method for fabricating the same, OLED pixels are patterned through a photolithography process, so a large area patterning can be performed and a fine pitch can be obtained, and an organic compound layer can be protected by forming a buffer layer of a metal oxide on an upper portion of the organic compound layer or patterning the organic compound layer by using a cathode as a mask, improving device efficiency. In addition, among red, green, and blue pixels, two pixels are patterned through a lift-off process and the other remaining one is deposited to be formed without patterning, the process can be simplified and efficiency can be increased.

Abstract: A method of fabricating a light emitting diode device comprises depositing conductive material to cover a portion of surface of a conductive and reflective layer to form a first contact pad, and surfaces between adjacent first trenches to form a second contact pad; and depositing a first passivation layer over uncovered portion of surface of the conductive and reflective layer to form a first planar passivation contact surface between the first contact pad and the second trench and depositing bonding material to cover a portion of surface of the first contact pad, a portion of the second contact pad and a portion of the first planar passivation contact to form a first light emitting diode bonding pad on the first contact pad, a second light emitting diode bonding pad on the second contact pad, and a third light emitting diode bonding pad on the first planar passivation contact.

Abstract: The present disclosure discloses a method for manufacturing a TFT array substrate, comprising: depositing a gate metal layer, a gate insulating layer, a semiconductor layer and a source-drain electrode layer in this order on a base substrate, performing a first photolithograph process to form a common electrode line, a gate line, a gate electrode, a source electrode, a drain electrode and a channel defined between the source electrode and the drain electrode; depositing a passivation layer, performing a second photolithograph process to form a first via hole and a second via hole in the passivation layer; and depositing a pixel electrode layer and a data line layer in this order, perform a third photolithograph process to form a data line connected to the source electrode through the first via hole and a pixel electrode connected to the drain electrode through the second via hole.

Abstract: Connectors and methods of coupling electronic devices and cables are provided. In one embodiment, a connector has a first coded magnet on a first surface of a first device. The first coded magnet has at least two different polarity regions on the first surface. A second coded magnet on a second surface of a second device is also provided. The second coded magnet is configured to provide identifying information regarding the device on which it is located.

Abstract: The present invention is directed to a method for fabricating a magnetic tunnel junction (MTJ) memory element. The method comprises the steps of providing a substrate having a contact dielectric layer, a bottom dielectric layer, a bottom electrode layer, an etch stop layer, an MTJ layer stack, and a top electrode layer sequentially formed thereon; etching the top electrode layer with a first mask thereon to form a top electrode; etching the MTJ layer stack with the top electrode thereon to form a patterned MTJ; encapsulating the patterned MTJ with a passivation layer; depositing a top dielectric layer on top of the passivation layer and planarizing the same layer; forming a second mask on the top dielectric layer; and etching the bottom electrode layer, the etch stop layer, the passivation layer, and the top dielectric layer with the second mask thereon to form a bottom electrode.

Abstract: An encapsulating sheet, for encapsulating an optical semiconductor element mounted on a board by a wire-bonding connection, includes an embedding layer for embedding the optical semiconductor element and a wire and a cover layer covering the embedding layer. The embedding layer and the cover layer contain a catalyst containing a transition metal and are prepared from a silicone resin composition that is cured by accelerating a reaction by the catalyst. The ratio of the concentration of the transition metal in the cover layer to that of the transition metal in the embedding layer is 1 or more. The length from an interface between the embedding layer and the cover layer to a portion of the wire that is positioned closest to the cover layer-side is 150 ?m or more.

Abstract: An array substrate comprises a substrate, a passivation layer on a surface of the substrate, a first organic film on a surface of the passivation layer and provided with a groove, a common electrode disposed on a surface of the first organic film outside the groove, and a pixel electrode disposed in the groove. A vertical projection of the common electrode on the surface of the passivation layer does not overlap with a vertical projection of the pixel electrode on the surface of the passivation layer.

Abstract: Disclosed herein is a light emitting diode having a multi-junction structure and a method of fabricating the same. In the light emitting diode, each light emitting structure has a column shape and includes two light emitting layers centered on a p-type semiconductor layer. In addition, a p-type electrode is formed on a side surface of the p-type semiconductor layer, and a p-type electrode is formed through formation and removal of a sacrificial layer. Through this process, the p-type electrode can be formed as a side electrode.

Abstract: A method of applying a conversion means to an optoelectronic semiconductor chip includes preparing the optoelectronic semiconductor chip having a main radiation face, preparing the conversion means, the conversion means being applied to a main carrier face of a carrier, arranging the conversion means such that it faces the main radiation face and has a spacing relative to the main radiation face, and releasing the conversion means from the carrier and applying the conversion means to the main radiation face by irradiation and heating of an absorber constituent of the conversion means and/or of a release layer located between the conversion means and the carrier with a pulsed laser radiation which passes through the carrier.

Abstract: A method and structure for receiving a micro device on a receiving substrate are disclosed. A micro device such as a micro LED device is punched-through a passivation layer covering a conductive layer on the receiving substrate, and the passivation layer is hardened. In an embodiment the micro LED device is punched-through a B-staged thermoset material. In an embodiment the micro LED device is punched-through a thermoplastic material.

Abstract: A display device according to an exemplary embodiment of the present invention includes a semiconductor layer; a data line disposed on the semiconductor layer, and a source electrode as well as a drain electrode disposed on the semiconductor layer and facing the source electrode. The semiconductor layer is made of an oxide semiconductor including indium, tin, and zinc. An atomic percent of indium in the oxide semiconductor is equal to or larger than about 10 at % and equal to or smaller than about 90 at %, an atomic percent of zinc in the oxide semiconductor is equal to or larger than about 5 at % and equal to or smaller than about 60 at %, and an atomic percent of tin in the oxide semiconductor is equal to or larger than about 5 at % and equal to or smaller than about 45 at %, and the data line and the drain electrode comprise copper.

Abstract: A method of fabricating LED devices includes using a laser to form trenches between the LEDs and then using a chemical solution to remove slag creating by the laser.

Abstract: Method for manufacturing a thin film transistor liquid crystal display is provided. A substrate is provided. A gate electrode, a source electrode, a drain electrode, and a passivation film are formed on the substrate in sequence. The passivation film has a contact hole to expose a part of the drain electrode. A conductive layer is formed by coating nano metal material on the passivation film and in the contract hole from which the drain electrode is exposed. A pixel electrode is formed by patterning the conductive layer.

Abstract: A method is for manufacturing a nitride semiconductor laser element including a substrate, a nitride semiconductor layer that is laminated on the substrate and that has a ridge on its surface, an insulating protective film, and an electrode that is electrically connected with the nitride semiconductor layer. The method includes forming the ridge; forming a monocrystalline first film from the side faces of the ridge to the nitride semiconductor layer on both sides of the ridge; and forming a second film containing polycrystalline or an amorphous substance over the first film thereby forming the insulating protective film.

Abstract: An OLED display device is provided. The OLED display device includes a substrate segmented into a plurality sub-pixel regions, a thin film transistor formed in each of the sub-pixel regions, an insulating layer and a planarization layer formed on the thin film transistor, a semitransparent reflective layer selectively formed in each sub-pixel region on the planarization layer, a protective layer formed on the semitransparent reflective layer, an anode electrode formed in a region corresponding to the semitransparent reflective layer on the protective layer and connected to the thin film transistor, an organic light emitting layer connected to the anode electrode, and emitting light, and a cathode electrode formed on the organic light emitting layer.

Abstract: The number of manufacturing steps is reduced to provide a semiconductor device with high productivity and low cost. A semiconductor device with low power consumption and high reliability is provided. A photolithography process for forming an island-shaped semiconductor layer is omitted, and a semiconductor device is manufactured through at least four photolithography processes: a step for forming a gate electrode (including a wiring or the like formed from the same layer), a step for forming a source electrode and a drain electrode (including a wiring or the like formed from the same layer), a step for forming a contact hole, and a step for forming a pixel electrode. In the step for forming the contact hole, a groove portion is formed, whereby formation of a parasitic transistor is prevented. The groove portion overlaps with the wiring with an insulating layer provided therebetween.

Abstract: Various embodiments of the present disclosure pertain to selective photo-enhanced wet oxidation for nitride layer regrowth on substrates. In one aspect, a method may comprise: forming a first III-nitride layer with a first low bandgap energy on a first surface of a substrate; forming a second III-nitride layer with a first high bandgap energy on the first III-nitride layer; transforming portions of the first III-nitride layer into a plurality of III-oxide stripes by photo-enhanced wet oxidation; forming a plurality of III-nitride nanowires with a second low bandgap energy on the second III-nitride layer between the III-oxide stripes; and selectively transforming at least some of the III-nitride nanowires into III-oxide nanowires by selective photo-enhanced oxidation.

Abstract: Provided are a transistor, a method of manufacturing the transistor, and an electronic device including the transistor. The transistor may include a passivation layer on a channel layer, a source, a drain, and a gate, wherein the component of the passivation layer is varied in a height direction. The passivation layer may have a multi-layer structure including a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer sequentially stacked. The channel layer may include an oxide semiconductor.

Abstract: A method for making a light emitting diode is provided. In the method, a substrate having an epitaxial growth surface is provided. A first semiconductor layer, an active layer, and a second semiconductor layer are grown on the epitaxial growth surface in series. The first semiconductor layer, the active layer, and the second semiconductor layer constitute a source layer. A metallic plasma generating layer is then formed on a surface of the source layer away from the substrate. A first optical symmetric layer is then disposed on a surface of the metallic plasma generating layer. A first electrode is applied on an exposed surface of the first semiconductor layer. A second electrode is applied to electrically connect with the second semiconductor layer.

Abstract: Provided is a method of forming a micropattern according to an aspect of the present invention. The method of forming a micropattern may include forming an organic wire or organic-inorganic hybrid wire mask pattern having a circular or elliptical cross section on a substrate, forming a material layer on an entire surface of the substrate having the organic wire or organic-inorganic hybrid wire mask pattern formed thereon, and removing the organic wire or organic-inorganic hybrid wire mask pattern from the substrate to allow only the material layer on a portion of the substrate having no organic wire or organic-inorganic hybrid wire mask pattern formed thereon to be remained.

Abstract: A mold having an open interior volume is used to define patterns. The mold has a ceiling, floor and sidewalls that define the interior volume and inhibit deposition. One end of the mold is open and an opposite end has a sidewall that acts as a seed sidewall. A first material is deposited on the seed sidewall. A second material is deposited on the deposited first material. The deposition of the first and second materials is alternated, thereby forming alternating rows of the first and second materials in the interior volume. The mold and seed layer are subsequently selectively removed. In addition, one of the first or second materials is selectively removed, thereby forming a pattern including free-standing rows of the remaining material. The free-standing rows can be utilized as structures in a final product, e.g., an integrated circuit, or can be used as hard mask structures to pattern an underlying substrate. The mold and rows of material can be formed on multiple levels.

Abstract: A method for making light emitting diode includes following steps. A substrate having an epitaxial growth surface is provided. A first semiconductor layer, an active layer, and a second semiconductor layer is epitaxially grown on the epitaxial growth surface of the substrate in that sequence. A first optical symmetric layer is formed on the second semiconductor layer. A metallic layer is applied on the first optical symmetric layer. A second optical symmetric layer is formed on the metallic layer. A first electrode is electrically connected to the first semiconductor layer. A second electrode is electrically connected to the second semiconductor layer.

Abstract: The present invention provides a pixel structure including a substrate, a first metal pattern layer, an insulating layer, a second metal pattern layer, a passivation layer, and a conductive protection layer. The substrate has at least one pixel region. The first patterned metal layer is disposed on the substrate, and has a top surface. The insulating layer is disposed on the first patterned metal layer and the substrate, and is in contact with the top surface of the first patterned metal layer. The second patterned metal layer is disposed on the insulating layer in the pixel region, and includes a source and a drain. The passivation layer is disposed on the second patterned metal layer and the insulating layer. A top surface of the source is in contact with the passivation layer, and the conductive protection layer is disposed on the drain.

Abstract: The present disclosure discloses a method for manufacturing a TFT array substrate, comprising: depositing a gate metal layer, a gate insulating layer, a semiconductor layer and a source-drain electrode layer in this order on a base substrate, performing a first photolithograph process to form a common electrode line, a gate line, a gate electrode, a source electrode, a drain electrode and a channel defined between the source electrode and the drain electrode; depositing a passivation layer, performing a second photolithograph process to form a first via hole and a second via hole in the passivation layer; and depositing a pixel electrode layer and a data line layer in this order, perform a third photolithograph process to form a data line connected to the source electrode through the first via hole and a pixel electrode connected to the drain electrode through the second via hole.

Abstract: A method of forming a p-type gallium nitride based semiconductor without activation annealing is provided, and the method can provide a gallium nitride based semiconductor doped with a p-type dopant. A GaN semiconductor region 17 containing a p-type dopant is formed on a supporting base 13 in a reactor 10. An organometallic source and ammonia are supplied to the reactor 10 to grow the GaN semiconductor layer 17 on a GaN semiconductor layer 15. The GaN semiconductor is doped with a p-type dopant. Examples of the p-type dopant include magnesium. After the GaN semiconductor regions 15 and 17 are grown, an atmosphere 19 containing at least one of monomethylamine and monoethylamine is prepared in the reactor 10. After the atmosphere 19 is prepared, a substrate temperature is decreased from the growth temperature of the GaN semiconductor region 17. When the substrate temperature is lowered to room temperature after this film formation, a p-type GaN semiconductor 17a and an epitaxial wafer E has been fabricated.

Abstract: A method for making a light emitting diode is provided. In the method, a substrate having an epitaxial growth surface is provided. A first semiconductor layer, an active layer, and a second semiconductor layer are grown on the epitaxial growth surface in sequence. The first semiconductor layer, the active layer, and the second semiconductor layer constitute a source layer. A metallic plasma generating layer is then formed on a surface of the source layer away from the substrate. A first optical symmetric layer is then disposed on a surface of the metallic plasma generating layer. a second optical symmetric layer is then disposed on a surface of the first symmetric layer away from the substrate. A first electrode is applied to electrically connect the first semiconductor layer. A second electrode is applied to electrically connect the second semiconductor layer.

Abstract: A method of manufacturing an organic electroluminescence element having on a belt-formed flexible base material, a first electrode, at least one organic functional layer, and a second electrode, includes continuously forming at least one organic functional layer by coating the same on a first electrode which is formed continuously on the flexible base material in the conveying direction thereof, further forming a second electrode on the organic functional layer, so as to make a plurality of organic electroluminescence element structures in the conveying direction, and then cutting the electroluminescence element structures into individual organic electroluminescence elements so as to manufacture organic electroluminescence elements.

Abstract: A method for making a light emitting diode is provided. In the method, a substrate having an epitaxial growth surface is provided. A buffer layer, a first semiconductor layer, an active layer, a second semiconductor layer are grown on the epitaxial growth surface in sequence. The first semiconductor layer, the active layer, and the second semiconductor layer constitute a source layer. A third optical symmetric layer, a metallic layer, a fourth optical symmetric layer, and a first optical symmetric layer are then disposed on a surface of the second semiconductor layer away from the substrate in the listed sequence. The substrate and the buffer layer are removed to expose the first semiconductor layer. A first electrode is applied on an exposed surface of the first semiconductor layer and a second electrode is applied to electrically connect with the second semiconductor layer.

Abstract: One object is to provide a method for manufacturing a display device in which shift of the threshold voltage of a thin film transistor including an oxide semiconductor layer can be suppressed even when ultraviolet light irradiation is performed in the process for manufacturing the display device. In the method for manufacturing a display device, ultraviolet light irradiation is performed at least once, a thin film transistor including an oxide semiconductor layer is used for a switching element, and heat treatment for repairing damage to the oxide semiconductor layer caused by the ultraviolet light irradiation is performed after all the steps of ultraviolet light irradiation are completed.

Abstract: The present invention provides a semiconductor light-emitting device that emits light with a specific low correlated color temperature and with a high Ra, and a semiconductor light-emitting system provided with the semiconductor light-emitting device. This object is attained by the semiconductor light-emitting device having the below-described configuration. A semiconductor light-emitting device includes a LED chip as a semiconductor light-emitting element, and a phosphor emitting light using the LED chip as an excitation source, and emits light with a correlated color temperature equal to or higher than 1600 K and lower than 2400 K. The phosphor includes at least a green phosphor and a red phosphor. In the spectrum of light emitted from the semiconductor light-emitting device, the value of the peak intensity of the light emitted by the LED chip is less than 60% of the maximum peak intensity of the light emitted by the phosphor.

Abstract: According to one embodiment, a semiconductor light emitting device includes: a semiconductor layer including a first face, a second face, a side face, and a light emitting layer; a p-side electrode provided on the second face; an n-side electrode provided on the side face; a first p-side metal layer provided on the p-side electrode; a first n-side metal layer provided on the periphery of the n-side electrode; a first insulating layer provided on a face on the second face side in the first n-side metal layer; a second p-side metal layer connected with the first p-side metal layer on the first p-side metal layer, and provided, extending from on the first p-side metal layer to on the first insulating layer; and a second n-side metal layer provided on a face on the second face side in the first n-side metal layer in a peripheral region of the semiconductor layer.

Abstract: A semiconductor wafer including an electrostatic discharge (ESD) protective device, and methods for fabricating the same. In one aspect, the method includes forming a first semiconductor device in a first semiconductor die region on the semiconductor wafer; forming a second semiconductor device in a second semiconductor die region on the semiconductor wafer; and forming a protective device in a scribe line region between (i) the first semiconductor die region and (ii) the second semiconductor die region.

Abstract: A semiconductor optical emission device comprising a layer of material containing a plurality of stress variations and adhering to a surface of a semiconductor is described. In one embodiment the semiconductor is an indirect band gap semiconductor and is silicon in one aspect, the material of the layer comprises silicon and metal oxides and is prepared by a sol-gel process including thermal annealing in one aspect. The layer urges a plurality of randomly distributed elastic deformations in the semiconductor that substantially enhances the radiative recombination interactions among free carriers in the semiconductor.