Passivating Of Surface Patents (Class 438/38)
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Patent number: 8735192Abstract: There is provided a nitride semiconductor light emitting device having a light emitting portion coated with a coating film, the light emitting portion being formed of a nitride semiconductor, the coating film in contact with the light emitting portion being formed of an oxynitride. There is also provided a method of fabricating a nitride semiconductor laser device having a cavity with a facet coated with a coating film, including the steps of: providing cleavage to form the facet of the cavity; and coating the facet of the cavity with a coating film formed of an oxynitride.Type: GrantFiled: May 23, 2008Date of Patent: May 27, 2014Assignee: Sharp Kabushiki KaishaInventors: Takeshi Kamikawa, Yoshinobu Kawaguchi
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Patent number: 8735976Abstract: A Thin Film Transistor-Liquid Crystal Display (TFT-LCD) array substrate is presented which includes a gate line, a data line, and a pixel electrode. The pixel electrode is disposed in a pixel region defined by the intersection between the gate line and the data line. In the pixel region, a partition groove for forming a pixel electrode pattern is provided at the periphery of the pixel electrode.Type: GrantFiled: February 26, 2013Date of Patent: May 27, 2014Assignee: Beijing Boe Optoelectronics Technology Co., Ltd.Inventors: Hongxi Xiao, Jae Yun Jung, Zuhong Liu, Taek Ho Hong, Jeong Hun Rhee
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Patent number: 8735189Abstract: A method of fabricating a light emitting diode device comprises providing a substrate, growing an epitaxial structure on the substrate. The epitaxial structure includes a first layer on the substrate, an active layer on the first layer and a second layer on the active layer. The method further comprises depositing a conductive and reflective layer on the epitaxial structure, forming a group of first trenches and a second trench. Each of the first and second trenches extends from surface of the conductive and reflective layer to the first layer to expose part of the first layer. The method further comprises depositing conductive material to cover a portion of the conductive and reflective layer to form a first contact pad, and cover surfaces between adjacent first trenches to form a second contact pad. The second contact pad electrically connects the first layer by filling the conductive material in the first trenches.Type: GrantFiled: May 17, 2012Date of Patent: May 27, 2014Assignee: Starlite LED IncInventor: Chang Han
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Publication number: 20140138645Abstract: An organic light emitting display device includes: a substrate; a display unit on the substrate; and an encapsulation layer on the display unit, the encapsulation layer including a plurality of inorganic layers and a plurality of organic layers, the plurality of inorganic layers and the plurality of organic layers being alternately located, and the plurality of organic layers being at a region where the plurality of inorganic layers is located. The plurality of inorganic layers covers the display unit and is sequentially on the substrate, and areas of each of the inorganic layers are increased moving in a direction away from the display unit.Type: ApplicationFiled: August 30, 2013Publication date: May 22, 2014Applicant: SAMSUNG DISPLAY CO., LTD.Inventor: Ji-Hun Ryu
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Publication number: 20140105235Abstract: Provided are a semiconductor laser and a method of manufacturing the same. The method includes: providing a substrate including a buried oxide layer; forming patterns, which includes an opening part to expose the substrate, by etching the buried oxide layer; forming a germanium single crystal layer in the opening part; and forming an optical coupler, which is adjacent to the germanium single crystal layer, on the substrate.Type: ApplicationFiled: February 25, 2013Publication date: April 17, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: In Gyoo KIM, Gyungock KIM, Sang Hoon KIM, Ki Seok JANG, JiHo JOO
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Patent number: 8686444Abstract: An organic light emitting device including a substrate on which an organic light emitting unit is formed, wherein the organic light emitting unit sequentially includes a first electrode, an organic layer, and a second electrode; and a passivation layer covering the substrate and the second electrode, and a method of manufacturing the organic light emitting device.Type: GrantFiled: June 14, 2010Date of Patent: April 1, 2014Assignee: Samsung Display Co., Ltd.Inventors: Yong-Tak Kim, Jong-Hyuk Lee, Won-Jong Kim, Joon-Gu Lee, Jin-Baek Choi
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Patent number: 8679883Abstract: Various embodiments of the present disclosure pertain to selective photo-enhanced wet oxidation for nitride layer regrowth on substrates. In one aspect, a semiconductor structure may comprise: a first substrate structure; a III-nitride structure bonded with the first substrate structure; a plurality of air gaps formed between the first substrate structure and the III-nitride structure; and a III-oxide layer formed on surfaces around the air gaps, wherein a portion of the III-nitride structure including surfaces around the air gaps is transformed into the III-oxide layer by a selective photo-enhanced wet oxidation, and the III-oxide layer is formed between an untransformed portion of the III-nitride structure and the first substrate structure.Type: GrantFiled: April 9, 2013Date of Patent: March 25, 2014Assignee: Opto Tech CorporationInventors: Lung-Han Peng, Jeng-Wei Yu, Po-Chun Yeh
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Patent number: 8679880Abstract: An electron transporting surfactant is added to a raw material solution such that the electron transporting surfactant is coordinated on the surfaces of quantum dots, and after the dispersion solvent is evaporated by vacuum drying, the immersion in a solvent containing a hole transporting surfactant prepares a quantum dot dispersed solution with a portion of the electron transporting surfactant replaced with the hole transporting surfactant. The quantum dot dispersed solution is applied onto a substrate to prepare a hole transport layer and a quantum dot layer at the same time, and thereby to achieve a thin film which has a two-layer structure.Type: GrantFiled: June 15, 2012Date of Patent: March 25, 2014Assignee: Murata Manufaaturing Co., Ltd.Inventor: Koji Murayama
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Patent number: 8679875Abstract: A high-quality light emitting device is provided which has a long-lasting light emitting element free from the problems of conventional ones because of a structure that allows less degradation, and a method of manufacturing the light emitting device is provided. After a bank is formed, an exposed anode surface is wiped using a PVA (polyvinyl alcohol)-based porous substance or the like to level the surface and remove dusts from the surface. An insulating film is formed between an interlayer insulating film on a TFT and the anode. Alternatively, plasma treatment is performed on the surface of the interlayer insulating film on the TFT for surface modification.Type: GrantFiled: June 20, 2013Date of Patent: March 25, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hirokazu Yamagata, Shunpei Yamazaki, Toru Takayama
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Patent number: 8673746Abstract: The present invention includes methods directed to improved processes for producing a monolayer of sulfur on the surface of a semiconductor. As a surface layer, it functions to passivate the surface; if annealed, it provides a doping element.Type: GrantFiled: April 13, 2011Date of Patent: March 18, 2014Assignee: Sematech, Inc.Inventors: Joel Myron Barnett, Richard James William Hill
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Patent number: 8664115Abstract: A passivation layer is formed on inlaid Cu for protection against oxidation and removal during subsequent removal of an overlying metal hardmask. Embodiments include treating an exposed upper surface of inlaid Cu with hydrofluoric acid and a copper complexing agent, such as benzene triazole, to form a passivation monolayer of a copper complex, etching to remove the metal hardmask, removing the passivation layer by heating to at least 300° C., and forming a barrier layer on the exposed upper surface of the inlaid Cu.Type: GrantFiled: June 10, 2011Date of Patent: March 4, 2014Inventors: Christin Bartsch, Susanne Leppack
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Publication number: 20140042473Abstract: A vertical light emitting diode (LED) is disclosed, which includes a conductive substrate; a conductive diamond-like carbon (DLC) layer located on the conductive substrate; a first passivation layer disposed on the conductive DLC layer and formed with a first opening; a first electrode located on the conductive DLC layer and in the first opening of the first passivation layer; a semiconductor epitaxial multilayer structure disposed on the first electrode; a second passivation layer disposed on the first passivation layer and covering the lateral surface of the semiconductor epitaxial multilayer structure, wherein a second opening is formed in the second passivation layer to expose the surface of the semiconductor epitaxial multilayer structure; and a second electrode located on the semiconductor epitaxial multilayer structure and in the second opening of the second passivation layer. A method for manufacturing the vertical LED mentioned above is also disclosed.Type: ApplicationFiled: March 15, 2013Publication date: February 13, 2014Inventor: Chien-MIn Sung
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Publication number: 20140027709Abstract: A method and structure for receiving a micro device on a receiving substrate are disclosed. A micro device such as a micro LED device is punched-through a passivation layer covering a conductive layer on the receiving substrate, and the passivation layer is hardened. In an embodiment the micro LED device is punched-through a B-staged thermoset material. In an embodiment the micro LED device is punched-through a thermoplastic material.Type: ApplicationFiled: July 30, 2012Publication date: January 30, 2014Inventors: John A. Higginson, Andreas Bibl, Hsin-Hua Hu
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Publication number: 20140027759Abstract: A display device according to an exemplary embodiment of the present invention includes a semiconductor layer; a data line disposed on the semiconductor layer, and a source electrode as well as a drain electrode disposed on the semiconductor layer and facing the source electrode. The semiconductor layer is made of an oxide semiconductor including indium, tin, and zinc. An atomic percent of indium in the oxide semiconductor is equal to or larger than about 10 at % and equal to or smaller than about 90 at %, an atomic percent of zinc in the oxide semiconductor is equal to or larger than about 5 at % and equal to or smaller than about 60 at %, and an atomic percent of tin in the oxide semiconductor is equal to or larger than about 5 at % and equal to or smaller than about 45 at %, and the data line and the drain electrode comprise copper.Type: ApplicationFiled: January 3, 2013Publication date: January 30, 2014Applicant: SAMSUNG DISPLAY CO., LTD.Inventors: Byung Du AHN, Kyoung Won LEE, Gun Hee KIM, Young Joo CHOI
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Publication number: 20130328035Abstract: A thin film transistor element includes a gate electrode, an insulating layer formed on the gate electrode, and partition walls formed on the insulating layer and defining a first aperture above the gate electrode. The thin film transistor element further includes, at a bottom portion of the first aperture, a source electrode and a drain electrode that are in alignment with each other with a gap therebetween, a liquid-philic layer, and a semiconductor layer that covers the source electrode, the drain electrode, and the liquid-philic layer as well as gaps therebetween. The liquid-philic layer has higher liquid philicity than the insulating layer, and in plan view of the bottom portion of the first aperture, a center of area of the liquid-philic layer is offset from a center of area of the bottom portion of the first aperture.Type: ApplicationFiled: August 16, 2013Publication date: December 12, 2013Applicant: PANASONIC CORPORATIONInventors: Yuko OKUMOTO, Akihito MIYAMOTO, Takaaki UKEDA
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Patent number: 8592239Abstract: There is provided a process for forming a contained second layer over a first layer, including the steps: forming the first layer having a first surface energy; treating the first layer with a priming layer; exposing the priming layer patternwise with radiation resulting in exposed areas and unexposed areas; developing the priming layer to effectively remove the priming layer from either the exposed areas or the unexposed areas resulting in a first layer having a pattern of priming layer, wherein the pattern of priming layer has a second surface energy that is higher than the first surface energy; and forming the second layer by liquid depositions on the pattern of priming layer on the first layer. There is also provided an organic electronic device made by the process.Type: GrantFiled: December 21, 2009Date of Patent: November 26, 2013Assignee: E I du Pont de Nemours and CompanyInventors: Adam Fennimore, Jonathan M. Ziebarth, Nora Sabina Radu
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Publication number: 20130256718Abstract: The subject invention relates to a light emitting device, including a first semiconductor layer having a first conductive type; a second semiconductor layer having a second conductive type, wherein the second conductive type is different from the first conductive type; and a passivation layer covering the first and the second semiconductor layers, wherein the passivation layer has a rough surface made from a roughing treatment. The subject invention further discloses a manufacturing method for such light emitting device. The structure of the light emitting device of the subject invention can eliminate unnecessary elements, reduce process time, facilitate control of light emitting shape and further improve light emitting efficiency.Type: ApplicationFiled: March 29, 2013Publication date: October 3, 2013Applicants: KUN-HSIN TECHNOLOGY INC., WINSKY TECHNOLOGY LIMITEDInventor: Kun Chuan LIN
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Patent number: 8524594Abstract: A method for manufacturing a solid-state imaging device includes: forming pixels that receive incident light in a pixel array area of a substrate; forming pad electrodes in a peripheral area located around the pixel array area of the substrate; forming a carbon-based inorganic film on an upper surface of each of the pad electrodes including a connection surface electrically connected to an external component; forming a coated film that covers upper surfaces of the carbon-based inorganic films; and forming an opening above the connection surface of each of the pad electrodes to expose the connection surface.Type: GrantFiled: September 12, 2011Date of Patent: September 3, 2013Assignee: Sony CorporationInventor: Hiroshi Horikoshi
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Patent number: 8524591Abstract: In semiconductor devices, integrity of a titanium nitride material may be increased by exposing the material to an oxygen plasma after forming a thin silicon nitride-based material. The oxygen plasma may result in an additional passivation of any minute surface portions which may not be appropriately covered by the silicon nitride-based material. Consequently, efficient cleaning recipes, such as cleaning processes based on SPM, may be performed after the additional passivation without undue material loss of the titanium nitride material. In this manner, sophisticated high-k metal gate stacks may be formed with a very thin protective liner material on the basis of efficient cleaning processes without unduly contributing to a pronounced yield loss in an early manufacturing stage.Type: GrantFiled: August 2, 2010Date of Patent: September 3, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Sven Beyer, Rick Carter, Andreas Hellmich, Berthold Reimer
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Patent number: 8518731Abstract: A manufacturing method of a thin film transistor array panel includes: simultaneously forming a gate conductor and a first electrode on a substrate, using a non-peroxide-based etchant; forming a gate insulating layer on the gate conductor and the first electrode; forming a semiconductor, a source electrode, and a drain electrode on the gate insulating layer; forming a passivation layer on the semiconductor, the source electrode, and the drain electrode; and forming a second electrode layer on the passivation layer.Type: GrantFiled: December 2, 2011Date of Patent: August 27, 2013Assignee: Samsung Display Co., Ltd.Inventors: Jeong Min Park, Dong-Won Woo, Je Hyeong Park, Sang Gab Kim, Jung-Soo Lee, Ji-Hyun Kim
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Publication number: 20130193470Abstract: An optoelectronic component includes a protective layer including a material containing hydrophobic groups. Furthermore, a method is described, by means of which an optoelectronic component can be produced, and in which a protective layer including hydrophobic groups is applied.Type: ApplicationFiled: August 10, 2011Publication date: August 1, 2013Applicant: OSRAM OPTO SEMICONDUCTORS GMBHInventors: Karl Weidner, Johann Ramchen, Axel Kaltenbacher, Walter Wegleiter, Bernd Barchmann, Gertrud Kraeuter
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Patent number: 8481353Abstract: Various embodiments of the present disclosure pertain to separating nitride films from growth substrates by selective photo-enhanced wet oxidation. In one aspect, a method may transform a portion of a III-nitride structure that bonds with a first substrate structure into a III-oxide layer by selective photo-enhanced wet oxidation. The method may further separate the first substrate structure from the III-nitride structure.Type: GrantFiled: April 14, 2011Date of Patent: July 9, 2013Assignee: Opto Tech CorporationInventors: Lung-Han Peng, Jeng-Wei Yu, Po-Chun Yeh
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Publication number: 20130141657Abstract: The present invention discloses an array substrate, a liquid crystal display device and a manufacturing method of array substrate; an array substrate comprises a plurality of thin film transistors and a first pixel electrode connected with the drain electrode of the thin film transistor, wherein the array substrate also comprises a second pixel electrode which is arranged on the bottom of the first pixel electrode and forms mutual insulation with the first pixel electrode; The present invention can increase the penetration rate of the pixel, improve the visual color cast characteristic of a panel, and reduce uneven brightness caused by variation of electrode wire width.Type: ApplicationFiled: December 4, 2011Publication date: June 6, 2013Inventor: Chenghung Chen
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Patent number: 8455282Abstract: A semiconductor light emitting diode (LED) and a manufacturing method thereof are disclosed. The method for manufacturing a semiconductor light emitting diode (LED) includes: forming a light emission structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer on a substrate with prominences and depressions; removing the substrate from the light emission structure to expose a first concavoconvex portion corresponding to the prominences and depressions; forming a protection layer on the first concavoconvex portion; removing a portion of the protection layer to expose a convex portion of the first concavoconvex portion; and forming a second concavoconvex portion on the convex portion of the first concavoconvex portion.Type: GrantFiled: June 16, 2011Date of Patent: June 4, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Ki Sung Kim, Gi Bum Kim, Tae Hun Kim, Young Chul Shin, Young Sun Kim
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Patent number: 8455372Abstract: The present invention belongs to the technical field of semiconductor materials and specifically relates to a method for cleaning and passivizing gallium arsenide (GaAs) surface autologous oxide and depositing an Al2O3 dielectric. This method includes: use a new-type of sulfur passivant to react with the autologous oxide on the GaAs surface to clean it and generate a passive sulfide film to separate the GaAs from the outside environment, thus preventing the GaAs from oxidizing again; further cleaning the residuals such as autologous oxides and sulfides on the GaAs surface through the pretreatment reaction of the reaction source trimethyl aluminum (TMA) of the Al2O3 ALD with the GaAs surface, and then deposit high-quality Al2O3 dielectric through ALD as the gate dielectric which fully separates the GaAs from the outside environment. The present invention features a simple process and good effects, and can provide preconditions for manufacturing the GaAs devices.Type: GrantFiled: June 20, 2012Date of Patent: June 4, 2013Assignee: Fudan UniversityInventors: Qingqing Sun, Runchen Fang, Wen Yang, Pengfei Wang, Wei Zhang
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Patent number: 8440518Abstract: A manufacturing method of a semiconductor element from a pattern formed body capable of attaining patterning efficiently with a high precision. The method includes a photoresist pattern formation step, a hydrophilicity imparting step and a photoresist pattern peeling step.Type: GrantFiled: March 25, 2011Date of Patent: May 14, 2013Assignee: Dai Nippon Printing Co., Ltd.Inventors: Kenichi Ogawa, Tomomi Suzuki, Masataka Kano
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Publication number: 20130112977Abstract: The present invention provides a pixel structure including a substrate, a first metal pattern layer, an insulating layer, a second metal pattern layer, a passivation layer, and a conductive protection layer. The substrate has at least one pixel region. The first patterned metal layer is disposed on the substrate, and has a top surface. The insulating layer is disposed on the first patterned metal layer and the substrate, and is in contact with the top surface of the first patterned metal layer. The second patterned metal layer is disposed on the insulating layer in the pixel region, and includes a source and a drain. The passivation layer is disposed on the second patterned metal layer and the insulating layer. A top surface of the source is in contact with the passivation layer, and the conductive protection layer is disposed on the drain.Type: ApplicationFiled: June 28, 2012Publication date: May 9, 2013Inventors: Chin-Tzu Kao, Jin-Chuan Kuo, Ya-Ju Lu
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Patent number: 8431422Abstract: A method for producing a multiplicity of optoelectronic components includes providing a semiconductor body carrier including on a first main area a multiplicity of semiconductor bodies, each provided with a contact structure and having an active layer that generates electromagnetic radiation, in a semiconductor layer sequence, and forming a planar filling structure on the first main area such that the planar filling structure at least partly covers regions of the contact structure and the semiconductor body carrier without covering the semiconductor body.Type: GrantFiled: June 18, 2009Date of Patent: April 30, 2013Assignee: OSRAM Opto Semiconductors GmbHInventor: Siegfried Herrmann
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Patent number: 8426845Abstract: An embodiment of the present invention improves the fabrication and operational characteristics of a type-II superlattice material. Layers of indium arsenide and gallium antimonide comprise the bulk of the superlattice structure. One or more layers of indium antimonide are added to unit cells of the superlattice to provide a further degree of freedom in the design for adjusting the effective bandgap energy of the superlattice. One or more layers of gallium arsenide are added to unit cells of the superlattice to counterbalance the crystal lattice strain forces introduced by the aforementioned indium antimonide layers.Type: GrantFiled: May 6, 2011Date of Patent: April 23, 2013Assignee: SVT Associates, Inc.Inventors: Yiqiao Chen, Peter Chow
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Publication number: 20130092962Abstract: A light emitting device (LED), a manufacturing method thereof, and an LED module using the same. The LED may include a first semiconductor layer, an active layer, and a second semiconductor layer formed sequentially on a light-transmitting substrate, a first electrode formed in a region exposed by removing a part of the first semiconductor layer, a second electrode formed on the second semiconductor layer, a passivation layer formed on the first electrode and the second electrode to expose a region of the first electrode and a region of the second electrode, a first bump formed in a first region including the first electrode exposed through the passivation layer, and extended to another region of the second electrode on which the passivation layer is formed, and a second bump formed in a second region including the second electrode exposed through the passivation layer.Type: ApplicationFiled: October 18, 2012Publication date: April 18, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ho Sun Paek, Hak Hwan Kim, Ill Heung Choi, Kyung Mi Moon
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Patent number: 8420421Abstract: A method for fabricating a GaN-based thin film transistor includes: forming a semiconductor epitaxial layer on a substrate, the semiconductor epitaxial layer having a n-type GaN-based semiconductor material; forming an insulating layer on the semiconductor epitaxial layer; forming an ion implanting mask on the insulating layer, the ion implanting mask having an opening to partially expose the insulating layer; ion-implanting a p-type impurity through the opening and the insulating layer to form a p-doped region in the n-type GaN-based semiconductor material, followed by removing the insulating layer and the ion implanting mask; forming a dielectric layer on the semiconductor epitaxial layer; partially removing the dielectric layer; forming source and drain electrodes; and forming a gate electrode.Type: GrantFiled: May 27, 2011Date of Patent: April 16, 2013Assignee: National Chiao Tung UniversityInventors: Yi Chang, Chia-Hua Chang, Yueh-Chin Lin
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Patent number: 8409892Abstract: Various embodiments of the present disclosure pertain to selective photo-enhanced wet oxidation for nitride layer regrowth on substrates. In one aspect, a method may comprise: forming a first III-nitride layer with a first low bandgap energy on a first surface of a substrate; forming a second III-nitride layer with a first high bandgap energy on the first III-nitride layer; transforming portions of the first III-nitride layer into a plurality of III-oxide stripes by photo-enhanced wet oxidation; forming a plurality of III-nitride nanowires with a second low bandgap energy on the second III-nitride layer between the III-oxide stripes; and selectively transforming at least some of the III-nitride nanowires into III-oxide nanowires by selective photo-enhanced oxidation.Type: GrantFiled: April 14, 2011Date of Patent: April 2, 2013Assignee: Opto Tech CorporationInventors: Lung-Han Peng, Jeng-Wei Yu, Po-Chun Yeh
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Patent number: 8410487Abstract: A manufacturing method and a structure of a light-emitting diode (LED) chip are disclosed. The method includes the steps of: providing a conductive block; providing an epitaxial block; bonding; removing an epitaxial substrate; making independent LEDs; forming a dielectric layer; and making electrical connection. A first LED, a second LED, and a third LED are formed on the conductive block, wherein the first and second LEDs are electrically connected in series, and the second and third LEDs are electrically connected in parallel. Thus, a basic unit with a flexible design of series- and parallel-connected LEDs can be formed to increase the variety and application of LED chip-based designs.Type: GrantFiled: December 15, 2011Date of Patent: April 2, 2013Assignee: Helio Optoelectronics CorporationInventors: Wei-Tai Cheng, Ming-Hung Chen, Ching-Jen Pan
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Patent number: 8404507Abstract: A TFT-LCD array substrate and a manufacturing method thereof. The array substrate comprises a gate line, a data line, and a pixel electrode, and the pixel electrode is disposed in a pixel region defined by the intersection between the gate line and the data line. In the pixel region, a partition groove for forming a pixel electrode pattern is provided at the periphery of the pixel electrode. This structure is helpful to form a pixel electrode pattern by a lift-off process, which significantly reduces the production cost and improves the production yield.Type: GrantFiled: June 24, 2009Date of Patent: March 26, 2013Assignee: Beijing Boe Optoelectronics Technology Co., Ltd.Inventors: Hongxi Xiao, Jae Yun Jung, Zuhong Liu, Taek Ho Hong, Jeong Hun Rhee
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Publication number: 20130051421Abstract: A semiconductor laser device formed on a semiconductor substrate, the device comprising: a passivation layer arranged on an upper surface of the device structure for resisting moisture ingress, wherein the passivation layer comprises an inner layer deposited on the upper surface of the device by atomic layer deposition and an outer layer deposited on the inner layer, and comprising a material that is inert in the presence of water.Type: ApplicationFiled: August 23, 2012Publication date: February 28, 2013Inventors: Silke Traut, Stephanie Saintenoy
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Patent number: 8367441Abstract: Example embodiments herein relate to a nitride semiconductor light emitting device including a coat film formed at a light emitting portion and including an aluminum nitride crystal or an aluminum oxynitride crystal, and a method of manufacturing the nitride semiconductor light emitting device. Also provided is a nitride semiconductor transistor device including a nitride semiconductor layer and a gate insulating film which is in contact with the nitride semiconductor layer and includes an aluminum nitride crystal or an aluminum oxynitride crystal.Type: GrantFiled: September 23, 2011Date of Patent: February 5, 2013Assignee: Sharp Kabushiki KaishaInventors: Takeshi Kamikawa, Yoshinobu Kawaguchi
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Publication number: 20130026474Abstract: A storage capacitor architecture for pixel structure and manufacturing method thereof are described. The storage capacitor architecture includes a substrate, a first electrode, an insulating layer and a second electrode. The first electrode has a first concave and convex structure. The insulating layer is disposed on the first concave and convex structure of the first electrode. The second electrode is disposed on the insulating layer and has a second concave and convex structure. The first concave and convex structure and the second concave and convex structure form an interdigitated space and the insulating layer is disposed in the interdigitated space to solve the problem of decreased aperture ratio of the LCD panel.Type: ApplicationFiled: September 5, 2011Publication date: January 31, 2013Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO. ltdInventor: Chihtsung Kang
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Patent number: 8354288Abstract: An etchant includes about 0.1 percent by weight to about 30 percent by weight of ammonium persulfate (NH4)2S2O8, about 0.1 percent by weight to about 10 percent by weight of an inorganic acid, about 0.1 percent by weight to about 10 percent by weight of an acetate salt, about 0.01 percent by weight to about 5 percent by weight of a fluorine-containing compound, about 0.01 percent by weight to about 5 percent by weight of a sulfonic acid compound, about 0.01 percent by weight to about 2 percent by weight of an azole compound, and a remainder of water. Accordingly, the etchant may have high stability to maintain etching ability. Thus, manufacturing margins may be improved so that manufacturing costs may be reduced.Type: GrantFiled: August 3, 2012Date of Patent: January 15, 2013Assignee: Samsung Display Co., Ltd.Inventors: Bong-Kyun Kim, Jong-Hyun Choung, Byeong-Jin Lee, Sun-Young Hong, Hong-Sick Park, Shi-Yul Kim, Ki-Beom Lee, Sam-Young Cho, Sang-Woo Kim, Hyun-Cheol Shin, Won-Guk Seo
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Patent number: 8329562Abstract: Various embodiments of the present invention include a semiconductor device and a fabrication method therefor, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefor, in which downsizing and cost reduction can be realized.Type: GrantFiled: December 10, 2010Date of Patent: December 11, 2012Assignee: Spansion LLCInventors: Masanori Onodera, Kouichi Meguro, Junji Tanaka
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Patent number: 8318522Abstract: Surface passivation techniques for chamber-split processing are described. A method includes forming a first Group III-V material layer above a substrate, the first Group III-V material layer having a top surface. A passivation layer is deposited on the top surface of the Group III-V material layer. The passivation layer is removed. Subsequently, a second Group III-V material layer is formed above the first Group III-V material layer.Type: GrantFiled: December 13, 2010Date of Patent: November 27, 2012Assignee: Applied Materials, Inc.Inventor: Jie Su
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Publication number: 20120264246Abstract: Various embodiments of the present disclosure pertain to selective photo-enhanced wet oxidation for nitride layer regrowth on substrates. In one aspect, a method may comprise: forming a first III-nitride layer with a first low bandgap energy on a first surface of a substrate; forming a second III-nitride layer with a first high bandgap energy on the first III-nitride layer; transforming portions of the first III-nitride layer into a plurality of III-oxide stripes by photo-enhanced wet oxidation; forming a plurality of III-nitride nanowires with a second low bandgap energy on the second III-nitride layer between the III-oxide stripes; and selectively transforming at least some of the III-nitride nanowires into III-oxide nanowires by selective photo-enhanced oxidation.Type: ApplicationFiled: April 14, 2011Publication date: October 18, 2012Applicant: OPTO TECH CORPORATIONInventors: Lung-Han Peng, Jeng-Wei Yu, Po-Chun Yeh
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Patent number: 8247245Abstract: A pixel structure is disclosed. The pixel structure includes a substrate, a first data line having at least one end formed on the substrate, a first insulation layer overlying the first data line and exposing a part of the end of the first data line, a shielding electrode disposed on the first insulation layer and overlapped with the first data line, a second data line formed on the first insulation layer and electrically connected to the exposed end of the first data line, a second insulation layer overlying the shielding electrode and the second data line, and a pixel electrode formed on the second insulation layer and overlapped with the shielding electrode. The invention also provides a method for fabricating the pixel structure.Type: GrantFiled: March 14, 2011Date of Patent: August 21, 2012Assignee: AU Optronics Corp.Inventors: Hsiang-Lin Lin, Liu-Chung Lee, Kuo-Yu Huang
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Patent number: 8222064Abstract: A method of fabricating a compound semiconductor vertical LED is provided. A first growth substrate capable of supporting compound semiconductor epitaxial growth thereon is provided. One or more epitaxial layers of compound semiconductor material such as GaN or InGaN is formed on the first growth substrate to create a portion of a vertical light emitting diode. Plural trenches are formed in the compound semiconductor material. Passivating material is deposited in one or more trenches. A hard material is at least partially deposited in the trenches and optionally on portions of the compound semiconductor material. The hard material has a hardness greater than the hardness of the compound semiconductor. A metal layer is deposited over the compound semiconductor material followed by metal planarization. A new host substrate is bonded to the metal layer and the first growth substrate is removed. Dicing is used to form individual LED devices.Type: GrantFiled: July 27, 2011Date of Patent: July 17, 2012Assignee: Hong Kong Applied Science and Technology Research Institute Company LimitedInventors: Limin Lin, Xiangfeng Shao
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Patent number: 8222063Abstract: One embodiment of the present invention provides a method for fabricating light-emitting diodes (LEDs). The method includes fabricating an InGaAlN-based multilayer LED structure on a conductive substrate. The method further includes etching grooves of a predetermined pattern through the active region of the multilayer LED structure. The grooves separate a light-emitting region from non-light-emitting regions. In addition, the method includes depositing electrode material on the light-emitting and non-light-emitting regions, thereby creating an electrode. Furthermore, the method includes depositing a passivation layer covering the light-emitting and non-light-emitting regions. Moreover, the method includes removing the passivation layer on the electrode to allow the non-light-emitting regions which are covered with the electrode material and the passivation layer to be higher than the light-emitting region and the electrode, thereby protecting the light-emitting region from contact with test equipment.Type: GrantFiled: March 26, 2008Date of Patent: July 17, 2012Assignee: Lattice Power (Jiangxi) CorporationInventors: Li Wang, Fengyi Jiang
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Patent number: 8218919Abstract: A MEMS-based display device is described, wherein an array of interferometric modulators are configured to reflect light through a transparent substrate. The transparent substrate is sealed to a backplate and the backplate may contain electronic circuitry fabricated on the backplane. The electronic circuitry is placed in electrical communication with the array of interferometric modulators and is configured to control the state of the array of interferometric modulators.Type: GrantFiled: January 3, 2012Date of Patent: July 10, 2012Assignee: QUALCOMM MEMS Technologies, Inc.Inventor: Karen Tyger
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Patent number: 8212268Abstract: An epitaxial wafer, a light-emitting element, a method of fabricating the epitaxial wafer and a method of fabricating the light-emitting element, which have a high output and a low forward voltage, and can be fabricated without increasing fabricating cost, are provided.Type: GrantFiled: January 25, 2010Date of Patent: July 3, 2012Assignee: Hitachi Cable, Ltd.Inventor: Taichiroo Konno
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Publication number: 20120153343Abstract: A light emitting device includes a p-type semiconductor layer, an n-type semiconductor layer, and an active region between the n-type semiconductor layer and the p-type semiconductor layer. A non-transparent feature, such as a wire bond pad, is on the p-type semiconductor layer or on the n-type semiconductor layer opposite the p-type semiconductor layer, and a reduced conductivity region is in the p-type semiconductor layer or the n-type semiconductor layer and is aligned with the non-transparent feature. The reduced conductivity region may extend from a surface of the p-type semiconductor layer opposite the n-type semiconductor layer towards the active region and/or from a surface of the n-type semiconductor layer opposite the p-type semiconductor layer towards the active region.Type: ApplicationFiled: February 27, 2012Publication date: June 21, 2012Inventors: David Todd Emerson, Kevin Haberern, Michael John Bergmann, David B. Slater, JR., Matthew Donofrio, John Edmond
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Patent number: 8198638Abstract: A light emitting device structure, wherein the emitter layer structure comprises one or more device wells defined by thick field oxide regions, and a method of fabrication thereof are provided. Preferably, by defining device well regions after depositing the emitter layer structure, emitter layer structures with reduced topography may be provided, facilitating processing and improving layer to layer uniformity. The method is particularly applicable to multilayer emitter layer structures, e.g. comprising a layer stack of active layer/drift layer pairs. Preferably, active layers comprise a rare earth oxide, or rare earth doped dielectric such as silicon dioxide, silicon nitride, or silicon oxynitride, and respective drift layers comprise a suitable dielectric, preferably silicon dioxide, of an appropriate thickness to control excitation energy. Pixellated light emitting structures, or large area, high brightness emitter layer structures, e.g.Type: GrantFiled: July 14, 2010Date of Patent: June 12, 2012Assignee: Group IV Semiconductor Inc.Inventors: Thomas MacElwee, Alasdair Rankin
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Publication number: 20120119184Abstract: A vertical light emitting diode (VLED) die includes a p-type confinement layer, an active layer on the p-type confinement layer configured to emit light, and an n-type confinement structure having at least one etch stop layer configured to protect the active layer. A method for fabricating a vertical light emitting diode (VLED) die includes the steps of: providing a carrier substrate; forming an n-type confinement structure on the carrier substrate having at least one etch stop layer; forming an active layer on the n-type confinement structure; forming a p-type confinement layer on the active layer; and removing the carrier substrate.Type: ApplicationFiled: November 12, 2010Publication date: May 17, 2012Inventors: Kung-Hsieh Hsu, Yao-Kuo Wang, Wen-Huang Liu, Chuong Anh Tran
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Patent number: 8173456Abstract: A method of manufacturing a light emitting diode element is provided. A first patterned semi-conductor layer, a patterned light emitting layer, and a second patterned semi-conductor layer are sequentially formed on an epitaxy substrate so as to form a plurality of epitaxy structures, wherein the first patterned semi-conductor layer has a thinner portion in a non-epitaxy area outside the epitaxy structures. A passivation layer covering the epitaxy structures and the thinner portion is formed. The passivation layer covering on the thinner portion is partially removed to form a patterned passivation layer. A patterned reflector is formed directly on each of the epitaxy structures. The epitaxy structures are bonded to a carrier substrate. A lift-off process is performed to separate the epitaxy structures from the epitaxy substrate. An electrode is formed on each of the epitaxy structures far from the patterned reflector.Type: GrantFiled: December 29, 2009Date of Patent: May 8, 2012Assignee: Industrial Technology Research InstituteInventors: Jenq-Dar Tsay, Suh-Fang Lin, Yu-Hsiang Chang, Yih-Der Guo, Sheng-Huei Kuo, Wei-Hung Kuo, Hsun-Chih Liu