Passivating Of Surface Patents (Class 438/38)
  • Patent number: 8137999
    Abstract: A method for fabricating a LED includes: providing a metal substrate; etching the metal substrate to form a first terminal, a second terminal, and a gap between the first terminal and the second terminal, wherein the first terminal has at least one first etching concave and the second terminal has at least one second etching concave; placing at least one LED chip in the at least one first etching concave, wherein the at least one LED chip has a first electrode and a second electrode; electrically connecting the first electrode with the first terminal, and electrically connecting the second electrode with the second terminal; and then covering the at least one LED chip with synthetic polymer, wherein the synthetic polymer is filled into the at least one first etching concave, the at least one second etching concave and the gap to connect the first terminal with the second terminal.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: March 20, 2012
    Assignee: Harvatek Corporation
    Inventors: Bily Wang, Jonnie Chuang, Hui-Yen Huang
  • Patent number: 8120010
    Abstract: A quantum dot electroluminescent device that includes a substrate, a quantum dot light-emitting layer disposed on the substrate, a first electrode which injects charge carriers into the quantum dot light-emitting layer, a second electrode which injects charge carriers, which have an opposite charge than the charge carriers injected by the first electrode, into the quantum dot light-emitting layer, a hole transport layer disposed between the first electrode and the quantum dot light-emitting layer, and an electron transport layer disposed between the second electrode and the quantum dot light-emitting layer, wherein the quantum dot light-emitting layer has a first surface in contact with the hole transport layer and a second surface in contact with an electron transport layer, and wherein the first surface has an organic ligand distribution that is different from an organic ligand distribution of the second surface.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: February 21, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung Sang Cho, Byoung Lyong Choi, Eun Kyung Lee
  • Patent number: 8093080
    Abstract: The device includes an optical waveguide on a base. The waveguide is configured to guide a light signal through a light-transmitting medium. A light sensor is also positioned on the base. The light sensor including a ridge extending from slab regions. The slab regions are positioned on opposing sides of the ridge. A light-absorbing medium is positioned to receive at least a portion of the light signal from the light-transmitting medium included in the waveguide. The light-absorbing medium is included in the ridge and also in the slab regions. The light-absorbing medium includes doped regions positioned such that an application of a reverse bias across the doped regions forms an electrical field in the light-absorbing medium included in the ridge.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: January 10, 2012
    Assignee: Kotusa, Inc.
    Inventors: Shirong Liao, Dawei Zheng, Cheng-Chih Kung, Mehdi Asghari
  • Patent number: 8090229
    Abstract: A MEMS-based display device is described, wherein an array of interferometric modulators are configured to reflect light through a transparent substrate. The transparent substrate is sealed to a backplate and the backplate may contain electronic circuitry fabricated on the backplane. The electronic circuitry is placed in electrical communication with the array of interferometric modulators and is configured to control the state of the array of interferometric modulators.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: January 3, 2012
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventor: Karen Tyger
  • Publication number: 20110318858
    Abstract: A method for fabricating a light emitting diode chip is provided. Firstly, a semiconductor device layer is formed on a substrate. Afterwards, a current spreading layer is formed on a portion of the semiconductor device layer. Then, a current blocking layer and a passivation layer are formed on a portion of the semiconductor device layer not covered by the current spreading layer. Finally, a first electrode is formed on the current blocking layer and the current spreading layer. Moreover, a second electrode is formed on the semiconductor device layer.
    Type: Application
    Filed: August 30, 2011
    Publication date: December 29, 2011
    Applicant: LEXTAR ELECTRONICS CORP.
    Inventors: Kuo-Lung Fang, Chien-Sen Weng, Chih-Wei Chao
  • Publication number: 20110304684
    Abstract: A surface emitting laser device includes a substrate and plural semiconductor layers laminated on the substrate, the plural semiconductor layers including a first semiconductor multi-layer film including aluminum (Al), an active layer, and a second semiconductor multi-layer film, a light emitting section having a mesa structure being formed on the first semiconductor multi-layer film. When viewed in a direction orthogonal to a surface of the substrate, an outer shape of the first semiconductor multi-layer film is a macroscopically smooth shape without an angular corner, and a side surface of the first semiconductor multi-layer film is coated with a passivation film and a protection film.
    Type: Application
    Filed: June 8, 2011
    Publication date: December 15, 2011
    Applicant: RICOH COMPANY, LTD.
    Inventors: Masayuki NUMATA, Shunichi Sato
  • Patent number: 8071408
    Abstract: A method includes steps of: sequentially growing a first semiconductor layer of a first conductivity type, an active layer, and a second semiconductor layer of a second conductivity type on a growth substrate to form a layered structure; separating the substrate from the layered structure to expose the first layer; performing wet etching on an exposed surface to form defect depressions; forming an insulating layer on the exposed surface; polishing the insulating layer and the first layer to flatten the surface of the first layer; and performing wet etching on the surface of the first layer to form protrusions deriving from a crystal structure.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: December 6, 2011
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Satoshi Tanaka, Yusuke Yokobayashi
  • Publication number: 20110291139
    Abstract: An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optical device disposed on the first surface; a conducting pad disposed on the first surface; a first alignment mark formed on the first surface; and a light shielding layer disposed on the second surface and having a second alignment mark, wherein the second alignment mark corresponds to the first alignment mark.
    Type: Application
    Filed: May 24, 2011
    Publication date: December 1, 2011
    Inventors: Hsin-Chih CHIU, Chia-Ming Cheng, Chuan-Jin SHIU, Bai-Yao LOU
  • Patent number: 8067255
    Abstract: Provided are a nitride semiconductor light emitting device including a coat film formed at a light emitting portion and including an aluminum nitride crystal or an aluminum oxynitride crystal, and a method of manufacturing the nitride semiconductor light emitting device. Also provided is a nitride semiconductor transistor device including a nitride semiconductor layer and a gate insulating film which is in contact with the nitride semiconductor layer and includes an aluminium nitride crystal or an aluminum oxynitride crystal.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: November 29, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takeshi Kamikawa, Yoshinobu Kawaguchi
  • Patent number: 8062931
    Abstract: In the preferred embodiments, a method to reduce gate leakage and dispersion of group III-nitride field effect devices covered with a thin in-situ SiN layer is provided. This can be obtained by introducing a second passivation layer on top of the in-situ SiN-layer, in combination with cleaning of the in-situ SiN before gate deposition and before deposition of the second passivation layer.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: November 22, 2011
    Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&D
    Inventors: Anne Lorenz, Joff Derluyn, Joachim John
  • Patent number: 8057374
    Abstract: An ergonomic tool lifting machine and method particularly useful for manipulating a machine tool or another heavy object. In one embodiment of the invention, the machine tool is a large milling cutter. The ergonomic tool lifting machine generally includes an articulating arm attached at a fixed end to a vertical lift mechanism, and at a free end to a grasping device or tool holder adapted for gripping and retaining an object of interest. When the object is a milling cutter, the ergonomic tool lifting machine may be used to transfer the cutter between a stored position and an installed position in a milling machine. Consequently, the tool holder of this embodiment is preferably able to rotate between a pick-up/drop-off position and an installation/removal position associated with the cutter. In general, the ergonomic tool lift machine allows heavy loads to be accurately moved with very little effort required on the part of an operator.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: November 15, 2011
    Assignee: Honda Motor Co., Ltd.
    Inventor: Freedus McDermitt, Jr.
  • Patent number: 8054395
    Abstract: Disclosed is a method of fabricating a liquid crystal display (LCD) device in which a photosensitive film is selectively patterned using a half-tone mask, and then a portion of a passivation layer at a pixel area is selectively removed to secure an penetration path of a stripper. Additionally, a crack is generated on a conductive film formed on a photosensitive film pattern through a predetermined heat treatment to facilitate a lift-off process. Thus, the number of masks can be reduced to simplify the fabrication process of the LCD device and reduce fabrication costs.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: November 8, 2011
    Assignee: LG Display Co., Ltd.
    Inventors: Kyoung-Nam Lim, Byoung-Ho Lim, Hwan Kim
  • Publication number: 20110253972
    Abstract: A method for fabricating a semiconductor light-emitting device based on a strain adjustable multilayer semiconductor film is disclosed. The method includes epitaxially growing a multilayer semiconductor film on a growth substrate, wherein the multilayer semiconductor film comprises a first doped semiconductor layer, a second doped semiconductor layer, and a multi-quantum-wells (MQW) active layer; forming an ohmic-contact metal layer on the first doped semiconductor layer; depositing a metal substrate on top of the ohmic-contact metal layer, wherein the density and/or material composition of the metal substrate is adjustable along the vertical direction, thereby causing the strain in the multilayer semiconductor film to be adjustable; etching off the growth substrate; and forming an ohmic-electrode coupled to the second doped semiconductor layer.
    Type: Application
    Filed: August 19, 2008
    Publication date: October 20, 2011
    Applicant: LATTICE POWER (JIANGXI) CORPORATION
    Inventors: Chuanbing Xiong, Fengyi Jiang, Wenqing Fang, Li Wang, Guping Wang
  • Patent number: 8030650
    Abstract: A pixel structure comprises at least two scan and data lines. The scan and data lines substantially intersects one another to form at least one region therein. The pixel structure further comprises at least one thin film transistor, at least one passivation layer, at least one defect detection pattern, and at least one pixel electrode. The pixel electrode is disposed on the passivation layer and electrically connected to the thin film transistor via an opening of the passivation layer. The defect detection pattern is disposed in the region to detect whether any residue remains therebelow.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: October 4, 2011
    Assignee: AU Optronics Corp.
    Inventors: Yu-Hsin Lin, Chung-Chih Cheng
  • Patent number: 8013327
    Abstract: A thin-film transistor includes an insulating substrate, a source electrode, and a drain electrode, disposed over the top of the insulating substrate, a semiconductor layer electrically continuous with the source electrode, and the drain electrode, respectively, a gate dielectric film formed over the top of at least the semiconductor layer; and a gate electrode disposed over the top of the gate dielectric film so as to overlap the semiconductor layer. Further, a first bank insulator is formed so as to overlie the source electrode, a second bank insulator is formed so as to overlie the drain electrode, and the semiconductor layer, the gate dielectric film, and the gate electrode are embedded in a region between the first bank insulator, and the second bank insulator.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: September 6, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Kawasaki, Masaaki Fujimori, Takeo Shiba, Shuji Imazeki, Tadashi Arai
  • Patent number: 8008101
    Abstract: The present invention relates to a gallium nitride (GaN) compound semiconductor light emitting element (LED) and a method of manufacturing the same. The present invention provides a vertical GaN LED capable of improving the characteristics of a horizontal LED by means of a metallic protective film layer and a metallic support layer. According to the present invention, a thick metallic protective film layer with a thickness of at least 10 microns is formed on the lateral and/or bottom sides of the vertical GaN LED to protect the element against external impact and to easily separate the chip. Further, a metallic substrate is used instead of a sapphire substrate to efficiently release the generated heat to the outside when the element is operated, so that the LED can be suitable for a high-power application and an element having improved optical output characteristics can also be manufactured. A metallic support layer is formed to protect the element from being distorted or damaged due to impact.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: August 30, 2011
    Assignees: Seoul Opto Device Co., Ltd., Postech Foundation
    Inventor: Jong-Lam Lee
  • Patent number: 8003987
    Abstract: In order to suppress the effect due to electrons (holes) generated by incident light that cannot be prevented from entering only by means of light shielding, rather than the drain region 34 of a transistor, with respect to a majority carrier, a region 36 whose voltage is set to a value lower than the reference value of product of the voltage of a drain region and Q (unit electric charge) is provided, or a potential barrier is provided around the drain region. In such a configuration, by controlling the voltage of the periphery of the drain region 34 connected to a reflection electrode 30 to be in a floating state, photo carriers generated in the semiconductor substrate are caused to be hardly guided in the drain region 34.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: August 23, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takeshi Ichikawa
  • Patent number: 8003418
    Abstract: Provided is a method for producing a Group III nitride-based compound semiconductor light-emitting device, wherein a contact electrode is formed on an N-polar surface of an n-type layer through annealing at 350° C. or lower. In the case where, in a Group III nitride-based compound semiconductor device produced by the laser lift-off process, a contact electrode is formed, through annealing at 350° C. or lower, on a micro embossment surface (i.e., a processed N-polar surface) of an n-type layer from vanadium, chromium, tungsten, nickel, platinum, niobium, or iron, when a pseudo-silicon-heavily-doped layer is formed on the micro embossment surface (i.e., N-polar surface) of the n-type layer through treatment with a plasma of a silicon-containing compound gas, and treatment with a fluoride-ion-containing chemical is not carried out, ohmic contact is obtained, and low resistance is attained.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: August 23, 2011
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Toshiya Umemura, Ryohei Inazawa, Koichi Goshonoo, Tomoharu Shiraki
  • Publication number: 20110195539
    Abstract: A method for manufacturing a light emitting device according to an embodiment of the present invention includes preparing a growth substrate; selectively forming a projection pattern on the growth substrate; forming a first conductive type semiconductor layer on the growth substrate and the projection pattern; forming an active layer on the first conductive type semiconductor layer; forming a second conductive type semiconductor layer on the active layer; and executing an isolation etching for selectively removing the first conductive type semiconductor layer, the active layer, and the second conductive type semiconductor layer including the projection pattern.
    Type: Application
    Filed: November 17, 2010
    Publication date: August 11, 2011
    Inventors: Dae Sung Kang, Sang Hoon Han
  • Patent number: 7989275
    Abstract: A light-blocking layer is formed using a first resist mask, and a base film is formed over the light-blocking layer. A first conductive film, a first insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are sequentially formed over the base film, and first etching is performed on the second conductive film, the impurity semiconductor film, the semiconductor film, and the first insulating film using a second resist mask over the second conductive film. Then, second etching in which side-etching is performed is performed on part of the first conductive film to form a gate electrode layer, and source and drain electrode layers, source and drain region layers, and a semiconductor layer are formed using a third resist mask. The first resist mask and the second resist mask are formed using the same photomask. Thus, a thin film transistor is manufactured.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: August 2, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Takafumi Mizoguchi
  • Patent number: 7989244
    Abstract: Provided is a method of manufacturing a nitride-based semiconductor light-emitting device having increased efficiency and increased output properties. The method may include forming a sacrificial layer having a wet etching property on a substrate, forming a protective layer on the sacrificial layer, protecting the sacrificial layer in a reaction gas atmosphere for crystal growth, and facilitating epitaxial growth of a semiconductor layer to be formed on the protective layer, forming a semiconductor device including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on the protective layer, and removing the substrate from the semiconductor device by wet etching the sacrificial layer.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: August 2, 2011
    Assignee: Samsung LED Co., Ltd.
    Inventors: Kyoung-kook Kim, Kwang-ki Choi, June-o Song, Suk-ho Yoon, Kwang-hyeon Baik, Hyun-soo Kim
  • Patent number: 7989243
    Abstract: A pixel structure fabricating method is provided. A gate is formed on a substrate. A gate insulation layer covering the gate is formed on the substrate. A channel layer, a source, and a drain are simultaneously formed on the gate insulation layer above the gate. The gate, channel layer, source, and drain form a thin film transistor (TFT). A passivation layer is formed on the TFT and the gate insulation layer. A black matrix is formed on the passivation layer. The black matrix has a contact opening above the drain and a color filter containing opening. A color filer layer is formed within the color filter containing opening through inkjet printing. A dielectric layer is formed on the black matrix and the color filter layer. The dielectric layer and the passivation layer are patterned to expose the drain. A pixel electrode electrically connected to the drain is formed.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: August 2, 2011
    Assignee: Au Optronics Corporation
    Inventors: Ta-Wen Liao, Chen-Pang Tung, Chia-Ming Chang, Zong-Long Jhang, Che-Yung Lai, Chun-Yi Chiang, Chou-Huan Yu, Hsiang-Chih Hsiao, Han-Tang Chou, Jun-Kai Chang
  • Publication number: 20110159623
    Abstract: A method for fabricating a light emitting diode chip is provided. In the method, a half-tone mask process, a gray-tone mask process or a multi-tone mask process is applied and combined with a lift-off process to further reduce process steps of the light emitting diode chip. In the present invention, some components may also be simultaneously formed by an identical process to reduce the process steps of the light emitting diode chip. Consequently, the fabricating method of the light emitting diode provided in the present invention reduces the cost and time for the fabrication of the light emitting diode.
    Type: Application
    Filed: March 11, 2011
    Publication date: June 30, 2011
    Applicant: LEXTAR ELECTRONICS CORP.
    Inventors: Kuo-Lung Fang, Chien-Sen Weng, Chih-Wei Chao
  • Publication number: 20110147704
    Abstract: A light-emitting device and method for the fabrication thereof. The device includes a substrate, a first doped semiconductor layer situated above the substrate, a second doped semiconductor layer situated above the first doped semiconductor layer, and a multi-quantum-well (MQW) situated between the first and the second doped semiconductor layer. The device also includes a first electrode coupled to the first doped semiconductor layer and a second electrode coupled to the second doped semiconductor layer. The device further includes a first passivation layer which substantially covers the sidewalls of the first and second doped semiconductor layers, the MQW active layer, and the part of the horizontal surface of the second doped semiconductor layer which is not covered by the second electrode. The first passivation layer is formed through an oxidation technique. The device further includes a second passivation layer overlaying the first passivation layer.
    Type: Application
    Filed: August 19, 2008
    Publication date: June 23, 2011
    Applicant: LATTICE POWER (JIANGXI) CORPORATION
    Inventors: Fengyi Jiang, Junlin Liu, Li Wang
  • Publication number: 20110143471
    Abstract: Surface passivation techniques for chamber-split processing are described. A method includes forming a first Group III-V material layer above a substrate, the first Group III-V material layer having a top surface. A passivation layer is deposited on the top surface of the Group III-V material layer. The passivation layer is removed. Subsequently, a second Group III-V material layer is formed above the first Group III-V material layer.
    Type: Application
    Filed: December 13, 2010
    Publication date: June 16, 2011
    Inventor: Jie Su
  • Patent number: 7960191
    Abstract: The present invention provides a composite laser element that solves the problems encountered with a conventional laser medium composed of an Nd:YAG single crystal or polycrystal, and exhibits excellent performance as a laser medium. The invention relates to a laser element in which two or more crystal materials are joined, wherein (1) at least one of the crystal materials is a transparent crystal material capable of laser oscillation, including a laser active element in a matrix crystal, and (2) the transparent crystal material capable of laser oscillation and/or a second crystal body joined thereto is a polycrystal.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: June 14, 2011
    Inventor: Akio Ikesue
  • Publication number: 20110133159
    Abstract: A semiconductor light-emitting device includes a substrate, a first doped semiconductor layer, a second doped semiconductor layer situated above the first doped semiconductor layer, and a multi-quantum-well (MQW) active layer situated between the first and the second doped layers. The device also includes a first electrode coupled to the first doped semiconductor layer, wherein part of the first doped semiconductor layer is passivated, and wherein the passivated portion of the first doped semiconductor layer substantially insulates the first electrode from the edges of the first doped semiconductor layer, thereby reducing surface recombination. The device further includes a second electrode coupled to the second doped semiconductor layer and a passivation layer which substantially covers the sidewalls of the first and second doped semiconductor layers, the MQW active layer, and part of the horizontal surface of the second doped semiconductor layer which is not covered by the second electrode.
    Type: Application
    Filed: August 19, 2008
    Publication date: June 9, 2011
    Applicant: LATTICE POWER (JIANGXI) CORPORATION
    Inventors: Fengyi Jiang, Yingwen Tang, Chunlan Mo, Li Wang
  • Publication number: 20110127518
    Abstract: Provided are a transistor, a method of manufacturing the transistor, and an electronic device including the transistor. The transistor may include a passivation layer on a channel layer, a source, a drain, and a gate, wherein the component of the passivation layer is varied in a height direction. The passivation layer may have a multi-layer structure including a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer sequentially stacked. The channel layer may include an oxide semiconductor.
    Type: Application
    Filed: July 28, 2010
    Publication date: June 2, 2011
    Inventors: Ji-sim Jung, Chang-seung Lee, Jae-cheol Lee, Sang-yoon Lee, Jang-yeon Kwon, Kwang-hee Lee, Kyoung-seok Son
  • Publication number: 20110121270
    Abstract: An organic light emitting device including a substrate on which an organic light emitting unit is formed, wherein the organic light emitting unit sequentially includes a first electrode, an organic layer, and a second electrode; and a passivation layer covering the substrate and the second electrode, and a method of manufacturing the organic light emitting device.
    Type: Application
    Filed: June 14, 2010
    Publication date: May 26, 2011
    Applicant: SAMSUNG MOBILE DISPLAY CO., LTD.
    Inventors: Yong-Tak KIM, Jong-Hyuk LEE, Won-Jong KIM, Joon-Gu LEE, Jin-Baek CHOI
  • Patent number: 7947518
    Abstract: This invention discloses that photolithography can be made compatible with the production of electronic devices containing sensitive materials, if the sensitive materials are over-coated with an ultra-thin layer of non-reactive materials (e.g. inorganic oxides) before undergoing photolithographic patterning. This protecting layer isolates the sensitive materials from solvents and etching reactants used in photolithographic patterning, and does not need to be removed from the sensitive materials after patterning is completed. This invention enables photolithography to be applied to the production of electronic devices containing sensitive materials, facilitating the development of commercially viable production processes for these devices.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: May 24, 2011
    Assignee: National Taiwan University
    Inventors: Feng-Yu Tsai, Syue-Jhao Jhuo
  • Publication number: 20110108861
    Abstract: A method is provided for anisotropically etching semiconductor materials such as II-VI and III-V semiconductors. The method involves repeated cycles of plasma sputter etching of semiconductor material with a non-reactive gas through an etch mask, followed by passivation of the side walls by plasma polymerization using a polymer former. Using this procedure small pixels in down-converted light-emitting diode devices can be fabricated.
    Type: Application
    Filed: November 5, 2010
    Publication date: May 12, 2011
    Inventors: Terry L. SMITH, Jun-Ying Zhang
  • Patent number: 7939353
    Abstract: A method of forming an integrated circuit includes forming a fluorine-passivated surface of a substrate. A device quality silicon oxide layer is formed by causing the fluorine-passivated surface to interact with an oxygen-containing gas. Hydroxyl groups are substantially formed on a surface of the device quality silicon oxide layer. A high dielectric constant (high-k) gate dielectric layer is formed on the surface of the device quality silicon oxide layer.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: May 10, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jeff J. Xu
  • Patent number: 7935544
    Abstract: The present invention provides a method of manufacturing an organic light-emitting device which is applicable to a large-screen display device. The method includes the steps of: forming, over a drive substrate, an element region including a drive transistor, and an organic electroluminescence element in which, an anode, an organic layer and a cathode are stacked in this order; and after the formation of the element region, repairing a short circuit area while setting at least the element region in an atmosphere in which an oxygen concentration is 0.1% or higher and less than 1% and a dew point is ?50 degrees or less, and applying a voltage across the anode and the cathode.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: May 3, 2011
    Assignee: Sony Corporation
    Inventors: Kazunari Takagi, Takashi Hirano
  • Patent number: 7927900
    Abstract: Disclosed is a method of manufacturing a thin film transistor, in which a semiconductor layer and a gate insulating film may be formed through ink jet printing using a single bank, thereby simplifying the manufacturing process and decreasing the manufacturing cost, leading to more economical thin film transistors. The thin film transistor manufactured using the method of example embodiments may be used as a switching element for sensors, memory devices, optical devices, and active matrix flat panel displays.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: April 19, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ick Hwan Ko, In Seo Kee, Young Gu Lee, Hong Shik Shim
  • Patent number: 7915622
    Abstract: A high fill factor textured light emitting diode structure comprises: a first textured cladding and contact layer (2) comprising a doped III-V or II-VI group compound semiconductor or alloys of such semiconductors deposited by epitaxial lateral overgrowth (ELOG) onto a patterned substrate (1); a textured undoped or doped active layer (3) comprising a III-V or II-VI group semiconductor or alloys of such semiconductors and where radiative recombination of electrons aid holes occurs or intersubband transition occurs; and a second textured cladding and contact layer (4) comprising a doped III-V or II-VI group semiconductor or alloys of such semiconductors.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: March 29, 2011
    Assignee: Nanogan Limited
    Inventor: Wang Nang Wang
  • Publication number: 20110049540
    Abstract: One embodiment of the present invention provides a method for fabricating light-emitting diodes (LEDs). The method includes fabricating an InGaAlN-based multilayer LED structure on a conductive substrate. The method further includes etching grooves of a predetermined pattern through the active region of the multilayer LED structure. The grooves separate a light-emitting region from non-light-emitting regions. In addition, the method includes depositing electrode material on the light-emitting and non-light-emitting regions, thereby creating an electrode. Furthermore, the method includes depositing a passivation layer covering the light-emitting and non-light-emitting regions. Moreover, the method includes removing the passivation layer on the electrode to allow the non-light-emitting regions which are covered with the electrode material and the passivation layer to be higher than the light-emitting region and the electrode, thereby protecting the light-emitting region from contact with test equipment.
    Type: Application
    Filed: March 26, 2008
    Publication date: March 3, 2011
    Applicant: LATTICE POWER (JIANGXI) CORPORATION
    Inventors: Li Wang, Fengyi Jiang
  • Patent number: 7892866
    Abstract: The invention provides an end-face-processing jig that allows the formation of a reflectance control film on an end face of a semiconductor laser body while preventing possible degradation due to catastrophic optical damage (COD) of a semiconductor laser, and a method of manufacturing a semiconductor laser employing such an end-face-processing jig. A window part of the end-face-processing jig is made of at least one of an oxide and a nitride, and semiconductor laser bars are fixed by the end-face-processing jig so that their end faces are exposed through a window of the window part. In this condition, a reflectance control film is formed on the end faces of the semiconductor laser bars for the manufacture of a semiconductor laser. This prevents a metal from being taken in the reflectance control film, thus preventing the absorption of light caused by a metal taken in the reflectance control film.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: February 22, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yasuyuki Nakagawa
  • Patent number: 7888686
    Abstract: A light emitting device includes an active layer structure, which has one or more active layers with luminescent centers, e.g. a wide bandgap material with semiconductor nano-particles, deposited on a substrate. For the practical extraction of light from the active layer structure, a transparent electrode is disposed over the active layer structure and a base electrode is placed under the substrate. Transition layers, having a higher conductivity than a top layer of the active layer structure, are formed at contact regions between the upper transparent electrode and the active layer structure, and between the active layer structure and the substrate. Accordingly the high field regions associated with the active layer structure are moved back and away from contact regions, thereby reducing the electric field necessary to generate a desired current to flow between the transparent electrode, the active layer structure and the substrate, and reducing associated deleterious effects of larger electric fields.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: February 15, 2011
    Assignee: Group IV Semiconductor Inc.
    Inventors: George Chik, Thomas MacElwee, Iain Calder, E. Steven Hill
  • Publication number: 20110033965
    Abstract: A vertical nitride-based semiconductor LED comprises a structure support layer; a p-electrode formed on the structure support layer; a p-type nitride semiconductor layer formed on the p-electrode; an active layer formed on the p-type nitride semiconductor layer; an n-type nitride semiconductor layer formed on the active layer; an n-electrode formed on a portion of the n-type nitride semiconductor layer; and a buffer layer formed on a region of the n-type nitride semiconductor layer on which the n-electrode is not formed, the buffer layer having irregularities formed thereon. The surface of the n-type nitride semiconductor layer coming in contact with the n-electrode is flat.
    Type: Application
    Filed: October 21, 2010
    Publication date: February 10, 2011
    Applicant: SAMSUNG LED CO., LTD.
    Inventors: Sang Ho YOON, Su Yeol LEE, Doo Go BAIK, Seok Beom CHOI, Tae Sung JANG, Jong Gun WOO
  • Patent number: 7884466
    Abstract: According to the present invention, a recess portion is formed in a package substrate which is formed of a multilayer organic substrate having a multilayer wiring, and an LSI chip is accommodated within the recess portion. Wiring traces are formed on the upper surface of a resin which seals the LSI chip connected to the multilayer wiring. The wiring traces are connected to terminal wiring traces connected to the multilayer wiring on the front face of the package substrate and to front-face bump electrodes for external connection on the upper surface of the resin. On the back face side of the package substrate, back-face bump electrodes for external connection are formed and connected to the multilayer wiring.
    Type: Grant
    Filed: April 9, 2007
    Date of Patent: February 8, 2011
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Masamichi Ishihara, Fumihiko Ooka, Yoshihiko Ino
  • Patent number: 7879636
    Abstract: A method of forming a p-type gallium nitride based semiconductor without activation annealing is provided, and the method can provide a gallium nitride based semiconductor doped with a p-type dopant. A GaN semiconductor region 17 containing a p-type dopant is formed on a supporting base 13 in a reactor 10. An organometallic source and ammonia are supplied to the reactor 10 to grow the GaN semiconductor layer 17 on a GaN semiconductor layer 15. The GaN semiconductor is doped with a p-type dopant. Examples of the p-type dopant include magnesium. After the GaN semiconductor regions 15 and 17 are grown, an atmosphere 19 containing at least one of monomethylamine and monoethylamine is prepared in the reactor 10. After the atmosphere 19 is prepared, a substrate temperature is decreased from the growth temperature of the GaN semiconductor region 17. When the substrate temperature is lowered to room temperature after this film formation, a p-type GaN semiconductor 17a and an epitaxial wafer E has been fabricated.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: February 1, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masaki Ueno, Yusuke Yoshizumi, Takao Nakamura
  • Publication number: 20110008922
    Abstract: A light emitting device includes a p-type semiconductor layer, an n-type semiconductor layer, and an active region between the n-type semiconductor layer and the p-type semiconductor layer. A non-transparent feature, such as a wire bond pad, is on the p-type semiconductor layer or on the n-type semiconductor layer opposite the p-type semiconductor layer, and a reduced conductivity region is in the p-type semiconductor layer or the n-type semiconductor layer and is aligned with the non-transparent feature. The reduced conductivity region may extend from a surface of the p-type semiconductor layer opposite the n-type semiconductor layer towards the active region and/or from a surface of the n-type semiconductor layer opposite the p-type semiconductor layer towards the active region.
    Type: Application
    Filed: September 10, 2010
    Publication date: January 13, 2011
    Inventors: David Todd Emerson, Kevin Haberern, Michael John Bergmann, David B. Slater, JR., Matthew Donofrio, John Edmond
  • Patent number: 7867810
    Abstract: A method for manufacturing a solid-state image capturing apparatus including a pixel array constituted of a plurality of pixels, is provided, where each of the plurality of pixels includes a photoelectric conversion section, the method comprising the steps of: forming an impurity diffusion area in a surface area of a semiconductor substrate; and forming a plurality of different impurity diffusion areas in the surface area of the semiconductor substrate, other than the impurity diffusion area constituting the photoelectric conversion section.
    Type: Grant
    Filed: April 10, 2009
    Date of Patent: January 11, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Tetsuya Hatai
  • Publication number: 20110001120
    Abstract: A light-emitting device includes a substrate, a first doped semiconductor layer situated above the substrate, a second doped semiconductor layer situated above the first doped layer, and a multi-quantum-well (MQW) active layer situated between the first and the second doped layers. The device also includes a first electrode coupled to the first doped layer and a first passivation layer situated between the first electrode and the first doped layer in areas other than an ohmic-contact area. The first passivation layer substantially insulates the first electrode from edges of the first doped layer, thereby reducing surface recombination. The device further includes a second electrode coupled to the second doped layer and a second passivation layer which substantially covers the sidewalls of the first and second doped layers, the MQW active layer, and the horizontal surface of the second doped layer.
    Type: Application
    Filed: March 25, 2008
    Publication date: January 6, 2011
    Applicant: LATTICE POWER (JIANGXI) CORPORATION
    Inventors: Fengyi Jiang, Junlin Liu, Li Wang
  • Patent number: 7842596
    Abstract: A thin silicon solar cell having a back dielectric passivation and rear contact with local back surface field is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness from 50 to 500 micrometers. A barrier layer and a dielectric layer are applied at least to the back surface of the silicon wafer to protect the silicon wafer from deformation when the rear contact is formed. At least one opening is made to the dielectric layer. An aluminum contact that provides a back surface field is formed in the opening and on the dielectric layer. The aluminum contact may be applied by screen printing an aluminum paste having from one to 12 atomic percent silicon and then applying a heat treatment at 750 degrees Celsius.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: November 30, 2010
    Assignee: Georgia Tech Research Corporation
    Inventors: Ajeet Rohatgi, Vichai Meemongkolkiat
  • Publication number: 20100291722
    Abstract: An etchant includes about 0.1 percent by weight to about 30 percent by weight of ammonium persulfate (NH4)2S2O8, about 0.1 percent by weight to about 10 percent by weight of an inorganic acid, about 0.1 percent by weight to about 10 percent by weight of an acetate salt, about 0.01 percent by weight to about 5 percent by weight of a fluorine-containing compound, about 0.01 percent by weight to about 5 percent by weight of a sulfonic acid compound, about 0.01 percent by weight to about 2 percent by weight of an azole compound, and a remainder of water. Accordingly, the etchant may have high stability to maintain etching ability. Thus, manufacturing margins may be improved so that manufacturing costs may be reduced.
    Type: Application
    Filed: May 11, 2010
    Publication date: November 18, 2010
    Inventors: Bong-Kyun Kim, Jong-Hyun Choung, Byeong-Jin Lee, Sun-Young Hong, Hong-Sick Park, Shi-Yul Kim, Ki-Beom Lee, Sam-Young Cho, Sang-Woo Kim, Hyun-Cheol Shin, Won-Guk Seo
  • Patent number: 7825399
    Abstract: An optical device comprising: a first active stack of layers comprising an optical cavity, at least one quantum dot located in said cavity; an upper contact provided above said optical cavity; a lower contact provided below said cavity, wherein an abrupt material interface defines the whole lateral boundary of said cavity and said cavity is patterned such that it provides two dimensional lateral confinement of photon modes, said upper an lower contacts being arranged such that current can flow vertically across the cavity between the two contacts.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: November 2, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Patrick Un Siong See, Andrew James Shields
  • Patent number: 7803649
    Abstract: An angular rate sensor 100 comprises a first structure 110 which includes a fixed portion 111 having an opening 114, a displacing portion 112 placed in the opening 114, and a connecting portion 113 adapted to connect the fixed portion 111 and the displacing portions 112; a second structure 130 which includes a weighting portion 132 joined to the displacing portion 112, and a pedestal portion 131 arranged to surround the weighting portions 132 and joined to the fixed portion 111, and is laminated in place on the first structure 110. A first body 140 formed by laminating a first metal layer 142 and a first insulating layer 141 thereon is joined to the fixed portion 111 such that the first insulating layer 141 faces the fixed portion 111. A second substrate 150 formed by laminating a second metal layer 152 and a second insulating layer 151 thereon is joined to the pedestal portion 131 such that the second insulating layer 151 faces the pedestal portion 131.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: September 28, 2010
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Katsumi Hashimoto, Jiro Takei
  • Patent number: 7795059
    Abstract: A semiconductor light-emitting element has a laminated section which has an active layer made of a semiconductor, and first and second clad layers each being disposed to sandwich the active layer and made of a semiconductor, a pair of first high-reflection layers each being disposed to sandwich the active layer in a first direction orthogonal to the laminated direction of the laminated section, and a low-reflection layer and a second high-reflection layer each being disposed to sandwich the active layer in a second direction orthogonal to the laminated direction and crossing to the first direction.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: September 14, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Saito, Shinya Nunoue
  • Patent number: 7790483
    Abstract: To provide a manufacturing method of a thin film transistor and a display device with fewer masks than a conventional method. A thin film transistor is manufactured by including the steps of: forming a first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film to be stacked; forming a resist mask including three regions with different thicknesses; performing first etching to form a thin-film stack body; performing second etching in which side-etching is performed on the thin-film stack body to form a gate electrode layer; and recessing the resist mask to form a semiconductor layer and a source and drain electrode layer. A resist mask including three regions with different thicknesses can be formed using a four-tone photomask, for example.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: September 7, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Ryu Komatsu