Passivating Of Surface Patents (Class 438/38)
  • Patent number: 7456042
    Abstract: Many inventions are disclosed. Some aspects are directed to MEMS, and/or methods for use with and/or for fabricating MEMS, that supply, store, and/or trap charge on a mechanical structure disposed in a chamber. Various structures may be disposed in the chamber and employed in supplying, storing and/or trapping charge on the mechanical structure. In some aspects, a breakable link, a thermionic electron source and/or a movable mechanical structure are employed. The breakable link may comprise a fuse. In one embodiment, the movable mechanical structure is driven to resonate. In some aspects, the electrical charge enables a transducer to convert vibrational energy to electrical energy, which may be used to power circuit(s), device(s) and/or other purpose(s). In some aspects, the electrical charge is employed in changing the resonant frequency of a mechanical structure and/or generating an electrostatic force, which may be repulsive.
    Type: Grant
    Filed: June 4, 2006
    Date of Patent: November 25, 2008
    Assignee: Robert Bosch GmbH
    Inventors: Brian H. Stark, Markus Lutz, Aaron Partridge
  • Publication number: 20080267239
    Abstract: Disclosed is an example method to reduce waveguide scattering loss. The method includes forming a waveguide having a sidewall, the waveguide including a group III-V compound semiconductor material, and growing a native oxide on the waveguide to form an index of refraction contrast at the sidewall, the native oxide grown in a controlled Oxygen-enriched water vapor environment to reduce a roughness of the sidewall.
    Type: Application
    Filed: April 18, 2008
    Publication date: October 30, 2008
    Inventors: Douglas Hall, Di Liang
  • Publication number: 20080246089
    Abstract: Disclosed is a method of manufacturing a thin film transistor, in which a semiconductor layer and a gate insulating film may be formed through ink jet printing using a single bank, thereby simplifying the manufacturing process and decreasing the manufacturing cost, leading to more economical thin film transistors. The thin film transistor manufactured using the method of example embodiments may be used as a switching element for sensors, memory devices, optical devices, and active matrix flat panel displays.
    Type: Application
    Filed: April 4, 2008
    Publication date: October 9, 2008
    Inventors: Ick Hwan Ko, In Seo Kee, Young Gu Lee, Hong Shik Shim
  • Publication number: 20080220550
    Abstract: The object of the present invention is to provide a method of producing an n-type group-13 nitride semiconductor which enables resistance of the n-type group-13 nitride semiconductor to be changed, as well as, a method of producing a laser using the above method to produce a current confinement structure. There is provided a method of producing an n-type group-13 nitride semiconductor, including: preparing an n-type group-13 nitride semiconductor; and irradiating the n-type group-13 nitride semiconductor with light having a wavelength of 350 nm or more to 370 nm or less so as not to change a crystal structure of the n-type group-13 nitride semiconductor before and after the light irradiation, thereby increasing resistance of the n-type group-13 nitride semiconductor.
    Type: Application
    Filed: March 3, 2008
    Publication date: September 11, 2008
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Yoshinori Tomida
  • Publication number: 20080210942
    Abstract: An array substrate for a liquid crystal display device includes a gate line on a substrate; a gate insulating layer on the gate line; a data line crossing the gate line; a gate electrode connected to the gate line; an active layer on the gate insulating layer and overlapping the gate electrode; first and second ohmic contact layers on the active layer, the first and second ohmic contact layers spaced apart from each other by a first distance; first and second barrier patterns spaced apart from each other by the first distance and on the first and second ohmic contact layers, respectively. The active layer is exposed through the first and second barrier patterns; source and drain electrodes spaced apart from each other by a second distance greater than the first distance and on the first and second barrier patterns, respectively.
    Type: Application
    Filed: December 26, 2007
    Publication date: September 4, 2008
    Inventor: Joon-Young Yang
  • Patent number: 7407896
    Abstract: A fabrication method and materials produce high quality aperiodic photonic structures. Light emission can be activated by thermal annealing post growth treatments when thin film layers of SiO2 and SiNx or Si-rich oxide are used. From these aperiodic structures, that can be obtained in different vertical and planar device geometries, the presence of aperiodic order in a photonic device provides strong group velocity reduction (slow photons), enhanced light-matter interaction, light emission enhancement, gain enhancement, and/or nonlinear optical properties enhancement.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: August 5, 2008
    Assignee: Massachusetts Institute of Technology
    Inventors: Luca Dal Negro, Jae Hyung Yi, Jurgen Michel, Yasha Yi, Victor T. Nguyen, Lionel C. Kimerling
  • Patent number: 7399657
    Abstract: Ball grid array packages for semiconductor die include a thermally conductive container and a substrate that substantially enclose a semiconductor die. The die is positioned with respect to the container by thermally conductive supports formed in the container or attached to the container. The die contacts the supports so that the die and the container form a cavity that is at least partially filled with a thermally conductive material such as a conductive epoxy to promote thermal conduction between the die and the container. The die electrically connects to the substrate with bond wires that extend through an aperture in the substrate and attach to bond pads provided on the substrate. The aperture is typically filled with a protective layer of resin, epoxy, or other material that also encapsulates the bond wires.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: July 15, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Todd O. Bolken, Chad A. Cobbley
  • Publication number: 20080164466
    Abstract: The present invention relates to a sol-gel deposition/heat treatment process, which consistently produces polycrystalline direct bandgap semiconductor, e.g. ZnO, thin films exhibiting a photo luminescent (PL) spectrum at room temperature that is dominated by a single peak, e.g. in the ultraviolet part of the spectrum, in which the PL intensity of the bandgap emission is more than approximately 40 times greater than any deep-level defect emission peak or band. The present invention incorporates such direct bandgap semiconductor, e.g. ZnO, polycrystalline thin films produced by the method of the present invention into electro-luminescent devices that exhibit similarly high ratios of bandgap/deep-level defect emission intensity.
    Type: Application
    Filed: January 9, 2008
    Publication date: July 10, 2008
    Inventors: Brian Rioux, Jean-Paul Noel
  • Publication number: 20080111138
    Abstract: A pixel structure is disclosed. The pixel structure includes a substrate, a first data line having at least one end formed on the substrate, a first insulation layer overlying the first data line and exposing a part of the end of the first data line, a shielding electrode disposed on the first insulation layer and overlapped with the first data line, a second data line formed on the first insulation layer and electrically connected to the exposed end of the first data line, a second insulation layer overlying the shielding electrode and the second data line, and a pixel electrode formed on the second insulation layer and overlapped with the shielding electrode. The invention also provides a method for fabricating the pixel structure.
    Type: Application
    Filed: March 28, 2007
    Publication date: May 15, 2008
    Applicant: AU OPTRONICS CORP.
    Inventors: Hsiang-Lin Lin, Liu-Chung Lee, Kuo-Yu Huang
  • Publication number: 20080111126
    Abstract: An organic light emitting display includes: a substrate, a buffer layer arranged on the substrate, a semiconductor layer arranged on the buffer layer, a gate insulating layer arranged on the semiconductor layer, a gate electrode arranged on the gate insulating layer, an inter-layer dielectric layer arranged on the gate electrode, a source/drain electrode arranged on the inter-layer dielectric layer, an insulating layer arranged on the source/drain electrode, an non-transmissive layer arranged on the insulating layer; and an organic light emitting diode arranged on the insulating layer.
    Type: Application
    Filed: April 13, 2007
    Publication date: May 15, 2008
    Inventors: Jongyun Kim, Byoungdeog Choi
  • Patent number: 7361278
    Abstract: A process for producing a mass transfer device is provided which enables packing of a packing material uniformly in a flow channel, and transfers a specified substance by flowing a fluid containing the specified substance through a flow channel on a substrate. A mass transfer device produced by the process is also provided. The process for producing a mass transfer device comprises steps of preparing a substrate, forming a flow channel on the surface of the substrate, applying a liquid drop composed of a packing material and a liquid medium, and packing the packing material in the flow channel by removing the liquid medium.
    Type: Grant
    Filed: January 7, 2005
    Date of Patent: April 22, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takeo Yamazaki, Naoto Mihashi, Takeshi Imamura, Satoko Omizu
  • Publication number: 20080054296
    Abstract: Provided is a nitride-based semiconductor light emitting device having increased efficiency and power characteristics and method of manufacturing the same. The method may include forming a sacrificial layer on a substrate, forming a passivation layer on the sacrificial layer, forming a plurality of masking dots of a metal nitride on the passivation layer, laterally epitaxially growing a nitride-based semiconductor layer on the passivation layer using the masking dots as masks, forming a semiconductor device on the nitride-based semiconductor layer, and wet etching the sacrificial layer to separate and/or remove the substrate from the semiconductor device.
    Type: Application
    Filed: June 8, 2007
    Publication date: March 6, 2008
    Inventors: Suk-ho Yoon, Sung-ho Jin, Kyoung-kook Kim, Jeong-wook Lee
  • Patent number: 7338826
    Abstract: This invention pertains to an electronic device and to a method for making it. The device is a heterojunction transistor, particularly a high electron mobility transistor, characterized by presence of a 2 DEG channel. Transistors of this invention contain an AlGaN barrier and a GaN buffer, with the channel disposed, when present, at the interface of the barrier and the buffer. Surface treated with ammonia plasma resembles untreated surface. The method pertains to treatment of the device with ammonia plasma prior to passivation to extend reliability of the device beyond a period of time on the order of 300 hours of operation, the device typically being a 2 DEG AlGaN/GaN high electron mobility transistor with essentially no gate lag and with essentially no rf power output degradation.
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: March 4, 2008
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Jeffrey A. Mittereder, Andrew P. Edwards, Steven C. Binari
  • Publication number: 20080032434
    Abstract: One embodiment of the invention relates to a method of manufacturing a light emitting diode. The method includes forming an insulating layer on an area, not covered by a seed layer, of at least one of a p-type semiconductor layer and an n-type semiconductor layer, wherein the impurity concentration varies on the surface of the area; and immersing at least part of the seed layer into an electrolyte having metal ions which tend to reduce and deposit on the seed layer under no bias voltage.
    Type: Application
    Filed: August 7, 2007
    Publication date: February 7, 2008
    Applicant: EPISTAR CORPORATION
    Inventors: Chia-Ming Chuang, Yu-Heng Shao, Liang-Sheng Chi, Yu-Chieh Huang, Tai-Chan Huo
  • Patent number: 7323217
    Abstract: An optical-interference type reflective panel and a method for making the same are disclosed, wherein the display panel has a substrate on which multiple supporting layers are firstly formed. Then, a plurality of first conductive optical film stacks, spacing layers and multiple second conductive optical film stacks are sequentially formed on the substrate. Finally, once the spacing layers are removed, optical-interference regulators are formed. Since said supporting layers forming step is prior to the first conductive optical film stacks, a precise back-side exposing step is not necessary so that the making procedure of the panel is simplified.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: January 29, 2008
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventors: Wen-Jian Lin, Hsiung-Kuang Tsai
  • Patent number: 7316784
    Abstract: A method of patterning a transparent conductive film adaptive for selectively etching a transparent conductive film without any mask processes, a thin film transistor for a display device using the same and a fabricating method thereof are disclosed. In the method of patterning the transparent conductive film, an inorganic material substrate is prepared. An organic material pattern is formed at a desired area of the inorganic material substrate. A thin film having a different crystallization rate depending upon said inorganic material and said organic material is formed. The thin film is selectively etched in accordance with said crystallization rate.
    Type: Grant
    Filed: February 10, 2004
    Date of Patent: January 8, 2008
    Assignee: LG.Philips LCD Co., Ltd.
    Inventors: Byung Chul Ahn, Byoung Ho Lim, Byeong Dae Choi
  • Patent number: 7315344
    Abstract: A method of fabricating a liquid crystal display device includes forming a gate electrode, a gate bus line, and a gate pad on a substrate using a first mask process, forming a gate insulating layer and an active layer on an entire surface of the substrate, forming a first organic material film on an entire surface of the substrate, removing a portion of the first organic material film to expose a first portion of the gate pad, depositing a transparent film on an entire surface of the substrate, patterning the transparent film using a second half-tone mask to form a data bus line, a source electrode, a drain electrode, a pixel electrode, a channel layer, and an ohmic contact layer, exposing portions of the data pad and data bus line using a third mask, forming a second organic material film on an entire surface of the substrate, depositing a low resistance material on the data bus line, coating a passivation film on the substrate, removing the second organic material film using a lift-off process to expose a s
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: January 1, 2008
    Assignee: LG.Philips LCD Co., Ltd.
    Inventor: Byoung Ho Lim
  • Publication number: 20070285591
    Abstract: An exemplary embodiment of a method of manufacturing a liquid crystal display panel according to the present invention comprises forming a storage electrode on a substrate, forming a gate electrode on the substrate, forming a gate insulating layer on the storage electrode and the substrate, wherein the thickness of the gate insulating layer is thinner on the storage electrode than the thickness on the substrate, forming a semiconductor pattern on the gate insulating layer, forming a source electrode on the semiconductor pattern, forming a drain electrode opposing the source electrode on the semiconductor pattern, wherein the drain electrode overlaps the storage electrode to form the storage capacitor, forming a passivation layer on the source and drain electrodes, wherein the passivation layer has a contact hole which exposes the drain electrode, and forming a pixel electrode connected to the drain electrode via the contact hole.
    Type: Application
    Filed: February 12, 2007
    Publication date: December 13, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD
    Inventors: Sang Moon MOH, Seung Jae KANG
  • Patent number: 7291363
    Abstract: A method of lubricating MEMS devices using fluorosurfactants 42. Micro-machined devices, such as a digital micro-mirror device (DMD™) 940, which make repeated contact between moving parts, require lubrication in order to prevent the onset of stiction (static friction) forces significant enough to cause the parts to stick irreversibly together, causing defects. These robust and non-corrosive fluorosurfactants 42, which consists of a hydrophilic chain 40 attached to a hydrophobic fluorocarbon tail 41, are applied by nebulization and replace the more complex lubricating systems, including highly reactive PFDA lubricants stored in polymer getters, to keep the parts from sticking. This lubrication process, which does not require the use of getters, is easily applied and has been shown to provide long-life, lower-cost, operable MEMS devices.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: November 6, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Seth Miller
  • Patent number: 7285436
    Abstract: A semiconductor light-emitting device exhibits high reflectance even with less number of pairs of light-reflecting layers, and allows light emitted from the active layer to be effectively extracted outside. This semiconductor light-emitting device is fabricated at good mass productivity by a semiconductor light-emitting device manufacturing method including the step of providing an active layer which generates light having a specified wavelength on a semiconductor substrate. On the semiconductor substrate, are stacked an AlxGa1-xAs layer and the active layer, in this order. Part of the AlxGa1-xAs layer with respect to the is changed into an AlOy layer (where y is a positive real number).
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: October 23, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Nakatsu, Takahisa Kurahashi, Tetsuroh Murakami, Shouichi Ooyama
  • Patent number: 7279351
    Abstract: In a method of passivating a semiconductor device with two types of transistors, e.g., NMOS and PMOS transistor, the semiconductor device is placed in a pressurized sealed chamber and at least two different passivating gases are introduced into the chamber. The two passivating gases can be selected to have one gas suitable for passivating PMOS transistors and the other gas suitable for NMOS transistors.
    Type: Grant
    Filed: May 3, 2006
    Date of Patent: October 9, 2007
    Assignee: Toppoly Optoelectronics Corp.
    Inventors: Yaw Ming Tsai, Shih Chang Chang, De Hua Deng, Shih Pin Wang
  • Patent number: 7228046
    Abstract: A method is provided for stabilizing an electro-optic substrate employed in a waveguide device. The method comprises cleaning a surface of the substrate, and exposing the device to a reactive oxide to passivate the surface. A layer of sealant is deposited on the substrate in a vacuum to seal the surface.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: June 5, 2007
    Assignee: Honeywell International, Inc.
    Inventors: Loren M. Hendry, Jeffrey E. Lewis, Jason C. Grooms, Charles B. Gray
  • Patent number: 7228043
    Abstract: An optical waveguide circuit comprising a plurality of first cores (203) arranged at intervals widening as they are away from the branch point or the joining point of optical signal, a clad (205) filling at least these first cores, and second cores (204) provided between the first cores and the clad and formed in the gap between the first cores in the vicinity of the branch point or the joining point while covering the first cores at least partially. Refractive index of the second core is larger than that of the clad, the boundary between the second core and the clad is smooth and the film thickness of the second core formed in the gap between the first cores is decreased as the interval of the plurality of first cores widens.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: June 5, 2007
    Assignee: NEC Corporation
    Inventor: Tsuyoshi Shimoda
  • Patent number: 7226798
    Abstract: A fabrication method for a multi-layered thin film protective layer, which is applicable on a substrate having a peripheral circuit area and a pixel cell area, is described. Metal layers and pixel cells are formed on the peripheral circuit area and the pixel cell area, respectively. A first oxide layer, a silicon nitride layer and a second oxide layer are sequentially formed on the pixel cells and the metal layers. The second oxide layer is then patterned to define a pre-determined position of a pad spacer in the pixel cell area and the peripheral circuit area. The silicon nitride layer and the first oxide layer are further defined to form a first protective layer in the peripheral circuit area and to from a pad spacer in the pixel cell area exposing the pixel cells. A second protective layer is then formed on the exposed pixel cells.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: June 5, 2007
    Assignee: United Microelectronics Corp.
    Inventors: Wei-Shiau Chen, Kao-Su Huang
  • Patent number: 7220612
    Abstract: A thin film transistor substrate and a fabricating method thereof for simplifying a process are disclosed. In a liquid crystal display device according to the present invention, a gate line is provided on a substrate. A data line crosses the gate line with having a gate insulating film therebetween to define a pixel area. A thin film transistor includes a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode opposed to the source electrode and a semiconductor layer for defining a channel between the source electrode and the drain electrode. A pixel electrode is connected to the drain electrode and is provided at said pixel area. Herein, said data line, said source electrode and said drain electrode have a double-layer structure in which a source/drain metal pattern and a transparent conductive pattern are built. Said pixel electrode is formed by an extension of the transparent conductive pattern of the drain electrode.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: May 22, 2007
    Assignee: LG.Philips LCD Co., Ltd.
    Inventors: Byung Chul Ahn, Joo Soo Lim, Byung Ho Park
  • Patent number: 7192787
    Abstract: MRAMs are provided with cells offering low current leakage for partially selected cells. MRAM cells are made with magnetic tunnel junctions having barriers that meet predetermined low barrier heights and predetermined thicknesses. The barrier heights are preferably about 1.5 eV or less. The predetermined thicknesses are calculated to meet power and speed requirements. The predetermined low barrier heights and predetermined thicknesses modify a nonlinear term relating current through to voltage across the magnetic tunnel junction. The modification of the nonlinear term also modifies the amount of current that flows through a magnetic tunnel junction at various voltages. At low voltages, current through the magnetic tunnel junction will be disproportionately lower than current through a conventional magnetic tunnel junction. This decreases leakage current through partially selected MRAM cells and power.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: March 20, 2007
    Assignee: International Business Machines Corporation
    Inventors: John Kenneth DeBrosse, Yu Lu, Stuart Stephen Papworth Parkin
  • Patent number: 7179673
    Abstract: A method of fabricating a liquid crystal display device is disclosed in the present invention. The method includes forming a thin film transistor in a pixel region and a pad on an edge region of a first substrate, depositing an organic passivation layer over the first substrate, and removing the organic passivation layer in the edge region using a diffraction mask to expose a portion of the pad, wherein the diffraction mask has a slit portion including a plurality of slits having different widths.
    Type: Grant
    Filed: October 23, 2003
    Date of Patent: February 20, 2007
    Assignee: LG.Philips LCD Co., Ltd.
    Inventors: In-Duk Song, Ho-Jin Ryu
  • Patent number: 7172915
    Abstract: An optical-interference type display panel and a method for making the same are disclosed, wherein the display panel has a substrate on which multiple first conductive optical film stacks, supporting layers and multiple second conductive optical film stacks are formed. The substrate further has a plurality of connecting pads consisting of a transparent conductive film of the first conductive optical film stacks. Since the transparent conductive film is made of indium tin oxide, these connecting pads have the excellent anti-oxidation ability at their surface.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: February 6, 2007
    Assignee: Qualcomm Mems Technologies Co., Ltd.
    Inventors: Wen-Jian Lin, Hung-Huei Hsu, Hsiung-Kuang Tsai
  • Patent number: 7172914
    Abstract: A method of forming a semiconductor structure includes forming an isolation region in a semiconductor substrate. A first oxide layer is on the substrate, a first sacrificial layer is on the first oxide layer, and a first nitride layer is on the first sacrificial layer. The first oxide layer may be a screen oxide layer, and the method provides consistency in the thickness of the screen oxide layer.
    Type: Grant
    Filed: January 2, 2001
    Date of Patent: February 6, 2007
    Assignee: Cypress Semiconductor Corporation
    Inventor: Sundar Narayanan
  • Patent number: 7125734
    Abstract: In a method for fabricating a flip-chip light emitting diode device, a submount wafer is populated with a plurality of the light emitting diode dies. Each device die is flip-chip bonded to the submount. Subsequent to the flip-chip bonding, a growth substrate is removed. The entire submount is immersed in the etchant solution, exposed to the light for a prespecified period of time, removed from the solution, dried and diced into a plurality of LEDs. The LEDs are immediately packaged without any further processing.
    Type: Grant
    Filed: March 9, 2005
    Date of Patent: October 24, 2006
    Assignee: GELcore, LLC
    Inventors: Michael J. Sackrison, Hari S. Venugopalan, Xiang Gao
  • Patent number: 7119487
    Abstract: A light emitting device which can be easily manufactured and can control the positions of light emission precisely, and an optical device. A first and second light emitting elements are formed on one face of a supporting base. The first light emitting element has an active layer made of GaInN mixed crystal on a GaN-made first substrate on the side thereof on which the supporting base is disposed. The second light emitting element has lasing portions on a GaAs-made second substrate on the side thereof on which the supporting base is disposed. Since the first and second light emitting elements are not grown on the same substrate, a multiple-wavelength laser having the output wavelength of around 400 nm can be easily obtained. Since the first substrate is transparent in the visible region, the positions of light emitting regions in the first and second light emitting elements can be precisely controlled by lithography.
    Type: Grant
    Filed: February 15, 2001
    Date of Patent: October 10, 2006
    Assignee: Sony Corporation
    Inventor: Masao Ikeda
  • Patent number: 7112545
    Abstract: The surface of a semiconductor material, e.g., gallium arsenide, is passivated by irradiating the surface with ultra-short laser pulses, until a stable passive surface is achieved. The passive surface so prepared is devoid of a superficial oxide layer.
    Type: Grant
    Filed: September 11, 2000
    Date of Patent: September 26, 2006
    Assignee: The Board of Trustees of the University of Arkansas
    Inventors: Tarak A. Railkar, Ajay P. Malshe, William D. Brown
  • Patent number: 7112478
    Abstract: A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel-interface layer-source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 ?-?m2. The interface layer may include a passivating material such as a nitride, a fluoride, an oxide, an oxynitride, a hydride and/or an arsenide of the semiconductor of the channel. In some cases, the interface layer consists essentially of a monolayer configured to depin the Fermi level of the semiconductor of the channel, or an amount of passivation material sufficient to terminate all or a sufficient number of dangling bonds of the semiconductor channel to achieve chemical stability of the surface.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: September 26, 2006
    Assignee: Acorn Technologies, Inc.
    Inventors: Daniel E. Grupp, Daniel J. Connelly
  • Patent number: 7110631
    Abstract: Disclosed is a method of adjusting a center channel wavelength of a group of channel wavelengths from of a plurality of modulated sources, integrated in a photonic integrated circuit (PIC), relative to the center of a wavelength passband of an optical combiner, such as an arrayed waveguide array (AWG), also integrated in the photonic integrated circuit (PIC) and optically coupled to outputs from the modulated sources.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: September 19, 2006
    Assignee: Infinera Corporation
    Inventors: Charles H. Joyner, Mark J. Missey, Radhakrishnan L. Nagarajan, Fred A. Kish, Jr.
  • Patent number: 7074628
    Abstract: A method and apparatus for identifying crystal defects in emitter-base junctions of NPN bipolar transistors uses a test structure having an NP junction that can be inspected using passive voltage contrast. The test structure eliminates the collector of the transistor and simulates only the emitter and base. Eliminating the collector removes an NP junction between collector and substrate of a wafer allowing charge to flow from the substrate to emitter if the emitter-base junction is defective since only one NP junction exists in the test structure. In one embodiment, the test structures are located between dies on a wafer and may be formed in groups of several thousand.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: July 11, 2006
    Assignee: Agere Systems, Inc.
    Inventors: Bradley J. Albers, Thomas Craig Esry, Daniel Charles Kerr, Edward Paul Martin, Jr., Oliver Desmond Patterson
  • Patent number: 7076126
    Abstract: A photonic integrated circuit (PIC) comprises a plurality of integrated optically coupled components formed in a surface of the PIC and a passivating layer overlies at least a portion of the PIC surface. The overlying passivating layer comprises a material selected from the group consisting of BCB, ZnS and ZnSe. Also, when the circuits are PIC chips are die in the semiconductor wafer, a plurality of linear cleave streets are formed in a wafer passivation layer where a pattern of the cleave streets define separate PIC chips in the wafer for their subsequent singulation from the wafer.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: July 11, 2006
    Assignee: Infinera Corporation
    Inventors: Charles H. Joyner, Mark J Missey, Radhakrishnan L. Nagarajan, Fred A. Kish, Jr.
  • Patent number: 7065266
    Abstract: An InP-based photonic integrated circuit (PIC) includes an optical passive element in the circuit with no bias current applied to such an element. A passivation cladding layer overlies a surface of the optical passive element where the passivation layer comprises benzocyclobutene polymer or BCB.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: June 20, 2006
    Assignee: Infinera Corporation
    Inventors: Charles H. Joyner, Mark J. Missey, Radhakrishnan L. Nagarajan, Fred A. Kish, Jr.
  • Patent number: 7065117
    Abstract: A semiconductor laser element includes: a stack of layers having resonator facets; and at least one protection layer formed on at least one of the resonator facets. Each of the at least one protection layer includes at least first, second, and third sublayers. The first sublayer is formed nearest to the stack among the at least first, second, and third sublayers, and made of a material not containing oxygen (or nitrogen) as a constituent element. The second sublayer is made of an oxide (or nitride) produced by oxidizing (or nitriding) a portion of the first sublayer. The third sublayer is formed farthest from the stack among the at least first, second, and third sublayers, and made of an oxide (or nitride). The thickness d2 of the second sublayer and the total thickness d1 of the first and second sublayers satisfy a relationship, 0.1?d2/d1?0.9.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: June 20, 2006
    Assignee: Fuji Photo Film Co., Ltd.
    Inventor: Fusao Yamanaka
  • Patent number: 7045376
    Abstract: A method of passivating a semiconductor device with two types of transistors, e.g., NMOS and PMOS transistors, the semiconductor device is placed in a pressurized sealed chamber and at least two different passivating gases are introduced into the chamber. The two passivating gases can be selected to have one gas suitable for passivating PMOS transistors and the other gas suitable for NMOS transistors.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: May 16, 2006
    Assignee: Toppoly Optoelectronics Corp.
    Inventors: Yaw Ming Tsai, Shih Chang Chang, De Hua Deng, Shih Pin Wang
  • Patent number: 7037741
    Abstract: A method for manufacturing a compound semiconductor optoelectronic device is proposed. There are steps of: forming an optoelectronic device epitaxial wafer, the optoelectronic device epitaxial wafer containing a V-shaped pit due to threading dislocation; forming an insulated isolation material in the V-shaped pit of the optoelectronic device epitaxial wafer; and forming an electrode layer on the optoelectronic device epitaxial wafer having the insulated isolation material in the V-shaped pit for completing the optoelectronic device.
    Type: Grant
    Filed: March 8, 2004
    Date of Patent: May 2, 2006
    Assignee: Epistar Corporation
    Inventors: Tzong-Liang Tasi, Yung-Chuan Yang, Chih-Sung Chang, Tzer-Perng Chen
  • Patent number: 7033850
    Abstract: A method for making organic light-emitting diodes on a flexible substrate includes supplying a flexible substrate, forming a plurality of thin-film layers on the flexible substrate to produce an organic light-emitting diode, disposing the flexible substrate above a barrier base and disposing a barrier cover over the substrate and the barrier base, and sealing the barrier base to the barrier cover to encapsulate the substrate between the barrier cover and the barrier base.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: April 25, 2006
    Assignee: Eastman Kodak Company
    Inventors: Yuan-Sheng Tyan, David R. Strip
  • Patent number: 7033852
    Abstract: A method and device for passivating the resonator end faces, in particular the cleaved edges of semiconductor laser diodes, by high-temperature epitaxy of the quaternary compound semiconductor InxGa1-xAsyP1-y, where (0?x?1 and 0?y?1). To passivate the InxGa1-xAsyP1-y, an additional passivation layer may be applied in situ. The semiconductor crystal is brought to the temperature required for the epitaxy by being heated. To avoid thermal destruction of the contact metal during the epitaxy, the metal is only deposited after the cleaving operation and the passivation. The deposition of the metal on the passivated laser bar is carried out by means of special equipment that allows deposition of metal on the entire surface of the laser and at the same time prevents vapour deposition on the cleaved edges. The method and device can be applied to the production of high-power laser diodes.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: April 25, 2006
    Assignee: Lumics GmbH
    Inventors: Karl Häusler, Nils Kirstaedter
  • Patent number: 7033848
    Abstract: A light emitting device is provided which has a structure for preventing degradation of a light emitting element due to water and oxygen contained in an interlayer insulating film formed between a TFT and the light emitting element. A TFT is formed on a substrate, an inorganic insulating film is formed on the TFT from an inorganic material and serves as a first insulating film, an organic insulating film is formed on the first insulating film from an organic material and serves as a second insulating film, and an inorganic insulating film is formed on the second insulating film from an inorganic material and serves as a third insulating film. Thus obtained is a structure for preventing the second insulating film from releasing moisture and oxygen. In order to avoid defect in forming the film, a portion of the third insulating film where a contact hole is formed is removed alone.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: April 25, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Murakami, Toru Takayama, Kengo Akimoto
  • Patent number: 7026178
    Abstract: Methods for fabricating a VCSEL having current confinement, the VCSEL having a substrate, a semiconductor active region, and a bottom mirror disposed between the substrate and the active region. A first top spacer layer is epitaxially grown on the active region, the first top spacer layer comprising a current-spreading buffer layer disposed on the active region, a current-confinement layer disposed on the buffer layer, and a current-spreading platform layer disposed on the current-confinement layer, wherein the combined thickness of the platform and current-confinement layers is less than the thickness of the buffer layer. A current-confinement structure having an annular region of enhanced resistivity and a central aperture of comparatively lower resistivity is formed in the current-confinement layer using ion implantation. Subsequently, epitaxial regrowth is performed to form a second top spacer layer on the platform layer, said second top spacer layer comprising a top current-spreading layer.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: April 11, 2006
    Assignee: Applied Optoelectronics, Inc.
    Inventors: Wen-Yen Hwang, Klaus Alexander Anselm
  • Patent number: 7026542
    Abstract: A transparent substrate for a cover for a solar battery and a method for producing the same are presented. Hemispherical concave portions are formed in a surface of light entering side of a cover glass almost over the entire surface wherein the ratio d/D of the depth d of the central portion of each concave portion to the radius D of the opening of the concave portion is from 0.10 to 0.50 and the proportion of area occupied by a flat portion where no concave portion is formed in the surface of light entering side is not more than 40%.
    Type: Grant
    Filed: March 22, 2004
    Date of Patent: April 11, 2006
    Assignee: Asahi Glass Company, Limited
    Inventors: Junichi Kageyama, Kazuo Sato, Mika Kambe
  • Patent number: 7016571
    Abstract: An arrayed waveguide grating (AWG) comprises at least two free space regions, a plurality of grating arms extending between the two space regions, a passivation layer formed over the arrayed waveguide grating and a plurality of inputs at least to one of the free space regions to receive a plurality of channel signals separated by a predetermined channel spacing. A depth of the passivation layer chosen by providing a TE to TM wavelength shift between TE and TM modes propagating through the arrayed waveguide grating being approximately less than or equal to 20% of a magnitude of the channel spacing.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: March 21, 2006
    Assignee: Infinera Corporation
    Inventors: Charles H. Joyner, Mark J. Missey, Radhakrishnan L. Nagarajan, Fred A. Kish, Jr.
  • Patent number: 7016655
    Abstract: A system that provides packaging for a surface acoustic wave filter in such a way that the surface acoustic wave filter is capable of integration with a number of additional electronic devices on an integrated substrate. The surface acoustic wave filter is mounted in a “flip chip” configuration that enables the surface of the surface acoustic wave filter to be protected from a molding compound during and after the encapsulation of the surface acoustic wave filter and other circuitry contained on the integrated substrate. The manner in which the surface acoustic wave filter is packaged provides a great reduction in cost and occupied real estate on the integrated substrate, in that, the surface acoustic wave filter is mounted in such as way as not to require conventionally used ceramic packaging that encases the surface acoustic wave filter. An air gap is preserved between the surface acoustic wave filter side of the surface acoustic wave filter and the integrated substrate on which it is mounted.
    Type: Grant
    Filed: June 3, 2004
    Date of Patent: March 21, 2006
    Assignee: Skyworks Solutions, Inc.
    Inventor: Nooshin D. Vakilian
  • Patent number: 6991951
    Abstract: A solid-state imaging device production method is provided. A light-receiving section 12 is formed on a semiconductor substrate 1. A first insulating film 6 is formed on a light-receiving section 12 and the semiconductor substrate 1. A metal film for wiring is formed on the first insulating film 6. A protection film 8 is formed on the metal film. A resist film is formed on a predetermined region of the protection film. A portion of the protection film 8 and a portion of the metal film is removed by using the resist film to form a wire 7 whose upper face is covered by the protection film 8. A hydrogen-containing second insulating film 10 is formed on the wire 7 and the first insulating film 6. A heating process is performed for the second insulating film 10. An anisotropic etching process is performed for the entire surface of the second insulating film 10 to remove the second insulating film 10.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: January 31, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Rieko Nishio, Toshihiro Kuriyama
  • Patent number: 6982182
    Abstract: Systems and methods of passivating planar index-guided oxide vertical cavity surface emitting lasers (VCSELs) are described. These systems and methods address the unique susceptibility of these devices to damage that otherwise might be caused by moisture intrusion into the etch holes that are used to form the index-guiding confinement regions. In one aspect, a VCSEL includes a vertical stack structure having a substantially planar top surface. The vertical stack structure includes a top mirror, a bottom mirror, and a cavity region disposed between the top mirror and the bottom mirror and including an active light generation region. At least one of the top mirror and the bottom mirror has a layer with a peripheral region that is oxidized into an electrical insulator as a result of exposure to an oxidizing agent. The vertical stack structure defines two or more etched holes each extending from the substantially planar top surface to the oxidized peripheral region.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: January 3, 2006
    Assignee: Agilent Technologies, Inc.
    Inventors: Seongsin Kim, Wilson H. Widjaja, Suning Xie
  • Patent number: 6979582
    Abstract: The present invention provides a vertical-cavity surface emitting laser (VCSEL) diode and a method for producing the same. In this method, an n-type and a p-type ohmic contact electrodes are previously disposed, and then two pairs of distributed Bragger reflectors (DBRs) are formed. At last, a permanent metal substrate is plated. According to the present invention, reflectivity of the DBRs can be preserved without damage during rapid thermal annealing, and thus brightness of the laser diode is improved.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: December 27, 2005
    Assignee: National Chung-Hsing University
    Inventors: Ray-Hua Horng, Dong-Sing Wu