Having Stacked Capacitor Structure (e.g., Stacked Trench, Buried Stacked Capacitor, Etc.) Patents (Class 438/387)
  • Patent number: 10121848
    Abstract: A method for fabricating a multi-layer, crown-shaped MIM capacitor is provided. A base having therein a conductive region within a capacitor-forming region is formed. An IMD layer is deposited on the base to cover the capacitor-forming region. A capacitor trench is formed within the capacitor-forming region. The capacitor trench penetrates through the IMD layer, thereby exposing a portion of the conductive region. A concentric capacitor lower electrode structure is formed within the capacitor trench. The concentric capacitor lower electrode structure includes a first electrode and a second electrode surrounded by the first electrode. The first electrode is in direct contact with the conductive region. A conductive supporting pedestal is formed within the capacitor trench for fixing and electrically connecting bottom portions of the first and second electrodes. A capacitor dielectric layer conformally lining the first and second electrodes and a top surface of the conductive supporting pedestal is formed.
    Type: Grant
    Filed: May 14, 2017
    Date of Patent: November 6, 2018
    Assignee: Powerchip Technology Corporation
    Inventors: Shyng-Yeuan Che, Wen-Yi Wong
  • Patent number: 9985089
    Abstract: Vertical metal-insulator-metal (MIM) capacitors include a metal conductor including a sidewall; a high k dielectric layer on the sidewall of the metal conductor; and a vertically oriented metal layer on the high k dielectric layer. Also disclosed are methods for fabricating the vertical MIM capacitor, wherein a single patterning/mask process can used to fabricate the vertical MIM capacitor structure.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 29, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Chih-Chao Yang
  • Patent number: 9755013
    Abstract: High density capacitor structures based on an array of semiconductor nanorods are provided. The high density capacitor structure can be a plurality of capacitors in which each of the semiconductor nanorods serves as a bottom electrode for one of the plurality of capacitors, or a large-area metal-insulator-metal (MIM) capacitor in which the semiconductor nanorods serve as a support structure for a bottom electrode of the MIM capacitor subsequently formed.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: September 5, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wai-Kin Li, Chengwen Pei, Ping-Chuan Wang
  • Publication number: 20150145103
    Abstract: A capacitive device includes a well, a first dielectric layer, a first conductive layer, a cap dielectric layer, and a first electrode. The well includes a first shoulder portion having an upper surface, a second shoulder portion having an upper surface, and a first trench, sandwiched between the first and second shoulder portions, having sidewalls and a bottom surfaces. The first dielectric layer is lined along at least a portion of the upper surfaces of the first and second shoulder portions, the sidewalls of the first trench, and the bottom surface of the first trench. The first conductive layer is lined along the first dielectric layer. The cap dielectric layer is over the well, the first dielectric layer, and the first conductive layer. The first electrode is in contact with the first shoulder portion.
    Type: Application
    Filed: November 27, 2013
    Publication date: May 28, 2015
    Applicant: Taiwan Semiconductor Mnaufacturing Company, Ltd.
    Inventors: Chung-Yen CHOU, Po-Ken LIN, Chia-Shiung TSAI, Ru-Liang LEE
  • Patent number: 9012296
    Abstract: A method for forming a trench capacitor includes providing a substrate of a semiconductor material having a hard mask layer; etching the hard mask layer and the substrate to form at least one trench extending into the substrate; and performing pull-back etching on the hard mask layer. In the pull-back etching, a portion of the hard mask layer defining and adjacent to side walls of an opening of the at least one trench is removed. A resulting opening on the hard mask layer has a width dimension larger than a width dimension of an opening of the at least one trench extending into the substrate. The method further comprises doping the semiconductor material defining upper surfaces and sidewalls of the at least one trench to form a doped well region.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: April 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wu-An Weng, Chen-Chien Chang
  • Publication number: 20150102464
    Abstract: Disclosed herein are a capacitor with a hole structure and a manufacturing method thereof. A capacitor with a hole structure includes: a substrate layer having a plurality of through-holes formed therein; a lower electrode layer including a first conductive layer having a low specific resistance and a second conductive layer having a specific resistance higher than that of the first conductive layer, the first conductive layer being formed on an inner wall of the through-hole and the second conducive layer being formed on the first conductive layer; a thin film dielectric layer formed on the lower electrode layer; and an upper electrode layer including a third conductive layer and a fourth conductive layer having a specific resistance lower than that of the third conductive layer, the third conductive layer being formed on the thin film dielectric layer and the fourth conductive layer being formed on the third conductive layer.
    Type: Application
    Filed: October 11, 2013
    Publication date: April 16, 2015
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young Sik KANG, Yeong Gyu LEE
  • Patent number: 9006061
    Abstract: A method of forming a capacitor comprises forming a first electrode of the capacitor over a substrate. The first electrode includes a bottom conductive plane and a plurality of first vertical conductive structures on the bottom conductive plane. The method also comprises forming an insulating structure over the first electrode. The method further comprises forming a second electrode of the capacitor over the insulating structure. The second electrode includes a top conductive plane and a plurality of second vertical conductive structures under the top conductive plane. The first vertical conductive structures of the plurality of first vertical conductive structures and the second vertical conductive structures of the plurality of second vertical conductive structures are interlaced with each other.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chewn-Pu Jou, Chen Ho-Hsiang, Fred Kuo, Tse-Hul Lu
  • Patent number: 8993396
    Abstract: A method for fabricating a capacitor includes forming a mold structure over a substrate, wherein the mold structure has a plurality of open parts and has a mold layer stacked with a support layer; forming cylinder type lower electrodes in the open parts; forming a first upper electrode over an entire surface of a structure including the cylinder type lower electrodes to fill the cylinder type lower electrodes; defining a through hole that passes through portions of the first upper electrode and the support layer; removing the mold layer through the through hole and exposing the cylinder type lower electrodes; forming a second upper electrode to fill the through hole and spaces between the cylinder type lower electrodes; and forming a third upper electrode to connect the second upper electrode and the first upper electrode with each other.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: March 31, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jong-Kook Park, Yong-Tae Cho
  • Patent number: 8946802
    Abstract: The specification and drawings present a new method, device and computer/software related product (e.g., a computer readable memory) are presented for realizing eDRAM strap formation in Fin FET device structures. Semiconductor on insulator (SOI) substrate comprising at least an insulator layer between a first semiconductor layer and a second semiconductor layer is provided. The (metal) strap formation is accomplished by depositing conductive layer on fins portion of the second semiconductor layer (Si) and a semiconductor material (polysilicon) in each DT capacitor extending to the second semiconductor layer. The metal strap is sealed by a nitride spacer to prevent the shorts between PWL and DT capacitors.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Sivananda Kanakasabapathy, Tenko Yamashita, Chun-Chen Yeb
  • Patent number: 8941211
    Abstract: An embodiment radio frequency area of an integrated circuit is disclosed. The radio frequency area includes a substrate having an implant region. The substrate has a first resistance. A buried oxide layer is disposed over the substrate and an interface layer is disposed between the substrate and the buried oxide layer. The interface layer has a second resistance lower than the first resistance. A silicon layer is disposed over the buried oxide layer and an interlevel dielectric is disposed in a deep trench. The deep trench extends through the silicon layer, the buried oxide layer, and the interface layer over the implant region. The deep trench may also extend through a polysilicon layer disposed over the silicon layer.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Yu Cheng, Wei-Kung Tsai, Kuan-Chi Tsai, Tsung-Yu Yang, Chung-Long Chang, Chun-Hong Chen, Chih-Ping Chao, Chen-Yao Tang, Yu Hung Chen
  • Patent number: 8932933
    Abstract: A method of forming a hydrophobic surface on a semiconductor device structure. The method comprises forming at least one structure having at least one exposed surface comprising titanium atoms. The at least one exposed surface of at least one structure is contacted with at least one of an organo-phosphonic acid and an organo-phosphoric acid to form a material having a hydrophobic surface on the at least one exposed surface of the least one structure. A method of forming a semiconductor device structure and a semiconductor device structure are also described.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: January 13, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Ian C. Laboriante, Prashant Raghu
  • Patent number: 8927365
    Abstract: The specification and drawings present a new method, device and computer/software related product (e.g., a computer readable memory) are presented for realizing eDRAM strap formation in Fin FET device structures. Semiconductor on insulator (SOI) substrate comprising at least an insulator layer between a first semiconductor layer and a second semiconductor layer is provided. The (metal) strap formation is accomplished by depositing conductive layer on fins portion of the second semiconductor layer (Si) and a semiconductor material (polysilicon) in each DT capacitor extending to the second semiconductor layer. The metal strap is sealed by a nitride spacer to prevent the shorts between PWL and DT capacitors.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Sivananda Kanakasabapathy, Tenko Yamashita, Chun-Chen Yeb
  • Patent number: 8912065
    Abstract: A method of fabricating a semiconductor device is described. A substrate having first and second areas is provided. A first patterned mask layer having at least one first opening in the first area and at least one second opening in the second area is formed over the substrate, wherein the first opening is smaller than the second opening. A portion of the substrate is removed with the first patterned mask layer as a mask to form first and second trenches respectively in the substrate in the first and second areas, wherein the width and the depth of the first trench are less than those of the second trench. A first dielectric layer is formed at least in the first and second trenches. A conductive structure is formed on the first dielectric layer on at least a portion of the sidewall of each of the first and second trenches.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: December 16, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Tieh-Chiang Wu, Wei-Ming Liao, Jei-Cheng Huang, Shin-Yu Nieh
  • Patent number: 8865544
    Abstract: Some embodiments include a method of forming a capacitor. An opening is formed through a silicon-containing mass to a base, and sidewalls of the opening are lined with protective material. A first capacitor electrode is formed within the opening and has sidewalls along the protective material. At least some of the silicon-containing mass is removed with an etch. The protective material protects the first capacitor electrode from being removed by the etch. A second capacitor electrode is formed along the sidewalls of the first capacitor electrode, and is spaced from the first capacitor electrode by capacitor dielectric. Some embodiments include multi-material structures having one or more of aluminum nitride, molybdenum nitride, niobium nitride, niobium oxide, silicon dioxide, tantalum nitride and tantalum oxide. Some embodiments include semiconductor constructions.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: October 21, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Joseph Neil Greeley, Duane M. Goodner, Vishwanath Bhat, Vassil N. Antonov, Prashant Raghu
  • Patent number: 8860113
    Abstract: A semiconductor structure is disclosed in which, in an embodiment, a first substrate includes at least one buried plate disposed in an upper part of the first substrate. Each of the at least one buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jennifer E. Appleyard, John E. Barth, John B. DeForge, Herbert L. Ho, Babar A. Khan, Kirk D. Peterson, Andrew A. Turner
  • Patent number: 8853048
    Abstract: The present disclosure provides a streamlined approach to forming vertically structured devices such as deep trench capacitors. Trenches and a contact plate bridging the trenches are formed using one lithographic process. A hard mask is formed over the substrate and etched through the mask to form two or more closely spaced trenches. The hard mask is then reduced by an isotropic etch process. The etch removes the hard mask preferentially between the trenches. Chemical mechanical polishing removes the conductive material down to the remaining hard mask layer, whereby conductive material remains in mask openings and forms a conductive bridge across the trenches.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wu-An Weng, Chen-Chien Chang
  • Patent number: 8841748
    Abstract: A dielectric wafer has, on top of its front face, a front electrical connection including an electrical connection portion. A blind hole passes through from a rear face of the wafer to at least partially reveal a rear face of the electrical connection portion. A through capacitor is formed in the blind hole. The capacitor includes a first conductive layer covering the lateral wall and the electrical connection portion (forming an outer electrode), a dielectric intermediate layer covering the first conductive layer (forming a dielectric membrane), and a second conductive layer covering the dielectric intermediate layer (forming an inner electrode). A rear electrical connection is made to the inner electrode.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: September 23, 2014
    Assignee: STMicroelectronics SA
    Inventors: Sylvain Joblot, Alexis Farcy, Jean-Francois Carpentier, Pierre Bar
  • Patent number: 8841749
    Abstract: A main blind hole is formed in a front face of a wafer having a rear face. A through capacitor is formed in the main blind hole including a conductive outer electrode, a dielectric intermediate layer, and a filling conductive material forming an inner electrode. Cylindrical portions of the outer electrode, the dielectric intermediate layer and the inner electrode have front ends situated in a plane of the front face of the wafer. A secondary rear hole is formed in the rear face of the wafer to reveal a bottom of the outer electrode. A rear electrical connection is made to contact the bottom of the outer electrode through the secondary rear hole. A through hole via filled with a conductive material is provided adjacent the through capacitor. An electrical connection is made on the rear face between the rear electrical connection and the through hole via.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: September 23, 2014
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Sylvain Joblot, Alexy Farcy, Jean-Francois Carpentier, Pierre Bar
  • Publication number: 20140264743
    Abstract: First and second multi-layer structures are formed within respective openings in at least one dielectric layer formed over a semiconductor substrate. The first multi-layer structure comprises a gate electrode, and the second multi-layer structure comprises a resistor and a first electrode of a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure is completed by forming a dielectric film on the at least one dielectric layer and forming a second electrode on the dielectric film.
    Type: Application
    Filed: May 30, 2013
    Publication date: September 18, 2014
    Inventors: Hsiu-Jung Yen, Jen-Pan Wang
  • Patent number: 8835250
    Abstract: A finFET trench circuit is disclosed. FinFETs are integrated with trench capacitors by employing a trench top oxide over a portion of the trench conductor. A passing gate is then disposed over the trench top oxide to form a larger circuit, such as a DRAM array. The trench top oxide is formed by utilizing different growth rates between polysilicon and single crystal silicon.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jonathan E. Faltermeier, Veeraraghavan S. Basker, Kangguo Cheng, Theodorus Eduardus Standaert
  • Patent number: 8828864
    Abstract: A semiconductor device and a method for manufacturing the same are disclosed. When forming a profile of the lower electrode, a second lower electrode hole (i.e., a bunker region) located at the lowermost part of the lower electrode is buried with an Ultra Low Temperature Oxide (ULTO) material without damaging the lower electrode material. As a result, when a dielectric film is deposited in a subsequent process, the above-mentioned semiconductor device prevents the occurrence of a capacitor leakage current caused by defective gapfilling of the dielectric film located at the lowermost part of the lower electrode.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: September 9, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyeong Uk Yun
  • Patent number: 8815677
    Abstract: A method for processing dielectric materials and electrodes to decrease leakage current is disclosed. The method includes a post dielectric anneal treatment in an oxidizing atmosphere to reduce the concentration of oxygen vacancies in the dielectric material. The method further includes a post metallization anneal treatment in an oxidizing atmosphere to reduce the concentration of interface states at the electrode/dielectric interface and to further reduce the concentration of oxygen vacancies in the dielectric material.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: August 26, 2014
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Hanhong Chen, Wim Deweerd, Xiangxin Rui, Sandra Malhotra, Hiroyuki Ode
  • Patent number: 8810007
    Abstract: A wiring board provided with a silicon substrate including a through hole that communicates a first surface and a second surface of the silicon substrate. A capacitor is formed on an insulating film, which is applied to the silicon substrate, on the first surface and a wall surface defining the through hole. A capacitor part of the capacitor includes a first electrode, a dielectric layer, and a second electrode that are sequentially deposited on the insulating film on the first surface and the wall surface of the through hole. A penetration electrode is formed in the through hole covered by the first electrode, the dielectric layer, and the second electrode of the capacitor part.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: August 19, 2014
    Assignees: Shinko Electric Industries Co., Ltd., Taiyo Yuden Co., Ltd.
    Inventors: Akihito Takano, Masahiro Sunohara, Hideaki Sakaguchi, Mitsutoshi Higashi, Kenichi Ota, Yuichi Sasajima
  • Patent number: 8759192
    Abstract: A wiring trench is formed in an interlayer insulating film partway in the depth direction of the interlayer insulating film. A via hole is formed extending from the bottom of the wiring trench to the bottom of the interlayer insulating film. A capacitor recess is formed reaching the bottom of the interlayer insulating film. A conductive member is embedded in the wiring trench and via hole. A capacitor is embedded in the capacitor recess, including a lower electrode, a capacitor dielectric film and an upper electrode. The lower electrode is made of the same material as that of the conductive member and disposed along the bottom and side surface of the capacitor recess. A concave portion is formed on an upper surface of the lower electrode, and the capacitor dielectric film covers an inner surface of the concave portion. The upper electrode is embedded in the concave portion.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: June 24, 2014
    Assignee: Fujitsu Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8728898
    Abstract: A method for fabricating a semiconductor device includes forming a mold layer over a substrate, wherein the mold layer includes a first sacrificial layer and a second sacrificial layer that are stacked, forming an insulation layer pattern that has an etch selectivity to the first sacrificial layer and the second sacrificial layer on the mold layer, etching the mold layer using the insulation layer pattern as an etch barrier to form storage node holes, forming a storage node conductive layer over a substrate structure including the insulation layer pattern and the mold layer that has been etched, performing a storage node isolation process that simultaneously forms storage nodes and forming the insulation layer pattern to a first thickness, and removing the first sacrificial layer and the second sacrificial layer.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: May 20, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Su-Young Kim
  • Patent number: 8728901
    Abstract: A method for fabricating a non-volatile, ferroelectric random access memory (F-RAM) device is described. In one embodiment, the method includes forming an opening in an insulating layer over a surface of a substrate, and forming bottom electrode spacers proximal to sidewalls of the opening. Next, a ferroelectric dielectric layer is formed in the opening over the surface of the substrate and between the bottom electrode spacers, and a pair of top electrodes is formed within the opening comprising first and second side portions displaced laterally from respective ones of the bottom electrode spacers by the ferroelectric dielectric layer.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: May 20, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shan Sun, Thomas Davenport, John Cronin
  • Patent number: 8722505
    Abstract: A semiconductor capacitor with large area plates and a small footprint is formed on a semiconductor wafer by forming an opening in the wafer, depositing a first metal atoms through a first shadow mask that lies spaced apart from the wafer to form a first metal layer in the opening, a dielectric layer on the first metal layer, and a second metal atoms through a second shadow mask that lies spaced apart from the wafer to form a second metal layer on the dielectric layer.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: May 13, 2014
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, William French
  • Publication number: 20140120690
    Abstract: The present disclosure provides a streamlined approach to forming vertically structured devices such as deep trench capacitors. Trenches and a contact plate bridging the trenches are formed using one lithographic process. A hard mask is formed over the substrate and etched through the mask to form two or more closely spaced trenches. The hard mask is then reduced by an isotropic etch process. The etch removes the hard mask preferentially between the trenches. Chemical mechanical polishing removes the conductive material down to the remaining hard mask layer, whereby conductive material remains in mask openings and forms a conductive bridge across the trenches.
    Type: Application
    Filed: November 1, 2012
    Publication date: May 1, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wu-An Weng, Chen-Chien Chang
  • Patent number: 8691656
    Abstract: The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: April 8, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Brett W. Busch, David K. Hwang, F. Daniel Gealy
  • Publication number: 20140080280
    Abstract: An embodiment relates to a method of forming a semiconductor structure, comprising: forming a first semiconductor layer; forming a second semiconductor layer over the first semiconductor layer; forming a third semiconductor layer over the second semiconductor layer; forming an opening in the first, second and third semiconductor layers; forming a conductive region within the first, the and third semiconductor layer, the conductive region surrounding the opening, the conductive region being electrically coupled to the first semiconductor layer; forming a dielectric layer in the opening and over the conductive region; and forming a conductive layer over the dielectric layer in the opening.
    Type: Application
    Filed: November 25, 2013
    Publication date: March 20, 2014
    Inventors: Detlef WILHELM, Guenter PFEIFER, Bernd EISENER, Dieter CLAEYS
  • Publication number: 20140070294
    Abstract: A finFET trench circuit is disclosed. FinFETs are integrated with trench capacitors by employing a trench top oxide over a portion of the trench conductor. A passing gate is then disposed over the trench top oxide to form a larger circuit, such as a DRAM array. The trench top oxide is formed by utilizing different growth rates between polysilicon and single crystal silicon.
    Type: Application
    Filed: September 13, 2012
    Publication date: March 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan E. Faltermeier, Veeraraghavan S. Basker, Kangguo Cheng, Theodorus Eduardus Standaert
  • Patent number: 8664075
    Abstract: A dual node dielectric trench capacitor includes a stack of layers formed in a trench. The stack of layers include, from bottom to top, a first conductive layer, a first node dielectric layer, a second conductive layer, a second node dielectric layer, and a third conductive layer. The dual node dielectric trench capacitor includes two back-to-back capacitors, which include a first capacitor and a second capacitor. The first capacitor includes the first conductive layer, the first node dielectric layer, the second conductive layer, and the second capacitor includes the second conductive layer, the second node dielectric layer, and the third conductive layer. The dual node dielectric trench capacitor can provide about twice the capacitance of a trench capacitor employing a single node dielectric layer having a comparable composition and thickness as the first and second node dielectric layers.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: March 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Keith Kwong Hon Wong, Ramachandra Divakaruni, Roger A. Booth, Jr.
  • Publication number: 20140057408
    Abstract: A rectangular capacitor for dynamic random access memory (DRAM) and a dual-pass lithography method to form the same are described. For example, a capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. A cup-shaped metal plate is disposed along the bottom and sidewalls of the trench. A second dielectric layer is disposed on and conformal with the cup-shaped metal plate. A trench-fill metal plate is disposed on the second dielectric layer. The second dielectric layer isolates the trench-fill metal plate from the cup-shaped metal plate. The capacitor has a rectangular or near-rectangular shape from a top-down perspective.
    Type: Application
    Filed: November 4, 2013
    Publication date: February 27, 2014
    Inventor: Nick Lindert
  • Patent number: 8652926
    Abstract: A method of forming capacitors includes providing first capacitor electrodes within support material. The first capacitor electrodes contain TiN and the support material contains polysilicon. The polysilicon-containing support material is dry isotropically etched selectively relative to the TiN-containing first capacitor electrodes using a sulfur and fluorine-containing etching chemistry. A capacitor dielectric is formed over sidewalls of the first capacitor electrodes and a second capacitor electrode is formed over the capacitor dielectric. Additional methods are disclosed.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: February 18, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Gurpreet Lugani, Kevin J. Torek
  • Publication number: 20140015097
    Abstract: Some embodiments include a method of forming a capacitor. An opening is formed through a silicon-containing mass to a base, and sidewalls of the opening are lined with protective material. A first capacitor electrode is formed within the opening and has sidewalls along the protective material. At least some of the silicon-containing mass is removed with an etch. The protective material protects the first capacitor electrode from being removed by the etch. A second capacitor electrode is formed along the sidewalls of the first capacitor electrode, and is spaced from the first capacitor electrode by capacitor dielectric. Some embodiments include multi-material structures having one or more of aluminum nitride, molybdenum nitride, niobium nitride, niobium oxide, silicon dioxide, tantalum nitride and tantalum oxide. Some embodiments include semiconductor constructions.
    Type: Application
    Filed: July 11, 2012
    Publication date: January 16, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Joseph Neil Greeley, Duane M. Goodner, Vishwanath Bhat, Vassil N. Antonov, Prashant Raghu
  • Patent number: 8627259
    Abstract: According to one exemplary embodiment, a method for adjusting geometry of a capacitor includes fabricating a first composite capacitor residing in a first standard cell with a first set of process parameters. The method further includes using a second standard cell having substantially same dimensions as the first standard cell. The method further includes using a capacitance value from the first composite capacitor to adjust a geometry of a second composite capacitor residing in the second standard cell, wherein the second composite capacitor is fabricated with a second set of process parameters. The geometry of the second composite capacitor can be adjusted to cause the second composite capacitor to have a capacitance value substantially equal to the capacitance value from the first composite capacitor.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: January 7, 2014
    Assignee: Broadcom Corporation
    Inventors: Peter Huang, Ming-Chun Chen
  • Patent number: 8627258
    Abstract: According to one exemplary embodiment, a method for adjusting geometry of a capacitor includes fabricating a first composite capacitor residing in a first standard cell with a first set of process parameters. The method further includes using a second standard cell having substantially same dimensions as the first standard cell. The method further includes using a capacitance value from the first composite capacitor to adjust a geometry of a second composite capacitor residing in the second standard cell, wherein the second composite capacitor is fabricated with a second set of process parameters. The geometry of the second composite capacitor can be adjusted to cause the second composite capacitor to have a capacitance value substantially equal to the capacitance value from the first composite capacitor.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: January 7, 2014
    Assignee: Broadcom Corporation
    Inventors: Peter Huang, Ming-Chun Chen
  • Patent number: 8617980
    Abstract: A substrate is provided with a first wiring layer 111, an interlayer insulating film 132 on the first wiring layer 111, a hole 112A formed in the interlayer insulating film, a first metal layer 112 covering the hole 112A, a second metal layer 113 formed in the hole 112A, a dielectric insulating film 135 on the first metal layer 112, and second wiring layers 114-116 on the dielectric insulating film 135, wherein the first metal layer 112 constitutes at least part of the lower electrode, an area, facing the lower electrode, of the second wiring layers 114-116 constitutes the upper electrode, and a capacitor 160 is constructed of the lower electrode, the dielectric insulating film 135 and the upper electrode P1.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: December 31, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Publication number: 20130337629
    Abstract: A method of fabricating a semiconductor device is described. A substrate having first and second areas is provided. A first patterned mask layer having at least one first opening in the first area and at least one second opening in the second area is formed over the substrate, wherein the first opening is smaller than the second opening. A portion of the substrate is removed with the first patterned mask layer as a mask to form first and second trenches respectively in the substrate in the first and second areas, wherein the width and the depth of the first trench are less than those of the second trench. A first dielectric layer is formed at least in the first and second trenches. A conductive structure is formed on the first dielectric layer on at least a portion of the sidewall of each of the first and second trenches.
    Type: Application
    Filed: June 15, 2012
    Publication date: December 19, 2013
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Tieh-Chiang Wu, Wei-Ming Liao, Jei-Cheng Huang, Shin-Yu Nieh
  • Patent number: 8609504
    Abstract: The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: December 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Fen Chen, Baozhen Li
  • Publication number: 20130307118
    Abstract: Semiconductor devices, methods of manufacture thereof, and methods of manufacturing capacitors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a capacitor over a workpiece. The capacitor includes a bottom electrode, a capacitor dielectric disposed over the bottom electrode, and a top electrode disposed over the capacitor dielectric. A portion of the bottom electrode and a portion of the top electrode are removed proximate edges of the capacitor dielectric.
    Type: Application
    Filed: May 15, 2012
    Publication date: November 21, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Kuo-Chi Tu
  • Patent number: 8586444
    Abstract: A semiconductor structure and method of fabricating the same are disclosed. In an embodiment, the structure includes a first substrate having a buried plate or plates in the substrate. Each buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jennifer E. Appleyard, John E. Barth, Jr., John B. DeForge, Herbert L. Ho, Babar A. Khan, Kirk D. Peterson, Andrew A. Turner
  • Patent number: 8563403
    Abstract: A method includes forming a first integrated circuit (IC) device having a first substrate, an alignment via defined in the first substrate, a first wiring layer over the alignment via, and a first bonding layer over the first wiring layer; forming a second IC device having a second substrate, a second wiring layer over the second substrate, and a second bonding layer over the second wiring layer; bonding the first bonding layer of first IC device to the second bonding layer of second IC device; thinning a backside of the first IC device so as to expose the alignment via; and using the exposed alignment via to form a deep, through substrate via (TSV) that passes through the first IC device, through a bonding interface between the first IC device and second IC device, and landing on the second wiring layer of the second IC device.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Spyridon Skordas, Richard P. Volant, Kevin R. Winstel
  • Patent number: 8563391
    Abstract: A method for forming a metal-insulator-metal capacitor in a multilevel semiconductor device utilizes the copper interconnect levels of the semiconductor device as parts of the capacitor. A lower capacitor plate consists of a copper interconnect level and a first metal layer formed on the copper interconnect level by selective deposition methods. The upper capacitor plate includes the same pattern as the capacitor dielectric, the pattern having an area less than the area of the lower capacitor plate. The upper capacitor plate is formed of a second metal layer. The first and second metal layers may each be formed of cobalt, tungsten, nickel, molybdenum, or a combinations of one of the aforementioned elements with boron and/or phosphorus. Conductive vias provide contact from the upper capacitor plate and lower capacitor plate, to interconnect levels.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: October 22, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Chun-Hong Chen, Minghsing Tsai
  • Patent number: 8558345
    Abstract: A capacitor in a semiconductor substrate employs a conductive through-substrate via (TSV) as an inner electrode and a columnar doped semiconductor region as an outer electrode. The capacitor provides a large decoupling capacitance in a small area, and does not impact circuit density or a Si3D structural design. Additional conductive TSV's can be provided in the semiconductor substrate to provide electrical connection for power supplies and signal transmission therethrough. The capacitor has a lower inductance than a conventional array of capacitors having comparable capacitance, thereby enabling reduction of high frequency noise in the power supply system of stacked semiconductor chips.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: October 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: Tae Hong Kim, Edmund J. Sprogis, Michael F. McAllister, Michael J. Shapiro
  • Publication number: 20130234288
    Abstract: A method for manufacturing a MIM capacitor trench structure includes forming a lower metal film on an inter-metal dielectric; forming a first inter-metal dielectric on the lower metal film; forming a first trench; sequentially forming a dielectric film and a first barrier metal film along the bottom surface and sidewalls of the first trench; and filling the first trench with a conductive material to form a first upper metal film. Further, the method includes forming a second inter-metal dielectric on the first upper metal film; forming a second trench; forming a via hole in a via hole region of the second inter-metal dielectric; forming a second barrier metal film along the bottom surface and sidewalls of the second trench; and filling the via hole and the second trench with the conductive material to form a via contact and a second upper metal film.
    Type: Application
    Filed: September 13, 2012
    Publication date: September 12, 2013
    Inventors: Sung Mo GU, Moon Hyung CHO, Young Sang KIM, Jong Bum PARK
  • Patent number: 8518792
    Abstract: Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM that allows for the formation of a ferroelectric capacitor with separated PZT layers aligned with a preexisting, three dimensional (3-D) transistor structure.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: August 27, 2013
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shan Sun, Thomas E. Davenport, John Cronin
  • Patent number: 8518773
    Abstract: A method of fabricating a semiconductor capacitor includes forming a cavity in a first dielectric layer. Then, a nitride stack comprising a slow-etch nitride layer disposed between two fast-etch nitride layers is deposited in the cavity. Next, a portion of the nitride stack is etched within the cavity. Continuing, a metal plug is deposited in the cavity. The fast-etch nitride layers of the nitride stack are removed while preserving the slow-etch nitride layer of the nitride stack. A first metal layer is deposited over the slow-etch nitride layer, a second dielectric layer is deposited over the first metal layer, and a second metal layer is deposited over the second dielectric layer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 27, 2013
    Assignee: International Business Machines Corporation
    Inventors: David Vaclav Horak, Shom Ponoth, Hosadurga Shobha, Chih-Chao Yang
  • Patent number: 8518791
    Abstract: Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating the same in the form of a damascene self-aligned F-RAM device comprising a PZT capacitor built on the sidewalls of an oxide trench, while allowing for the simultaneous formation of two ferroelectric sidewall capacitors.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: August 27, 2013
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shan Sun, Thomas E. Davenport, John Cronin
  • Patent number: 8502294
    Abstract: A semiconductor process for a memory array with buried digit lines is described. A first trench is formed in a semiconductor substrate. A liner layer is formed on the sidewall of the first trench. A second trench is formed in the substrate under the first trench. A mask layer is formed at the bottom of the second trench. An isotropic doping process is performed using the liner layer and the mask layer as a mask to form a digit-side junction only in the substrate at the sidewall of the second trench.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: August 6, 2013
    Assignee: Nanya Technology Corporation
    Inventors: Shyam Surthi, Lars Heineck