Abstract: A method for manufacturing a MIM capacitor trench structure includes forming a lower metal film on an inter-metal dielectric; forming a first inter-metal dielectric on the lower metal film; forming a first trench; sequentially forming a dielectric film and a first barrier metal film along the bottom surface and sidewalls of the first trench; and filling the first trench with a conductive material to form a first upper metal film. Further, the method includes forming a second inter-metal dielectric on the first upper metal film; forming a second trench; forming a via hole in a via hole region of the second inter-metal dielectric; forming a second barrier metal film along the bottom surface and sidewalls of the second trench; and filling the via hole and the second trench with the conductive material to form a via contact and a second upper metal film.

Abstract: A method of fabricating a semiconductor capacitor includes forming a cavity in a first dielectric layer. Then, a nitride stack comprising a slow-etch nitride layer disposed between two fast-etch nitride layers is deposited in the cavity. Next, a portion of the nitride stack is etched within the cavity. Continuing, a metal plug is deposited in the cavity. The fast-etch nitride layers of the nitride stack are removed while preserving the slow-etch nitride layer of the nitride stack. A first metal layer is deposited over the slow-etch nitride layer, a second dielectric layer is deposited over the first metal layer, and a second metal layer is deposited over the second dielectric layer.

Abstract: Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM that allows for the formation of a ferroelectric capacitor with separated PZT layers aligned with a preexisting, three dimensional (3-D) transistor structure.

Abstract: Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating the same in the form of a damascene self-aligned F-RAM device comprising a PZT capacitor built on the sidewalls of an oxide trench, while allowing for the simultaneous formation of two ferroelectric sidewall capacitors.

Abstract: A semiconductor process for a memory array with buried digit lines is described. A first trench is formed in a semiconductor substrate. A liner layer is formed on the sidewall of the first trench. A second trench is formed in the substrate under the first trench. A mask layer is formed at the bottom of the second trench. An isotropic doping process is performed using the liner layer and the mask layer as a mask to form a digit-side junction only in the substrate at the sidewall of the second trench.

Abstract: A memory device includes an array of electrodes that includes thin film plates of electrode material. Multilayer strips are arranged as bit lines over respective columns in the array of electrodes, including a layer of memory material and a layer of top electrode material. The multilayer strips have a primary body and a protrusion having a width less than that of the primary body and is self-aligned with contact surfaces on the thin film plates. Memory material in the protrusion contacts surfaces on the distal ends of thin film plates of electrodes in the corresponding column in the array. The device can be made using a damascene process in self-aligned forms over the contact surfaces.

Abstract: Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a semiconductor structure includes a trench capacitor within a silicon substrate, the trench capacitor including: an outer trench extending into the silicon substrate; a dielectric liner layer in contact with the outer trench; a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench within the outer trench; and a silicide layer over a portion of the doped polysilicon layer, the silicide layer separating at least a portion of the contact from at least a portion of the doped polysilicon layer; and a contact having a lower surface abutting the trench capacitor, a portion of the lower surface not abutting the silicide layer.

Abstract: A dual node dielectric trench capacitor includes a stack of layers formed in a trench. The stack of layers include, from bottom to top, a first conductive layer, a first node dielectric layer, a second conductive layer, a second node dielectric layer, and a third conductive layer. The dual node dielectric trench capacitor includes two back-to-back capacitors, which include a first capacitor and a second capacitor. The first capacitor includes the first conductive layer, the first node dielectric layer, the second conductive layer, and the second capacitor includes the second conductive layer, the second node dielectric layer, and the third conductive layer. The dual node dielectric trench capacitor can provide about twice the capacitance of a trench capacitor employing a single node dielectric layer having a comparable composition and thickness as the first and second node dielectric layers.

Abstract: An improved semiconductor capacitor and method of fabrication is disclosed. A MIM stack, comprising alternating first-type and second-type metal layers (each separated by dielectric) is formed in a deep cavity. The entire stack can be planarized, and then patterned to expose a first area, and selectively etched to recess all first metal layers within the first area. A second selective etch is performed to recess all second metal layers within a second area. The etched recesses can be backfilled with dielectric. Separate electrodes can be formed; a first electrode formed in said first area and contacting all of said second-type metal layers and none of said first-type metal layers, and a second electrode formed in said second area and contacting all of said first-type metal layers and none of said second-type metal layers.

Abstract: A method of fabricating a trench capacitor, and a trench capacitor fabricated thereby, are disclosed. The method involves the use of a vacuum impregnation process for a sol-gel film, to facilitate effective deposition of high-permittivity materials within a trench in a semiconductor substrate, to provide a trench capacitor having a high capacitance while being efficient in utilization of semiconductor real estate.

Abstract: An embodiment of the invention includes a pillar type capacitor where a pillar is formed over an upper portion of a storage node contact. A bottom electrode is formed over sidewalls of the pillar, and a dielectric film is formed over pillar and the bottom electrode. A top electrode is then formed over the upper portion of the dielectric film.

Abstract: In a method of manufacturing a semiconductor device, a plurality of sacrificial layers and a plurality of insulating interlayers are repeatedly and alternately on a substrate. The insulating interlayers include a different material from a material of the sacrificial layers. At least one opening through the insulating interlayers and the sacrificial layers are formed. The at least one opening exposes the substrate. The seed layer is formed on an inner wall of the at least one opening using a first silicon source gas. A polysilicon channel is formed in the at least one opening by growing the seed layer. The sacrificial layers are removed to form a plurality of grooves between the insulating interlayers. A plurality of gate structures is formed in the grooves, respectively.

Abstract: A method and structure is directed to eDRAM cells with high-conductance electrodes. The method includes forming upper layers on a semiconductor substrate and forming an opening in the upper layers. The method further includes forming a trench in the semiconductor substrate, aligned with the opening.

Abstract: The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided.

Abstract: A semiconductor structure having U-shaped transistors includes source/drain regions at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. Methods of forming semiconductor structures are also disclosed.

Abstract: Provided is a semiconductor device, including a silicon substrate, a first insulating film formed on the silicon substrate, a first conductive plug formed in an inside of a first contact hole of the first insulating film, an underlying conductive film having a flat surface formed on the first conductive plug and in the circumference thereof, a crystalline conductive film formed on the underlying conductive film, and a capacitor in which a lower electrode, a dielectric film made of a ferroelectric material, and an upper electrode are laminated in this order on the crystalline conductive film.

Abstract: A method of manufacturing a capacitor of a semiconductor device includes forming a high-k dielectric pattern on a semiconductor substrate, the high-k dielectric pattern having a pillar shape including a hole therein, forming a lower electrode in the hole of the high-k dielectric pattern, locally forming a blocking insulating pattern on an upper surface of the lower electrode, and forming an upper electrode covering the high-k dielectric pattern and the blocking insulating pattern.

Abstract: A semiconductor device substrate is presented here. The semiconductor device substrate includes a layer of first semiconductor material having a first lattice constant, a region of second semiconductor material located in the layer of first semiconductor material, and a layer of epitaxially grown third semiconductor material overlying the layer of first semiconductor material and overlying the region of second semiconductor material. The second semiconductor material has a second lattice constant that is different than the first lattice constant. Moreover, the layer of epitaxially grown third semiconductor material exhibits a stressed zone overlying the region of second semiconductor material. The stressed zone has a third lattice constant that is different than the first lattice constant.

Abstract: The present invention relates to a plasma etching method and apparatus for preparing high-aspect-ratio structures. The method includes the steps of placing the substrate into a plasma etching apparatus, wherein the plasma etching apparatus includes an upper electrode plate and a lower electrode plate; continuously supplying an upper source RF power and a DC power to the upper electrode plate; and discontinuously supplying a bias RF power to the lower electrode plate. When the bias RF power is switched to the off state, a large amount of secondary electrons pass through the bulk plasma and reach the substrate to neutralize the positive ions during the duration time of the off state (Toff).

Abstract: Forming a capacitor structure includes forming a first dielectric layer over a conductive region, wherein the first dielectric layer has a first conductive layer at a top surface of the first dielectric layer; forming a first opening in the first dielectric layer over the conductive region, wherein the first opening exposes a first sidewall of the first conductive layer; forming a second conductive layer within the first opening, wherein the second conductive layer contacts the first sidewall of the first conductive layer; removing a portion of the second conductive layer from the bottom of the first opening; forming an insulating layer within the first opening; removing a portion of the insulating layer from the bottom of the first opening; extending the first opening through the first dielectric layer to expose the conductive region; and filling the first opening with a conductive material, wherein the conductive material contacts the conductive region.

Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Abstract: To provide a dielectric film having good crystallinity while suppressing an influence of the size effects and preventing the dielectric film from being divided by an Al-doped layer although there is provided the Al-doped layer for improving the leakage characteristics in the dielectric film of a capacitor, the dielectric film has at least one Al-doped layer, and an area density of Al atoms in one layer of the Al-doped layer is smaller than 1.4E+14 atoms/cm2. Further, to achieve the area density, there is employed a combination of formation of a dielectric film using a general ALD method and Al doping using an adsorption site blocking ALD method including adsorbing a blocker molecule restricting an adsorption site of an Al source, adsorbing the Al source, and introducing a reaction gas for reaction.

Abstract: A method of forming an MIM capacitor having interdigitated capacitor plates. Metal and dielectric layers are alternately deposited in an opening in a layer of insulator material. After each deposition of the metal layer, the metal layer is removed at an angle from the side to form the capacitor plate. The side from which the metal layer is removed is alternated with every metal layer that is deposited. When all the capacitor plates have been formed, the remaining opening in the layer of insulator material is filled with dielectric material then planarized, followed by the formation of contacts with the capacitor plates. There is also an MIM capacitor structure having interdigitated capacitor plates.

Abstract: A fabricating method for a pixel structure is provided. First, a substrate having an active device and a capacitor electrode line thereon is provided. Next, a passivation layer is formed on the substrate to cover the active device. After that, a light shielding layer is formed on the passivation layer to define a unit area. Next, an ink-jet printing is performed to form a color filter pattern within the unit area defined by the light shielding layer. After that, a portion of the color filter pattern is removed to form a first hole above active device. Next, the passivation layer exposed by the first hole is removed so as to form a contact hole exposing a portion of the active device. After that, a pixel electrode is formed on the color filter pattern to fill into the contact hole so as to electrically connect with active device.

Abstract: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive metal nitride-comprising material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Inner sidewalls of the conductive material within the trench are annealed in a nitrogen-comprising atmosphere. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area. The conductive material within the array area is incorporated into a plurality of capacitors.

Abstract: According to one exemplary embodiment, a method for adjusting geometry of a capacitor includes fabricating a first composite capacitor residing in a first standard cell with a first set of process parameters. The method further includes using a second standard cell having substantially same dimensions as the first standard cell. The method further includes using a capacitance value from the first composite capacitor to adjust a geometry of a second composite capacitor residing in the second standard cell, wherein the second composite capacitor is fabricated with a second set of process parameters. The geometry of the second composite capacitor can be adjusted to cause the second composite capacitor to have a capacitance value substantially equal to the capacitance value from the first composite capacitor.

Abstract: A method of forming a capacitor structure includes forming a pad oxide layer overlying a substrate, a nitride layer overlying the pad oxide layer, an interlayer dielectric layer overlying the nitride layer, and a patterned polysilicon mask layer overlying the interlayer dielectric layer. The method then applies a first RIE process to form a trench region through a portion of the interlayer dielectric layer using the patterned polysilicon mask layer and maintaining the first RIE to etch through a portion of the nitride layer and through a portion of the pad oxide layer. The method stops the first RIE when a portion of the substrate has been exposed. The method then forms an oxide layer overlying the exposed portion of the substrate and applies a second RIE process to continue to form the trench region by removing the oxide layer and removing a portion of the substrate to a predetermined depth.

Abstract: Provided is a method of manufacturing a semiconductor device having a capacitor under bit line (CUB) structure capable of increasing a gap between a bit line in a cell area and an upper plate of a capacitor, reducing coupling capacitance therebetween, and forming deep contacts in a logic area. A capacitor including a lower electrode, a dielectric material layer, and an upper electrode is formed in an opening of a first insulating layer for exposing a first part of a semiconductor substrate in a cell area. A second insulating layer is formed on the first insulating layer. The first and second insulating layers are etched. First and second contact plugs are formed in first and second contact holes for exposing second and third parts in the cell area and the logic area. A third insulating layer including first through third conductive studs is formed on the second insulating layer.

Abstract: A method includes providing an SOI substrate including a layer of silicon disposed atop a layer of an oxide, the layer of an oxide being disposed atop the semiconductor substrate; forming a deep trench having a sidewall extending through the layer of silicon and the layer of an oxide and into the substrate; depositing a continuous spacer on the sidewall to cover the layer of silicon, the layer of an oxide and a part of the substrate; depositing a first conformal layer of a conductive material throughout the inside of the deep trench; creating a silicide within the deep trench in regions extending through the sidewall into an uncovered part of the substrate; removing the first conformal layer from the continuous spacer; removing the continuous spacer; depositing a layer of a high k dielectric material throughout the inside of the deep trench, and depositing a second conformal layer of a conductive material onto the layer of a high-k dielectric material.

Abstract: A capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. A first metal plate is disposed along the bottom and sidewalls of the trench. A second dielectric layer is disposed on and conformal with the first metal plate. A portion of the first metal plate directly adjacent to the second dielectric layer is recessed relative to the sidewalls of the second dielectric layer. A second metal plate is disposed on and conformal with the second dielectric layer. A portion of the second metal plate directly adjacent to the second dielectric layer is recessed relative to the sidewalls of the second dielectric layer. A third dielectric layer is disposed above the first metal plate, the second dielectric layer, and the second metal plate, and disposed between the first metal plate and the second dielectric layer and between the second metal plate and the second dielectric layer.

Abstract: Methods of forming an oxide are disclosed and include contacting a ruthenium-containing material with a tantalum-containing precursor and contacting the ruthenium-containing material with a vapor that includes water and optionally molecular hydrogen (H2). Articles including a first crystalline tantalum pentoxide and a second crystalline tantalum pentoxide on at least a portion of the first crystalline tantalum pentoxide, wherein the first tantalum pentoxide has a crystallographic orientation that is different than the crystallographic orientation of the second crystalline tantalum pentoxide, are also disclosed.

Abstract: The invention relates to a method for producing a solid electrolytic capacitor with excellent LC value, comprising sequentially stacking a dielectric oxide film, a semiconductor layer and an electrode layer on a sintered body of conductive powder to which an anode lead is connected and then encapsulating the whole with an outer jacket resin, wherein surface area of a cathode plate used in forming the semiconductor layer on the dielectric oxide film by applying current between the conductor having the dielectric oxide film thereon used as anode and the cathode plate provided in electrolysis solution is made larger by 10 times or more than its apparent surface area to thereby efficiently form the semiconductor layer, a capacitor produced by the method, and electronic circuits and electronic devices using the capacitor.

Abstract: A capacitor structure in trench structures of a semiconductor device includes conductive regions made of metallic and/or semiconducting materials. The conducting regions are surrounded by a dielectric and form stacked layers in the trench structure of the semiconductor device.

Abstract: A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory material. Accordingly, the conductive path in the memory cells passes from the top electrode through the conductive cup-shaped member, and through the plug of phase change material to the bottom electrode.

Abstract: Trench capacitors and methods of manufacturing the trench capacitors are provided. The trench capacitors are very dense series capacitor structures with independent electrode contacts. In the method, a series of capacitors are formed by forming a plurality of insulator layers and a plurality of electrodes in a trench structure, where each electrode is formed in an alternating manner with each insulator layer. The method further includes planarizing the electrodes to form contact regions for a plurality of capacitors.

Abstract: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive metal nitride-comprising material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Inner sidewalls of the conductive material within the trench are annealed in a nitrogen-comprising atmosphere. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area. The conductive material within the array area is incorporated into a plurality of capacitors.

Abstract: The invention includes methods in which one or more components of a carboxylic acid having an aqueous acidic dissociation constant of at least 1×10?6 are utilized during the etch of oxide (such as silicon dioxide or doped silicon dioxide). Two or more carboxylic acids can be utilized. Exemplary carboxylic acids include trichloroacetic acid, maleic acid, and citric acid.

Abstract: A method of grinding a molded semiconductor package to a desired ultra thin thickness without damage to the package is disclosed. Prior to grinding a molded package to a desired package thickness, the package may be protected from excessive mechanical stress generated during grinding by applying a protective tape to enclose interconnects formed on the package. This way, the protective tape provides support to the semiconductor package during package grinding involving the mold material as well as the die. In the post-grind package, the grinded die surface may be exposed and substantially flush with the mold material. The protective tape may then be removed to prepare the post-grind package for connection with an external device or PCB.

Abstract: Provided is a semiconductor device, including a silicon substrate, a first insulating film formed on the silicon substrate, a first conductive plug formed in an inside of a first contact hole of the first insulating film, an underlying conductive film having a flat surface formed on the first conductive plug and in the circumference thereof, a crystalline conductive film formed on the underlying conductive film, and a capacitor in which a lower electrode, a dielectric film made of a ferroelectric material, and an upper electrode are laminated in this order on the crystalline conductive film.

Abstract: Disclosed herein is a method of fabricating a capacitor of a semiconductor device that includes sequentially forming an interlayer insulating film defining a contact plug, a lower electrode oxide film, and a hard mask film over a semiconductor substrate; etching the hard mask film with a mask comprising a dummy pattern and a cell pattern to form a hard mask pattern wherein a first trench is formed in a dummy pattern region and a second trench is formed in a cell pattern region; forming a capping film that buries the first trench; and etching the lower electrode oxide film with the capping film and the hard mask pattern as a mask to form a lower electrode trench that exposes the contact plug.

Abstract: A method for manufacturing capacitor lower electrodes of a semiconductor memory firstly forms a first stacked structure over a semiconductor substrate which has a plurality of conductive plugs. Then a second stacked structure is formed on the first stacked structure; furthermore, a plurality of trenches extending from a top surface of the second stacked structure to a bottom surface of the first stacked structure are formed and expose the conducting plugs; finally, conductive metal materials and solid conducting cylindrical structures are deposited in the trenches in turn, and the conductive metal materials contact with the conductive plugs and the conducting cylindrical structures. Each conducting cylindrical structure is a capacitor lower electrode. Accordingly, the present invention can increase the supporting stress of the capacitor lower electrodes and further reduce the difficulty in disposing of capacitor upper electrodes and capacitor dielectric layers outside the capacitor lower electrodes.

Abstract: A capacitor has an MIM (Metal Insulator Metal) structure comprising a lower electrode formed in the interior of an electrode trench which is formed in an interlayer insulating film, a dielectric film formed over the lower electrode, and an upper electrode formed over the dielectric film. The upper electrode and the dielectric film are each formed with an area larger than the area of the lower electrode so that the whole of the lower electrode is positioned inside the upper electrode and the dielectric film. The reliability and production yield of the capacitor are improved.

Abstract: A microelectronic substrate and method for removing adjacent conductive and nonconductive materials from a microelectronic substrate. In one embodiment, the microelectronic substrate includes a substrate material (such as borophosphosilicate glass) having an aperture with a conductive material (such as platinum) disposed in the aperture and a fill material (such as phosphosilicate glass) in the aperture adjacent to the conductive material. The fill material can have a hardness of about 0.04 GPa or higher, and a microelectronics structure, such as an electrode, can be disposed in the aperture, for example, after removing the fill material from the aperture. Portions of the conductive and fill material external to the aperture can be removed by chemically-mechanically polishing the fill material, recessing the fill material inwardly from the conductive material, and electrochemically-mechanically polishing the conductive material.

Abstract: A semiconductor device with reduced contact resistance between a substrate and a plug includes a gate electrode disposed over the substrate, the plug formed over the substrate at both sides of the gate electrode and having a sidewall with a positive slope, a capping layer disposed between the gate electrode and the plug, and a gate hard mask layer whose sidewall disposed over the gate electrode is extended to a top surface of the capping layer. By employing the capping layer having a sidewall with a negative slope, the plug having the sidewall with a positive slope can be formed regardless of a shape or profile of the sidewall of the gate electrode. As a result, the contact area between the substrate and the plug is increased.

Abstract: The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure.

Abstract: A method for forming a capacitive structure in a metal level of an interconnection stack including a succession of metal levels and of via levels, including the steps of: forming, in the metal level, at least one conductive track in which a trench is defined; conformally forming an insulating layer on the structure; forming, in the trench, a conductive material; and planarizing the structure.

Abstract: A method for fabricating a capacitor arrangement which includes at least three electrodes is described. The capacitor arrangement is fabricated using a number of lithography methods that is smaller than the number of electrodes. A capacitor arrangement extending over more than two or more interlayers between metallization layers has a high capacitance per unit area and can be fabricated in a simple way is also described. The circuit arrangement has a high capacitance per unit area and can be fabricated in a simple way. An electrode layer is first patterned using a dry-etching process and residues of the electrode layer are removed using a wet-chemical process, making it possible to fabricate capacitors with excellent electrical properties.

Abstract: A memory cell includes a substrate, an access transistor and a storage capacitor. The access transistor comprising a gate stack disposed on the substrate, and a first and second diffusion region located on a first and second opposing sides of the gate stack. The storage capacitor comprises a first capacitor plate comprising a portion embedded within the substrate below the first diffusion region, a second capacitor plate and a capacitor dielectric sandwiched between the embedded portion of the first capacitor plate. At least a portion of the first diffusion region forms the second capacitor plate.

Abstract: A process of forming a semiconductive capacitor device for a memory circuit includes forming a first capacitor cell recess and a second capacitor cell recess that are spaced apart by a capacitor cell boundary of a first height. The process includes lowering the first height of the capacitor cell boundary to a second height. A common plate capacitor bridges between the first recess and the second recess over the boundary above the second height and below the first height.

Abstract: Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a semiconductor structure includes a trench capacitor within a silicon substrate, the trench capacitor including: an outer trench extending into the silicon substrate; a dielectric liner layer in contact with the outer trench; a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench within the outer trench; and a silicide layer over a portion of the doped polysilicon layer, the silicide layer separating at least a portion of the contact from at least a portion of the doped polysilicon layer; and a contact having a lower surface abutting the trench capacitor, a portion of the lower surface not abutting the silicide layer.