Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode ("bottom electrodes") of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.

Abstract: A discontinuous film structure on a surface which may be a substrate, with an underlying layer on the surface having a first opening formed therein, a separator layer on the underlying layer having a second opening formed therein, and the second opening overlying the first opening such that the separator layer overhangs the underlying layer. A discontinuous-as-deposited film is formed on the separator layer, with the discontinuity substantially in register with the second opening. The structure is made into a stacked capacitor with the discontinuous film being the bottom electrode, by forming a continuous dielectric layer on the bottom electrode and a continuous top electrode layer on the dielectric layer.

Abstract: Methods of forming capacitors and related integrated circuitry are described. In a preferred embodiment, the capacitors form part of a dynamic random access memory (DRAM) cell. According to one aspect of the invention, a first insulating layer is formed over a semiconductive material layer. A conductive gate is formed over the semiconductive material layer. A second insulating layer is formed over the gate and thereafter etched to form a capacitor container. In one implementation, such etch is conducted to outwardly expose the semiconductive material layer. In another implementation, such etch continues into the semiconductive material layer. In yet another implementation, such etch is conducted completely through the semiconductive material layer and into the first insulating layer. In a preferred implementation, a storage capacitor is formed within the capacitor container which extends both elevationally above and elevationally below the gate.

Abstract: The present invention relates to a method for arrangement of a buried capacitor on a substrate or the like, and a buried capacitor arranged according to the method. In order to diminish the resistive losses in a capacitor and to make it more efficient, in semi-conductor circuits, instead of the polycrystalline layer, one or more bodies of metal such as aluminum or tungsten may be used. This has been made possible using a new technique in which a trench filling of conducting material is etched away without removal through etching of the insulating layer in the trench. After the removal through etching of the trench filling, the trench is filled using the metal as above, whereby the insulating layer between the conducting material and the metal body will separate two conducting surfaces, thereby forming the buried capacitor.

Abstract: An integrated circuit and a method of manufacturing an integrated circuit comprises forming an insulator over a substrate, forming a trench in the insulator and the substrate, undercutting the insulator to form a gate conductor opening between the substrate and the insulator adjacent the trench, and forming a gate oxide and gate conductor in the gate conductor opening.

Abstract: A production process for a capacitor electrode formed of a platinum metal includes producing a conductive electrode body on a substrate having a silicon-containing surface for the capacitor electrode. Platinum is deposited over the full surface, the platinum is silicized in a temperature step outside the electrode body and the platinum silicide is removed. The advantage of the invention is the avoidance of an etching process for metallic platinum.

Abstract: A semiconductor device includes a semiconductor substrate having a trench on a surface thereof and an embedding member embedding the interior of the trench therewith. While the section of the trench when cut by a first plane perpendicular to the direction of the depth of the trench is defined as a first section and the section of the trench when cut by a second plane perpendicular to the direction of the depth of the trench and closer to the bottom of the trench than the first plane is defined as a second section, the area of the first section is smaller than that of the second section and a minimum radius of curvature of the first section is smaller than a minimum radius of curvature of the second section. As a result, it is possible to lessen the concentration of the electric field into the bottom of the trench.

Abstract: A pair of memory cells for use in a DRAM are formed in a monocrystalline bulk portion of a silicon wafer by first forming a pair of vertical trenches spaced apart by a bulk portion of the wafer. After a dielectric layer is formed over the walls of each trench, the trenches are each filled with polycrystalline silicon. By a pair of recess forming and recess filling steps there is formed at the top of each trench a silicon region that was grown epitaxially with the intermediate bulk portion. Each epitaxial region is made to serve as the body of a separate transistor having its drain in the lower polysilicon fill of a trench, and its source in the monocrystalline bulk intermediate between the two epitaxial regions. The lower polysilicon fill of each trench is also made to serve as the storage node of the capacitor of each cell, with the bulk serving as the other plate of the capacitor.

Abstract: An array of DRAM cells having Y-shaped multi-fin stacked capacitors with increased capacitance is achieved. A planar first insulating layer is formed over the semi-conductor devices on the substrate. Polycide bit lines are formed on the first insulating layer, and a second insulating layer and a silicon nitride (Si.sub.3 N.sub.4) etch-stop layer are conformally deposited. A multilayer, composed of a alternating insulating and polysilicon layers, is conformally deposited over the bit lines. Capacitor node contact openings are etched in the multilayer and in the underlying layers to the substrate. A fourth polysilicon layer is deposited sufficiently thick to fill the node contact openings and to form the node contacts. The multilayer is then patterned to leave portions over the node contacts, and an isotropic etch is used to remove the insulating layers exposed in the sidewalls of the patterned multilayer to provide Y-shaped multi-fin capacitor bottom electrodes over the bit lines.

Abstract: Reduced variations in buried layer across the chip is provided. The reduction in variation is achieved by defining the top surface of the buried layer and then the lower surface of the buried layer. This results in improved control buried strap variations, thereby improving performance of the IC.

Abstract: The present invention discloses a novel multiple fin-shaped capacitor for use in semiconductor memories. The capacitor has a plurality of horizontal fins and a crown shape. The capacitor structure comprises a bottom storage electrode. The bottom storage electrode comprises of a plurality of horizontal fins and a crown shape, wherein said crown shape includes two vertical pillars, and said plurality of horizontal fins extend outside from an external surface of said crown shape. A second dielectric layer is formed on the surface of the bottom storage electrode layer. A top storage electrode layer is formed along the surface of second dielectric layer. By including horizontal fins and vertical pillars, the surface area of the capacitor is significantly increased, resulting in increased capacitance.

Abstract: A method of fabricating an embedded dynamic random access memory. Using the method of dual damascence, by forming patterning only one dielectric layer, the contact windows with different depth are formed. In addition, the metal layer formed within the metal connecting regions are used as interconnects without further process.

Abstract: A method for the formation of field effect transistors (FETs), and more particularly metal oxide field effect transistors (MOSFETs), comprising the steps of: forming a dielectric stack on a semiconductor structure; defining an etch window on the dielectric stack; defining a gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process; depositing a side wall layer; removing the side wall layer from horizontal surfaces of the dielectric stack and gate hole such that side wall spacers remain which reduce the lateral size of the gate hole; depositing a gate conductor such that it fills the gate hole; removing the gate conductor covering the portions of the semiconductor structure surrounding the gate hole; removing at least part of the dielectric stack; and removing the side wall spacers.

Abstract: A method for improving the interface between a silicon nitride film and a silicon surface is described. According to the present invention a silicon nitride film is formed on a silicon surface of a substrate. While said substrate is heated the silicon nitride film is exposed to an ambient comprising hydrogen (H.sub.2). In a prefered embodiment of the present invention the ambient comprises H.sub.2 and N.sub.2.

Abstract: A method of fabricating a capacitor in a DRAM. A semiconductor substrate having a metal-oxide-semiconductor is provided. Using only one photolithography process, a bottom electrode is formed. By forming a dielectric layer over the substrate, and a poly-silicon layer on the dielectric layer, a capacitor is formed.

Abstract: A method for increasing the surface area, and thus the capacitance of a DRAM, stacked capacitor structure, has been developed. A storage node electrode, incorporating branches of polysilicon, is created via use of multiple polysilicon and insulator depositions, as well as via the use of dry anisotropic, and wet isotropic, etching procedures. The use of polysilicon spacers, created on the sides of silicon oxide mesas, adds a vertical component to the polysilicon branches. Removal of a portion of insulator layer from between polysilicon branches, results in exposure of the increased storage node electrode surface area. Unetched portions of the insulator layers, between polysilicon branches, supply structural support for the storage node electrode, comprised of polysilicon branches.

Abstract: A method of fabricating a ferroelectric capacitor structure by sequentially depositing a bottom electrode layer, a ferroelectric layer and a top electrode layer on a base structure, optionally with deposition of a layer of a conductive barrier material beneath the bottom electrode layer, to form a capacitor precursor structure, and planarizing the capacitor precursor structure by chemical mechanical polishing to yield the ferroelectric capacitor structure, e.g., a stack capacitor or trench capacitor. The process is carried out without dry etching of the electrode layers or dry etching of the ferroelectric layer, to yield ferroelectric capacitors having a very small feature size, as for example between 0.10 and 0.20 .mu.m.

Abstract: A double layer planar polysilicon capacitor for use within integrated circuits and a method by which that planar polysilicon capacitor is formed. Formed within a semiconductor substrate is a deep trench which is filled with a dielectric material. Formed within the dielectric material within the deep trench is a shallow trench which has a first polysilicon capacitor plate formed therein. The upper surface of the first polysilicon capacitor plate is substantially planar with the semiconductor substrate. Formed upon the first polysilicon capacitor plate is a polysilicon capacitor dielectric layer. Formed upon the polysilicon capacitor dielectric layer is a second polysilicon capacitor plate.

Abstract: A container capacitor having a recessed conductive layer. The recessed conductive layer is typically made of polysilicon. The recessed structure reduces the chances of polysilicon "floaters," which are traces of polysilicon that remain on the surface of the substrate, coupling adjacent capacitors together to create short circuits. The disclosed method of creating such a recessed structure uses chemical mechanical planarization to remove the layer of polysilicon and an overlying layer of photoresist from the upper surface of the substrate in which a container is formed. A wet etch selectively isolates a rim of the polysilicon within the container to recess the a rim, while the remainder of the polysilicon in the container is protected by the layer of photoresist.

Abstract: A method for forming square shape images in a lithographic process is disclosed wherein a first plurality of lines running in a first direction is defined in a first, usually sacrificial, layer, and then a second resist is defined wherein the lines run in an intersecting pattern to those of the first layer, thereby creating cornered images wherever the first and second layer intersect and in the open areas between the lines. Methods are proposed for developing the square intersecting areas and the square angle areas defined by the openings. Additionally, a photomask is disclosed in which the length and width of the cornered images are independently patterned using the two-exposure process.

Abstract: A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a trench in the semiconductor substrate between said first active region and said second active region. A first dielectric layer is then formed on said trench and a polysilicon layer is deposited on said first dielectric layer. The polysilicon layer is then thermally oxidized to form a second dielectric layer. Preferably the first dielectric is a thermal oxide 40 to 500 angstroms in thickness consuming less than 200 angstroms of said first active region and said second active region. The polysilicon layer is preferably between 1000 to 2000 angstroms.

Abstract: A twin bit DRAM cell capable of storing two bits of digital data as stored charge within the DRAM cell is disclosed. The twin bit DRAM cell has two pass transistors, a trench capacitor, and a stack capacitor. The pass transistors each have a source connected to a bit line voltage generator to control placement of the charge within the twin bit DRAM cell, a gate connected to a word line voltage generator to control activation of the DRAM cells, and a drain. The trench capacitor has a top plate connected to the drain of the first pass transistor and a bottom plate connected to a first biasing voltage source. The stack capacitor has a first plate connected to the drain of the second pass transistor and a second plate connected to a second biasing voltage generator. Twin bit DRAM cells will be arranged in a plurality of rows and columns to form an array of twin bit DRAM cells.

Abstract: Thin film capacitors are formed by a multi-level dry processing method that includes simultaneous ablation of via openings through both the dielectric and the metal electrode layers of a capacitor. Preferably, the dielectric films are formed of barium strontium titanate and the metal electrode layers are formed of platinum. The present invention overcomes the problems associated with the use of strong etchants to sequentially form separate via openings through the electrode and dielectric layers, prevents the potential for delamination of the respective layers during wet etching and the possible undesirable effects of etching solutions on substrate materials.

Abstract: A DRAM capacitor structure and its manufacturing include covering a semiconductor substrate with a first conducting layer. A first insulating layer and a second insulating layer are alternately stacked at least once above the first conducting layer to form a multi-layered structure. A contact window opening is formed in the multi-layered structure to expose a source/drain region located above the semiconductor substrate. A pattern is etch-defined on the multi-layered structure, using the first insulating layer as an etching stop layer. Part of the second insulating layer is etched away to form a cross-sectional profile similar to twin towers, with each tower having the form of a vertical T-stack. A second conducting layer covers the multi-layered structure. The first insulating layer and the second insulating layer of the multi-layered structure, as well as the second conducting layer in a top part of the multi-layered structure, are etched away to form a lower electrode.

Abstract: A method of forming a capacitor for DRAM or other circuits is described which avoids the problem of weak spots or gaps forming between a polysilicon contact plug and the first capacitor plate. A layer of first dielectric is formed on a substrate, A layer of second dielectric is formed on the layer of first dielectric. A layer of third dielectric is formed on the layer of second dielectric. A first hole is formed in the first, second, and third dielectrics exposing a contact region of the substrate. The first hole is then filled with a protective material and a second hole is formed in the layer of third dielectric using the layer of second dielectric as an etch stop. The first hole lies within the periphery of the second hole. The protective material prevents re-deposition of the third dielectric.

Abstract: A dynamic random access memory (DRAM) integrated circuit (10). The DRAM (10) includes a recessed region (20) defined in a semiconductor substrate (22). This recessed region has substantially vertical sides (34) extending from a bottom surface (32). A field effect transistor (18) is defined adjacent to the recessed region (20). A capacitor structure, including a lower capacitor plate (26), a capacitor dielectric (28), and an upper capacitor plate (30), is defined in the recessed region (20) and over the field effect transistor (18), thereby providing a greater capacitor surface.

Abstract: The present invention disclosed a structure of a charge storage electrode the and manufacturing method therefor. The present invention features forming initial oxide pattern(s) having viscous property at certain temperatures on a barrier layer as rectangular bar-shaped pattern(s) and applying heat to the oxide pattern(s) to transform the initial oxide pattern(s) to cylindrical oxide pattern(s); depositing polysilicon layer on the cylindrical oxide pattern(s); etching each end of the portions of the polysilicon layer and removing the oxide pattern(s); so as to provide a charge storage electrode structure having at least one conduit(s) which is formed with a polysilicon. The charge storage electrode structure according to the present invention has an increased effective surface area and is manufactured by a relatively simple method facilitating the manufacture of highly integrated semiconductor device.

Abstract: A method for fabricating a capacitor on a substrate includes the steps of forming an insulating layer on the substrate, and forming the first plate electrode on the insulating layer. A first dielectric layer is then formed on the plate electrode, and a first common storage electrode is formed on the first dielectric layer. A contact hole is then formed through the insulating layer, the first plate electrode, the first dielectric layer, and the first common storage electrode, thereby exposing a predetermined portion of the substrate. A first spacer is formed on a sidewall of the contact hole, and a conductive plug is formed in the contact hole extending from the substrate to the first common storage electrode.

Abstract: There is provided a method for manufacturing a capacitor in a semiconductor device including the steps of forming first and second insulating layers with a first contact hole through to a semiconductor substrate, patterning a first conductive layer to form a pedestal portion of a lower electrode, using a patterned third insulating layer selectively forming an upper portion of the lower electrode from a tungsten nitride thin film, and forming an undercut beneath the pedestal portion by wet-etching the second insulating layer.

Abstract: A crown-shape capacitor node is formed using a tapered etching process to increase the capacitance of the capacitor. A doped polysilicon layer is deposited over a substrate from which the capacitor node is formed. A tapered trench is formed in a doped polysilicon layer using a mask layer. The mask layer is removed and a dielectric layer is deposited over the doped polysilicon layer and filling the tapered trench. The dielectric layer is then etched back, leaving residual portions in the tapered trench. The doped polysilicon layer is then etched using the dielectric material in the tapered trench as an etching mask. The resulting capacitor node has tapered sidewalls, which increases the surface area of the capacitor node, thereby increasing the capacitor's capacitance. The mask layer can be formed so that the tapered etching process forms the capacitor node with either tapered exterior sidewalls or a tapered trench.

Abstract: A method is described for making an array of dynamic random access memory (DRAM) cells having a trench/stacked capacitor within each cell. The method involves forming trenches in the silicon substrate at the capacitor node contact areas of the DRAM cells, and using liquid phase deposition (LPD) of silicon oxide in the trenches to form oxide plugs that extend upward into the openings in the photoresist mask used to etch the trenches. After removing the photoresist, polysilicon sidewall spacers are formed on the LPD oxide plugs. The sidewall spacers become part of the stacked capacitor structures. Another patterned polysilicon layer is used to form the array of storage-node electrodes for the stacked capacitors, and also serve as the storage-node electrodes for the trench capacitors. Conventional methods are used to complete the array of trench/stacked capacitors by depositing an interelectrode dielectric layer and then forming the polysilicon top electrodes.