Abstract: A capacitor structure is formed over a semiconductor substrate by atomic layer deposition to achieve uniform thickness in memory cell dielectric layers, particularly where the dielectric layer is formed in a container-type capacitor structure. In accordance with several embodiments of the present invention, a process for forming a capacitor structure over a semiconductor substrate is provided. Other embodiments of the present invention relate to processes for forming memory cell capacitor structures, memory cells, and memory cell arrays. Capacitor structures, memory cells, and memory cell arrays are also provided.

Abstract: Methods of forming merged logic DRAM devices on silicon-on-insulator (SOI) wafers having a relatively thick buried oxide region, where deep trenches are etched into the SOI substrate without etching through the buried oxide layer are provided. The methods of the present invention provide high performance SOI merged logic DRAM devices.

Abstract: Provided is a method of integrating Ta2O5 into an MIS stack capacitor for a semiconductor device by forming a thin SiON layer at the Si/TaO interface using low temperature remote plasma oxidation anneal. Also provided is a method of forming an MIS stack capacitor with improved electrical performance by treating SiO2 with remote plasma nitridation or SiN layer with rapid thermal oxidation or RPO to form a SiON layer prior to Ta2O5 deposition with TAT-DMAE, TAETO or any other Ta-containing precursor.

Abstract: A method for etching trenches includes providing a patterned mask stack on a substrate. A trench is etched in the substrate by forming a tapered-shaped trench portion of the trench, which narrows with depth in the substrate by employing a first plasma chemistry mixture including O2, HBr and NF3. An extended portion of the trench is formed by etching a second profile deeper and wider than the tapered-shaped trench portion in the substrate by employing a second plasma chemistry mixture including O2, HBr and SF6 or F2.

Abstract: An isolation oxide film (2) has a recess. The bottom of the recess is below the upper surfaces of a P well (21) and an N well (22). A capacitor is provided on the bottom of the recess.

Abstract: The integrated circuit comprises a semiconductor substrate SB supporting a memory cell PM of the DRAM type comprising an access transistor T and a storage capacitor TRC. The access transistor is made on the substrate, and the substrate includes a capacitive trench TRC buried beneath the transistor and forming the storage capacitor, the capacitive trench being in contact with one of the source and drain regions of the transistor.

Abstract: A method of fabricating a capacitor of a DRAM cell. First, an insulating layer is formed on the semiconductor substrate at the top portion of the trench. Afterward, a seed layer on the ringed insulating layer and the semiconductor substrate at the bottom portion of the trench. A photoresist is coated in the trench at the bottom portion. Next, the seed layer is partially removed to expose the ringed insulating layer while the photoresist is used as the shield. The photoresist is then removed to expose the remaining seed layer at the bottom portion. A hemispherical silicon grain layer is deposited from the remaining seed layer on the semiconductor substrate. Ions are doped the hemispherical silicon grain layer and the semiconductor substrate so as to create a doped area to serve as the lower electrode of the capacitor.

Abstract: A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented. An Ru silicide layer is formed on the surface of a plug in a through hole formed below a lower electrode for an information storage capacitance device C and an Ru silicon nitride layer is formed further on the surface of the Ru silicide layer. Upon high temperature heat treatment in an oxygen atmosphere conducted in the step of forming a dielectric film on the lower electrode, the Ru silicon nitride layer is oxidized sacrificially into an Ru silicon oxynitride to prevent progress of oxidation in the Ru silicide layer.

Abstract: A process flow for forming a sacrificial collar (132) within a deep trench (113) of a semiconductor memory cell. A nitride liner layer (120) is deposited over a substrate (111). A thin polysilicon layer (122) is deposited over the nitride liner layer (120), and an oxide layer (124) is formed. A resist (116) is deposited within the trenches (113) and etched back. The top portion of the oxide layer (124) is removed, and the resist (116) is removed from the trenches (113). The wafer (100) is exposed to a nitridation process to form a nitride layer (128) over exposed portions of the polysilicon layer (122). The oxide layer (124) and polysilicon layer (124) are removed from the bottom of the trenches. (113). The nitride liner layer (120) is removed from the bottom of the trenches (113). The polysilicon layer (122) is removed from the top of the trenches (113) to leave a sacrificial collar (132) in the top of the trenches 113 formed by nitride liner layer (120).

Abstract: Within a method for fabricating a capacitor structure, and a capacitor structure fabricated employing the method, there is formed within an isolation region adjoining an active region of a semiconductor substrate a laterally asymmetric trench which leaves exposed an upper sidewall portion of the active region of the semiconductor substrate. There is then formed within the laterally asymmetric trench a capacitor node layer which contacts the exposed upper sidewall portion of the active region of the semiconductor substrate and extends above the active region of the semiconductor substrate. The capacitor may be a storage capacitor with increased capacitance fabricated within a memory cell structure of decreased dimensions.

Abstract: A semiconductor memory device is provided which prevents a lifting phenomenon by improving an adhesive strength between an upper electrode and an interlayer insulating layer. The semiconductor memory device includes a capacitor formed on a semiconductor substrate, wherein the capacitor includes a lower electrode, a dielectric layer and an upper electrode; an adhesion layer formed on the upper electrode; an interlayer insulating layer covering the capacitor, wherein a portion of the interlayer insulating layer is in contact with the adhesion layer; and a contact hole, formed within the interlayer insulating layer, whose bottom exposes the upper electrode and whose sidewalls expose the interlayer insulating layer and the adhesion layer.

Abstract: Within metal interconnect layers above a substrate of an integrated circuit, a vertical metal-insulator-metal (VMIM) capacitor is formed by the same damascene metallization types of processes that formed the metal interconnect layers. The metal interconnect layers have horizontal metal conductor lines, are vertically separated from other metal interconnect layers by an interlayer dielectric (ILD) layer, and electrically connect to the other metal interconnect layers through via connections extending through the ILD layer. One vertical capacitor plate of the VMIM capacitor is defined by a metal conductor line and a via connection. The other vertical capacitor plate is defined by a metal region adjacent to the metal conductor line and the via connection. The metal conductor line, the via connection and the metal region are formed by the damascene metallization processes.

Abstract: Method and apparatus are disclosed for protection of a circuit against process-induced electrical discharge. The method includes forming a diode in close proximity to a charge collector structure capable of exhibiting the antenna effect, and connecting the diode to the charge collector structure by means of local interconnect techniques during the intermediate processing steps. Additionally, the diode may be formed beneath a connecting pad to educe or eliminate antenna effect problems without significant loss of a die area.

Abstract: A method for manufacturing contacts for a Chalcogenide memory device is disclosed. A via is initially formed within a first oxide layer on a substrate. A conductive layer is then deposited on top of the first oxide layer. A second oxide layer is deposited on the conductive layer. Subsequently, the second oxide layer and the conductive layer are then removed such that the remaining portion of conductive layer within the via flushes with a surface of the first oxide layer. A third oxide layer is deposited on the conductive layer, and the first and second oxide layers. A pattern is formed to remove third layer so that the pattern opens orthgonally across and exposes the conductive layer. Next, a nitride layer is deposited on the third oxide layer, the conductive layer, and the first and second oxide layers. The nitride layer conforms with the contour of the third oxide layer.

Abstract: A trench capacitor with an expanded area for use in a memory cell and a method for making the same are provided. The trench capacitor includes a vertical trench formed in a semiconductor, a doping region formed around a low portion of the trench, a collar isolation layer formed on an inner sidewall of an upper portion of the trench, a doped silicon liner layer formed on a surface of the collar isolation layer, wherein the doped silicon liner layer is electrically connected to the doping region, a dielectric layer formed on a surface of the doped silicon liner layer and inner sidewall of the lower portion of the trench, and a doped silicon material formed inside the trench.

Abstract: Processing of a DRAM device containing vertical MOSFET arrays proceeds through planarization of the array gate conductor (GC) polysilicon of the vertical MOSFET to the top surface of the top oxide. A thin polysilicon layer is deposited over the planarized surface and an active area (M) pad nitride and tetraethyl orthosilicate (TEOS) stack is deposited. The M mask is used to open the pad layer to the silicon surface, and shallow trench isolation (STI) etching is used to form isolation trenches. An AA oxidation is performed, the isolation trenches are filled with high density plasma (HDP) oxide and planarized to the top surface of the AA pad nitride. Following isolation trench (IT) planarization, the AA pad nitride is stripped, with the thin silicon layer serving as an etch stop protecting the underlying top oxide. The etch support (ES) nitride liner is deposited, and the ES mask is patterned to open the support areas. The ES nitride, thin polysilicon layer and top oxide are etched from the exposed areas.

Abstract: A trench is formed in a substrate with an upper region and a lower region. The trench is subsequently widened in its upper region and in its lower region by isotropic etching. In the upper region, an insulating collar is formed that is designated as a buried insulating collar due to the widened trench. The insulating collar is removed in the vicinity of the surface of the substrate, through which the substrate is exposed in this region. Here, a selective epitaxial layer is subsequently grown in the trench, through which a subsequently formed selection transistor can be formed in perpendicular fashion over the trench, or very close to the trench. In addition, through the widened trench the electrode surface of the capacitor electrodes is enlarged, which ensures an increased storage capacity.

Abstract: The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.

Abstract: A method of manufacturing a capacitor of a semiconductor device. In order to reduce a vertical etching profile at a lower portion of a hole where a charge storage electrode, an impurity is doped into the interlayer insulating film wherein the difference in concentration of the impurity at a lower portion and at an upper portion of the interlayer insulating film is controlled to make the etching rate at the lower portion of the interlayer insulating film faster than that at the upper portion of the interlayer insulating film using a wet etching process. Therefore, the region where a lower electrode will be formed has a maximum width to prevent a decrease in the capacitance of the capacitor.

Abstract: A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.

Abstract: A method of using at least two insulative layers to form the isolation collar of a trench device, and the device formed therefrom. The first layer is preferably an oxide (e.g., silicon dioxide 116) formed on the trench substrate sidewalls, and is formed through a TEOS, LOCOS, or combined TEOS/LOCOS process. Preferably, both the TEOS process and the LOCOS process are used to form the first layer. The second layer is preferably a silicon nitride layer (114) formed on the oxide layer. The multiple layers function as an isolation collar stack for the trench. The dopant penetration barrier properties of the second layer permit the dielectric collar stack to be used as a self aligned mask for subsequent buried plate (120) doping.

Abstract: A contact structure in a semiconductor device and a method of forming the same are provided. The contact structure includes a lower interconnection having a capacitor upper electrode of memory cells; an interlayer dielectric layer formed on the lower interconnection and having a contact hole that exposes a portion of the lower interconnection; and an upper interconnection formed on the interlayer dielectric layer and electrically connected to the lower interconnection through the contact hole. The lower portion of the lower interconnection has a larger width than the bottom of the contact hole and extends downward or below the bottom of the contact hole so that the lower interconnection has a T-shape in cross-section. With these structures, the lower interconnection can be prevented from being pierced when the contact holes are formed. Consequently, stable and uniform contact resistance can be obtained.

Abstract: A memory cell structure for a folded bit line memory array of a dynamic random access memory device includes buried bit and word lines, with the access transistors being formed as a vertical structure on the bit lines. Isolation trenches extend orthogonally to the bit lines between the access transistors of adjacent memory cells, and a pair of word lines are located in each of the isolation trenches. The word lines are oriented vertically widthwise in the trench and are adapted to gate alternate access transistors, so that both an active and a passing word line can be contained within each memory cell to provide a folded bit line architecture. The memory cell has a surface area that is approximately 4 F2, where F is a minimum feature size. Also disclosed are processes for fabricating the DRAM cell using bulk silicon or a silicon on insulator processing techniques.

Abstract: A method and apparatus for forming a metal-insulator-metal structure on a copper damascene, including a semiconductor device thereof. A copper layer may be initially deposited upon a substrate to form a copper damascene, wherein the copper layer forms a metal layer of a metal-insulator-structure. A barrier layer may then be formed upon the substrate following deposition of the copper layer upon the substrate. Thereafter, the copper layer can be polished utilizing chemical mechanical polishing (CMP) to provide enhanced uniformity of the copper layer, thereby producing a well-controlled metal-insulator-metal structure upon the substrate. The barrier layer formed upon the substrate following deposition of the copper layer may be configured as an in-situ metal barrier. Such an in-situ metal barrier layer may be formed, for example, from tantalum nitride (TaN). The barrier layer may alternatively be configured as a dielectric barrier configured, for example, from NH3 plasma in combination with SiN.

Abstract: The present invention provides a method of preparing a surface of a silicon wafer for formation of HSG structures. The method contemplates providing a wafer having at least one HSG template comprising polysilicon formed in BPSG, the HSG template being covered by silicon dioxide. The wafer is treated with a cleaning agent to clean the surface of the wafer. Next, the wafer is treated with a conditioning agent. The conditioning agent removes native oxide from the HSG template without excessively etching structural BPSG. Preferably, the conditioning agent also removes a thin layer of polysilicon on the HSG template. The wafer is then transferred to a process chamber for HSG formation.

Abstract: An aluminum interconnect which extends adjacent to and is insulated from a stacked capacitor structure to facilitate electrical communication between an active device region of a semiconductor substrate of a semiconductor device structure and a bit line extending above the semiconductor substrate. The aluminum interconnect is disposed within a trench and may include a metal silicide layer adjacent the active device region to form a buried metal diffusion layer. The aluminum interconnect may also include a metal nitride layer disposed between the metal silicide and aluminum. The invention also includes methods of fabricating aluminium interconnects adjacent stacked capacitor structures and semiconductor device structures which include the aluminum interconnects.

Abstract: A process for forming a sacrificial collar (116) on the top portion of a deep trench (114). A nitride layer (116) is deposited within the trench (114). A semiconductor layer (120) is deposited over the nitride layer (116). A top portion of the semiconductor layer (120) is doped to form doped semiconductor layer (124). Undoped portions (120) of the semiconductor layer are removed, and the doped semiconductor layer (124) is used to pattern the nitride layer (116), removing the lower portion of nitride layer (116) from within deep trenches (114) and leaving a sacrificial collar (116) at the top of the trenches (114).

Abstract: The memory-storage node of the present invention includes a semiconductor substrate, a first insulating layer over the substrate, a conductive layer formed within the first insulating layer, and a barrier layer formed over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. The memory-storage node further includes a first electrode over the barrier layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The method for fabricating the memory storage-node of the present invention provides a semiconductor substrate and forms a first insulating layer on the substrate. A first opening is formed in the first insulating layer and a conductive layer is provided in the first opening. A barrier layer is then formed in the first opening and over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer.

Abstract: A method for fabricating a trench capacitor, that includes steps of: providing a silicon substrate; forming a trench, having a lower region and a surface, in the silicon substrate; and forming a doped layer in the silicon substrate in the lower region of the trench. In addition, a roughened silicon layer that has silicon grains with a diameter ranging from essentially 10 to 100 nm is produced in the lower region of the trench. A dielectric intermediate layer is applied on the roughened silicon layer, and the trench is filled with a doped layer.

Abstract: An electropolishing process for high resolution patterning of noble metals, such as platinum, for forming various semiconductor devices, such as capacitors or wiring patterns is disclosed.

Abstract: A capacitor having a double sided electrode for enhanced capacitance. In one embodiment, the double sided electrode capacitor is a stacked container capacitor used in a dynamic random access memory circuit. The double sided electrode is preferably formed of a conductive metal, provided that an oxide of the metal is conductive. The double sided electrode capacitor provides a capacitor that has high storage capacitance which provides an increased efficiency for a cell without an increase in the size of the cell.

Abstract: A capacitor having sufficient capacity without increased step difference between a memory cell portion and surrounding area. Silicon dioxide, silicon nitride, and a resist are layered on an underlying layer. Capacitor opening patterns limited in size by photolithography resolution, are formed in the resist and silicon nitride by photolithography. The patterned silicon nitride acts as a mask and a pocket with an aperture greater than the capacitor pattern is formed in the silicon dioxide by isotropic etching. Conductive polysilicon is formed on the wall of the pocket and is patterned to form a storage electrode. After a capacitor insulator is formed on the storage electrode, a cell plate electrode is formed to provide a capacitor structure. The aperture area of the storage electrode is made larger than the area of the capacitor pattern based on the thickness of the conductive polysilicon.

Abstract: An integrated ferroelectric memory configuration and a method for producing the integrated ferroelectric memory configuration, in which memory cells are arranged using the stacking principle, and both capacitor electrodes, which are located one above the other, of each memory cell are directly electrically connected by means of contact plugs to corresponding source and drain regions of an associated selection transistor in the substrate. Contact plugs for the contact connection to the upper capacitor electrodes are produced from above the configuration.

Abstract: In a method for forming an array of dynamic random access memory (DRAM) cells, each DRAM cell having one or more field effect transistors (FETs) and a deep trench capacitor, first, a substrate is prepared. Line type active areas (AAs) are patterned on the substrate to thereby provide AA lines (AALs). Next, deep trench capacitors (DTCs) are fabricated in an AAL in a predetermined configuration to thereby define deep trench areas (DTAs) for the DTCs, each DTC having a storage node, a collar insulator and a buried strap. In subsequent step, a node isolation area (NIA) is defined to isolate a storage node of a DTC and a storage node of its adjacent DTC and then a trench isolation area (TIA) for each of the DRAM cell is defined. Further, one or more FETs are fabricated in each AA to thereby form the array of DRAM cells, wherein a conductive path is formed from an electrode of one of the FETs to the buried strap of a corresponding DTC.

Abstract: An integrated circuit capacitor containing a thin film of dielectric metal oxide is formed above a silicon germanium substrate. A silicon nitride diffusion barrier layer is deposited on a silicon germanium substrate to prevent evaporation of the substrate in subsequent heating steps. A silicon dioxide stress reduction layer is deposited on the diffusion barrier layer. A bottom electrode is formed on the stress reduction layer, then a liquid precursor is spun on the bottom electrode, dried at about 400° C., and annealed at between 600° C. and 850° C. to form a BST capacitor dielectric. A top electrode is deposited on the dielectric and annealed. The integrated circuit may also include a BiCMOS device, a HBT device or a MOSFET.

Abstract: The invention includes methods of forming capacitors on a wafer, photolithographic methods of forming capacitors on a wafer, and to semiconductor wafers regardless of the method of fabrication. In one implementation, A method of forming capacitors on a wafer includes forming a dielectric well forming layer over the wafer. A protective rim is formed over the well forming layer proximate to and along at least a portion of the wafer's peripheral edge. Portions of the well forming layer are removed radially inward of the protective rim to form a plurality of wells within the well forming layer. A plurality of capacitors are formed within individual of the plurality of wells. One implementation includes a semiconductor wafer.

Abstract: The memory cell has a trench in which a capacitor is formed. Furthermore, a vertical transistor is formed in the trench, above the trench capacitor. The doping regions of the vertical transistor are arranged in the substrate. In order to connect the gate electrode of the vertical transistor to a word line, a dielectric layer having an inner opening is arranged in the trench, above the gate electrode. The dielectric layer is configured as lateral edge webs which project beyond the cross section of the trench and thus cover part of the substrate. The lateral edge webs enable self-aligned formation of an isolation trench.

Abstract: A deep trench capacitor, in accordance with the present invention, includes a deep trench formed in a substrate having a storage node formed therein. A center node is capacitively coupled to the storage node. The center node is disposed within the deep trench and formed inside the storage node. A first buried strap is provided for accessing the storage node, and a second buried strap is electrically isolated from the storage node and formed in contact with the center node and a buried plate. The center node is formed to provide additional capacitive area to the deep trench capacitor. A method for forming the deep trench capacitor in accordance with the present invention is also provided.

Abstract: A process for fabricating a fin type, cylindrical shaped, DRAM capacitor structure, with increased surface area, has been developed. The process features forming a non-continuous layer of discrete regions of silicon, on the surface of a capacitor opening, in a composite insulator layer. The discrete regions of silicon are then used as an etch mask to allow an isotropic etching procedure to create horizontal channels in the sides of the portions of the composite insulator layer exposed in the capacitor opening, creating a capacitor opening comprised with horizontal channnels. An amorphous silicon layer is then deposited and patterned to form a fin type, storage node structure, comprised of amorphous silicon on discrete regions of silicon, in the capacitor opening. Formation of a capacitor dielectric layer, and an overlying top electrode structure, complete the formation of a fin type, cylindrical shaped, DRAM capacitor structure.

Abstract: The present invention is directed to a method for fabricating a capacitor in a semiconductor device. The capacitor uses a Ta2O5 film as a dielectric film. The method for fabrication can include forming a nitride film on a capacitor lower electrode by a rapid thermal nitration process, and depositing the Ta2O5 film on the nitride film and heat treating using a rapid thermal process including N2O gas to form an SiON film at an interface between the capacitor lower electrode and the Ta2O5 film. A capacitor upper electrode is then formed on the Ta2O5 film. The method according to the present invention can reduce a device deterioration, improve leakage current characteristics and increase a device reliability.

Abstract: Structure and method for fabrication of an improved capacitor are disclosed. In one embodiment, the disclosed capacitor includes a metal column comprising a number of interconnect metal segments and a number of via metal segments stacked on one another. The metal column constitutes one electrode of the capacitor. Another electrode of the capacitor is a metal wall surrounding the metal column. In one embodiment, the metal wall is fabricated from a number of interconnect metal structures and a number of via metal structures stacked on one another. In one embodiment, the metal wall is shaped as a hexagon. In this embodiment, a tight packing arrangement is achieved by packing individual hexagonal capacitors “wall to wall” so as to achieve a cluster of individual hexagonal capacitors. The cluster of individual capacitors acts as a single composite capacitor. In one embodiment, the interconnect metal and via metal are both made of copper.

Abstract: A semiconductor device manufacturing method for silicidizing silicon-containing areas in array regions of dynamic random access memory (DRAMS)and embedded DRAM (eDRAM) devices to lower electrical resistance, and improve device reliability at low temperatures.

Abstract: A method for manufacturing a conductive strip includes forming a doped dielectric layer along a surface of a trench. Then, an ion-implanted-sensitive resist is formed over the doped dielectric layer. Next step is to implant ions into the ion-implanted-sensitive resist by substantially vertical implantation such that the ion-implanted-sensitive resist over the lower and upper horizontal surfaces is insoluble portions in a developer and the vertical surface is soluble in the developer. Subsequently, the vertical surface is removed by using the developer and then the doped dielectric layer attached on the vertical surface is also removed. Then, a CMP process is used to remove the ion-implanted-sensitive resist and the doped dielectric layer. Next, a thermal treatment is used to diffuse the dopants in the doped dielectric layer into the lower horizontal surface.

Abstract: Provided is a semiconductor memory device in which defective contact, deterioration in transistor characteristics and other problems are solved with a thermally stable, conductive diffusion barrier layer against oxygen, and against constituent elements in a plug material and a lower electrode, formed at the interface between a plug and the lower electrode made of a noble metal. The semiconductor memory device comprises a dielectric capacitor of a stacked structure including a first electrode (a lower electrode), a dielectric film and a second electrode (an upper electrode) and a conductive plug connected to the lower electrode, wherein the lower electrode connected to the conductive plug includes a metal suboxide layer with conductiveness and a diffusion barrier layer blocking diffusion of oxygen, and the metal suboxide layer and the diffusion barrier layer are stacked in the order from the conductive plug side of the lower electrode.

Abstract: The present invention provides a method for forming a substantially carbon- and oxygen-free conductive layer, wherein the layer can contain a metal and/or a metalloid material. According to the present invention, a substantially carbon- and oxygen-free conductive layer is formed in an oxidizing atmosphere in the presence of an organometallic catalyst using, for example, a chemical vapor deposition process. Such layers are particularly advantageous for use in memory devices, such as dynamic random access memory (DRAM) devices.

Abstract: The present invention provides a method for fabricating a DRAM cell having a trench capacitor. In order to simplify the fabrication method for a DRAM cell, to ensure a high yield and to achieve a high packing density of the DRAM cells, the invention proposes that the storage capacitor (4) of the DRAM cell and the selection transistor (3) be fabricated independently of one another. This saves method steps which, in the prior art, have to be carried out in order to isolate capacitor (9) and gate (16) in the same trench.

Abstract: There is provided a semiconductor device having a ferroelectric capacitor formed on a semiconductor substrate covered with an insulator film, wherein the ferroelectric capacitor comprises: a bottom electrode formed on the insulator film; a ferroelectric film formed on the bottom electrode; and a top electrode formed on the ferroelectric film. The ferroelectric film has a stacked structure of either of two-layer-ferroelectric film or three-layer-ferroelectric film. The upper ferroelectric film is metallized and prevents hydrogen from diffusing in lower ferroelectric layer. Crystal grains of the stacked ferroelectric films are preferably different.

Abstract: A semiconductor device includes a capacitor having a lower electrode (102), a high-dielectric-constant or ferroelectric thin film (103), and an upper electrode (104) which are subsequently stacked. An impurity having an action of suppressing the catalytic activity of a metal or a conductive oxide constituting the electrode is added to the upper electrode (104). The addition of the impurity is effective to prevent inconveniences such as a reduction in capacitance, an insulation failure, and the peeling of the electrode due to hydrogen heat-treatment performed after formation of the upper electrode (104), and to improve the long-term reliability.

Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.

Abstract: A DRAM cell (10) having a capacitor-over-bit line (COB) structure self-aligned to the word lines and bit lines is disclosed. Word lines (24) and bit lines (28) are formed with insulating structures that include insulating sidewalls. The word line insulating structure includes an etch barrier layer (46) that extends over a source region (18). A first interlayer dielectric (ILD) (48) insulates the word lines (24) from the bit lines (28) and a second ILD (60) insulates the bit lines from a cell capacitor. A capacitor contact hole (34), self-aligned with the bit lines and the word lines, is formed by etching through the first and second ILDs (48 and 60) to expose the etch barrier layer (46) over the source region (18). Portions of the bit line and word line exposed by the etch are protected by their respective insulating structures.