Abstract: The present invention relates to a method for depositing a dielectric material comprising a transition metal compound. After providing a substrate, a first pre-cursor comprising a transition metal compound and a second pre-cursor predominantly comprising at least one of water vapour, ammonia and hydrazine are successively applied on the substrate for forming a first layer of transition metal containing material. In a next step the first pre-cursor and a third pre-cursor comprising at least one of ozone and oxygen are successively applied on the first layer for forming a second layer of the transition metal containing material.

Abstract: A method for manufacturing a semiconductor device includes forming a first interlayer insulating film over a semiconductor substrate; forming a first opening in the first interlayer insulating film; forming a second interlayer insulating film on the first interlayer insulating film such that the first opening is not filled; and forming a second opening in the second interlayer insulating film such that the second opening is connected to the first opening.

Abstract: An on-chip bypass capacitor and method of manufacturing the same, the on-chip bypass capacitor including at least two capacitor arrays, each capacitor array including a first layer connecting the at least two capacitor arrays in series, each capacitor array including a plurality of capacitors, each of the plurality of capacitors including a second layer connecting the plurality of capacitors in parallel. The on-chip bypass capacitor may be part of a chip which also includes a memory cell array including at least one cell capacitor.

Abstract: Various on-chip capacitors and methods of making the same are disclosed. In one aspect, a method of manufacturing a capacitor is provided that includes forming a first conductor structure on a semiconductor chip and forming a passivation structure on the first conductor structure. An under bump metallization structure is formed on the passivation structure. The under bump metallization structure overlaps at least a portion of the first conductor structure to provide a capacitor.

Abstract: An electrostatic micromotor is provided with a fixed substrate, a mobile substrate facing the fixed substrate, and electrostatic-interaction elements enabling a relative movement of the mobile substrate with respect to the fixed substrate in a movement direction; the electrostatic micromotor is also provided with a capacitive position-sensing structure configured to enable sensing of a relative position of the mobile substrate with respect to the fixed substrate in the movement direction. The capacitive position-sensing structure is formed by sensing indentation, extending within the mobile substrate from a first surface thereof, and by first sensing electrode, facing, in given operating condition, the sensing indentation.

Abstract: Methods and apparatus for providing an integrated circuit including a substrate having a magnetic field sensor, first and second conductive layers generally parallel to the substrate, and a dielectric layer disposed between the first and second conductive layers such that the first and second conductive layers and the dielectric layer form a capacitor, wherein a slot is formed in at least one of the first and second conductive layers proximate the magnetic field sensor for reducing eddy currents in the first and second conductive layers.

Abstract: Provided herein are methods of forming a metal oxide layer that include providing an organometallic compound and an oxidizing agent to the substrate to form the metal oxide layer on the substrate. The organometallic compound may have the general formula of M(NR1R2)3R3, wherein M is a metal; R1 and R2 are each independently hydrogen or alkyl; and R3 is selected from the group consisting of alkyl, cycloalkyl, heterocycloalkyl, aryl and heteroaryl.

Abstract: A method of forming a capacitor includes forming a first capacitor electrode over a semiconductor substrate. A capacitor dielectric region is formed onto the first capacitor electrode. The capacitor dielectric region has an exposed oxide containing surface. The exposed oxide containing surface of the capacitor dielectric region is treated with at least one of a borane or a silane. A second capacitor electrode is deposited over the treated oxide containing surface. The second capacitor electrode has an inner metal surface contacting against the treated oxide containing surface. Other aspects and implementations are contemplated.

Abstract: A complementary metal-oxide-semiconductor (CMOS) static random-access-memory (SRAM) element comprising a planar metal-insulator-metal (MIM) capacitor is disclosed, and the planar MIM capacitor is electrically connected to the transistors in the CMOS memory element to reduce the effects of charged particle radiation on the CMOS memory element. Methods for immunizing a CMOS SRAM element to the effects of charged particle radiation are also disclosed, along with methods for manufacturing CMOS SRAM including planar MIM capacitors as integrated circuits.

Abstract: A parallel plate capacitor formed in the back end of an integrated circuit employs conductive capacitor plates that are formed simultaneously with the other interconnects on that level of the back end (having the same material, thickness, etc). The capacitor plates are set into the interlevel dielectric using the same process as the other interconnects on that level of the back end (preferably dual damascene). Some versions of the capacitors have perforations in the plates and vertical conductive members connecting all plates of the same polarity, thereby increasing reliability, saving space and increasing the capacitive density compared with solid plates.

Abstract: An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first conductive level including a first conductive trace over the substrate; forming a second conductive level spaced apart from the first conductive level and including a second conductive trace; and connecting the first conductive level to a third conductive level with a viabar that passes through the second conductive level without contacting the second conductive trace.

Abstract: A semiconductor device includes a ferroelectric capacitor formed over a semiconductor substrate, wherein the ferroelectric capacitor including a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film, and the upper electrode including a first conductive film formed of a first conductive noble metal oxide, and a second conductive film formed of a metal nitride compound formed on the first conductive film.

Abstract: A system and method are disclosed for processing an organic memory cell. An exemplary system can employ an enclosed processing chamber, a passive layer formation component operative to form a passive layer on a first electrode, and an organic semiconductor layer formation component operative to form an organic semiconductor layer on the passive layer. A wafer substrate is not needed to transfer from a passive layer formation system to an organic semiconductor layer formation system. The passive layer is not exposed to air after formation of the passive layer and before formation of the organic semiconductor layer. As a result, conductive impurities caused by the exposure to air do not occur in the thin film layer, thus improving productivity, quality, and reliability of organic memory devices. The system can further employ a second electrode formation component operative to form a second electrode on the organic semiconductor layer.

Abstract: A process of forming an electronic device can include forming a capacitor dielectric layer over a base region, wherein the base region includes a base semiconductor material, forming a gate dielectric layer over a substrate, forming a capacitor electrode over the capacitor dielectric layer, forming a gate electrode over the gate dielectric layer, and forming an input terminal and an output terminal to the capacitor electrode. The input terminal and the output terminal can be spaced apart from each other and are connected to different components within the electronic device. A filter can include the base region, the capacitor dielectric layer, and the capacitor electrode. A transistor structure can include the gate dielectric layer and the gate electrode. An electronic device can include a low-pass filter and a transistor structure, such as an n-channel transistor or a p-channel transistor.

Abstract: A method for manufacturing a capacitor of a semiconductor device includes forming a lower metal layer over a substrate, forming a dielectric layer over the lower metal layer, forming an upper metal layer over the dielectric layer, forming an upper electrode and a dielectric layer pattern by performing a reactive ion etching process with respect to the upper metal layer using the dielectric layer as an etch stop layer, and exposing a top surface of the lower metal layer, and performing a chemical down-stream etch (CDE) process to remove a by-product of a sidewall of the upper electrode.

Abstract: A non-volatile passive memory element comprising on a single surface a first electrode system and a second electrode system together with an insulating system, unless the insulating system is the surface, wherein the first electrode system is insulated from the second electrode system, the first and the second electrode systems are pattern systems and at least one conductive or semiconducting bridge is present between the first and second electrode systems, and wherein the non-volatile passive memory device is exclusive of metallic silicon and the systems and the conductive or semiconducting bridges are printable using conventional printing processes with the optional exception of the insulating system if the insulating system is the surface. A non-volatile passive memory device comprising a support and on at least one side of the support the above-mentioned non-volatile passive memory element.

Abstract: A method of producing a capacitor that includes producing a first electrode having a first surface; forming a recess in an element, walls of the element and the first surface of the first electrode defining the recess, the element having a first surface exterior of the recess; forming a dielectric layer on the element, the dielectric layer oriented against the first surface of the element and against the walls of the element within the recess; polishing off at least a portion of the dielectric layer oriented against the first surface of the element to electrically isolate the portion of the dielectric layer located in the recess from any portion of the dielectric layer remaining outside the recess; and producing a second electrode, the second electrode oriented at least partially within the recess with the dielectric layer oriented between the first electrode and the second electrode.

Abstract: The invention relates to a jig for producing capacitor elements, which is formed of resin material and is used for accommodate a plurality of capacitor element substrates therein to thereby batch-process the substrates. The jig is characterized in that portions of the jig at which the jig is supported during the process are protected with metal material. According to the invention, a group of capacitors each having a semiconductor layer serving as one electrode can be simultaneously produced with narrow variety in capacitance and with good precision, repeatedly, by using the jig having a high durability.

Abstract: A Metal-Insulator-Metal (MIM) capacitor structure and method of fabricating the same in an integrated circuit improve capacitance density in a MIM capacitor structure by utilizing a sidewall spacer extending along a channel defined between a pair of legs that define portions of the MIM capacitor structure. Each of the legs includes top and bottom electrodes and an insulator layer interposed therebetween, as well as a sidewall that faces the channel. The sidewall spacer incorporates a conductive layer and an insulator layer interposed between the conductive layer and the sidewall of one of the legs, and the conductive layer of the sidewall spacer is physically separated from the top electrode of the MIM capacitor structure. In addition, the bottom electrode of a MIM capacitor structure may be ammonia plasma treated prior to deposition of an insulator layer thereover to reduce oxidation of the electrode.

Abstract: A semiconductor memory device includes a memory cell portion and a peripheral circuit portion. The memory cell portion includes a pillar capacitor with a lower electrode, a dielectric film, and an upper electrode sequentially formed on a side surface of a first insulating portion which is parallel to a predetermined direction, and a transistor electrically connected to the lower electrode. The peripheral circuit portion includes a plate electrode, a cylinder capacitor with an upper electrode, a dielectric film, and a lower electrode sequentially formed on a side surface of the plate electrode which is parallel to the predetermined direction, and a transistor electrically connected to the lower electrode.

Abstract: A method of making a metal-metal capacitor is disclosed, in which a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer, and a third metal layer are formed in the order over a substrate; an upper capacitor is defined by etching using a first mask, wherein the stop of the etching can be controlled; a lower capacitor is defined by etching using a second mask; and an anti-reflective third mask is formed to cover the surface, and the capacitor border and metal interconnect conductive wire are defined, so as to make a metal-metal capacitor with a stable structure in a wide process window.

Abstract: A method of forming one or more capacitors on or in a substrate and a capacitor structure resulting therefrom is disclosed. The method includes forming a trench in the substrate, lining the trench with a first copper-barrier layer, and substantially filling the trench with a first copper layer. The first copper layer is substantially chemically isolated from the substrate by the first copper-barrier layer. A second copper-barrier layer is formed over the first copper layer and a first dielectric layer is formed over the second copper-barrier layer. The dielectric layer is substantially chemically isolated from the first copper layer by the second copper-barrier layer. A third copper-barrier layer is formed over the dielectric layer and a second copper layer is formed over the third copper-barrier layer. The second copper layer is formed in a non-damascene process.

Abstract: Disclosed is a metal capacitor including a lower electrode having hemispherical metal grains thereon. The metal capacitor includes a lower metal electrode containing Ti, hemispherical metal grains containing Pd and formed on the lower metal electrode containing Ti, a dielectric layer formed on the lower metal electrode containing Ti and the hemispherical metal grains containing Pd, and an upper metal electrode formed on the dielectric layer.

Abstract: A semiconductor device having a plurality of layers and a capacitor array that includes a plurality of individual capacitors. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections and capacitances of the plurality of individual capacitors in the capacitor array. The semiconductor device may include a metal structure disposed within the device to provide an electromagnetic shield for at least one of the plurality of individual capacitors in the capacitor array.

Abstract: The invention provides a method of manufacturing a porous anode for a solid electrolytic capacitor, comprising a step of subjecting a molded body containing powder of at least one material selected from oxygen-containing niobium material and oxygen-containing tantalum material and a pore-forming agent which is solid at reduction temperature to reduction reaction using reducing agent and another step of removing the pore-forming agent from the reduction reaction product and a solid electrolytic capacitor using an anode obtained thereby. As niobium material and tantalum material, at least one material selected from niobium, niobium alloy, niobium compound, tantalum, tantalum alloy and tantalum compound is used respectively.

Abstract: According to one aspect of the present invention, a method of forming a microelectronic assembly, such as an integrated passive device (72), is provided. An insulating initial dielectric layer (32) comprising charge trapping films of, for example, aluminum nitride or silicon nitride or silicon oxide or a combination thereof, is formed over a silicon substrate (20). At least one passive electronic component (62) is formed over the initial dielectric layer (32). In an embodiment where silicon nitride or oxide is used in the initial dielectric layer (32) in contact with the silicon substrate (20), it is desirable to pre-treat the silicon surface (22) by exposing it to a surface damage causing treatment (e.g. an argon plasma) prior to depositing the initial dielectric layer, to assist in providing carrier depletion near the silicon surface around zero bias. RF loss in integrated passive devices using such silicon substrates is equal or lower than that obtained with GaAs substrates.

Abstract: A tuneable capacitor arrangement for RF use has two series coupled MEMS variable capacitors (C1,C2;C4,C5,C6,C7), varied according to a control signal. The series coupling enables the capacitor to withstand a higher voltage since this is shared by the individual capacitors in a series coupled arrangement. An increase in size of electrodes for each capacitor is compensated by a reduction in size of the springs supporting movable electrodes. These springs can have a larger stiffness value since the capacitance is larger. This means shorter springs, which can also result in a reduction in problems of stiction, resistance, and slow switching. The capacitances have a fixed and a movable electrode, with the RF signal coupled to the fixed electrode to avoid the springs needing to carry an RF signal. This can reduce the problems of inductance and resistance in the springs.

Abstract: There is provided a semiconductor device which includes a base insulating film formed on a semiconductor substrate, a capacitor formed on the base insulating film, an interlayer insulating film covering the capacitor, a first layer metal wiring formed on the interlayer insulating film, a single-layer first insulating film which covers the interlayer insulating film and the first layer metal wiring and has a first film thickness above the first layer metal wiring, a first capacitor protective insulating film formed on the first insulating film, a first cover insulating film which is formed on the first capacitor protective insulating film and has a second film thickness thicker than the first film thickness, above the first layer metal wiring, a third hole formed in the insulating films on the first layer metal wiring, and a fifth conductive plug formed in the third hole.

Abstract: Structures and methods of forming an ideal MIM capacitor are disclosed. The single capacitor includes a first and a second metal structure overlying a substrate, a first dielectric material disposed between a first portion of the first metal structure and a first portion of the second metal structure. A second dielectric material is disposed between a second portion of the first metal structure and a second portion of the second metal structure. No first dielectric material is disposed between the second portion of the first and second metal structures, and no second dielectric material is disposed between the first portion of the first and second metal structures. The first and second dielectric material layers include materials with opposite coefficient of capacitance.

Abstract: The invention relates to a method for producing a solid electrolytic capacitor, in which a dielectric oxide film, a semiconductor layer and an electrode layer are sequentially formed on a rectangular parallelepiped sintered body of conductive powder having an anode lead implanted in one face and then the whole is encapsulated with jacketing resin, the method comprising providing an insulating plate of almost the same shape with the face having the anode lead implanted therein in parallel with and 200 ?m or less apart from the face, and a solid electrolytic capacitor produced by the method.

Abstract: The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention achieves a capacitor that minimizes capacitance tolerance and preserves symmetry in parasitic electrode-substrate capacitive coupling, without adversely affecting other interconnects and via contacts formed in the same wiring level, through the use of, at most, one additional noncritical, photomask.

Abstract: A semiconductor structure and a method for forming the same. The structure includes (i) a dielectric layer, (ii) a bottom capacitor plate and an electrically conductive line on the dielectric layer, (iii) a top capacitor plate on top of the bottom capacitor plate, (iv) a gap region, and (v) a solder ball on the dielectric layer. The dielectric layer includes a top surface that defines a reference direction perpendicular to the top surface. The top capacitor plate overlaps the bottom capacitor plate in the reference direction. The gap region is sandwiched between the bottom capacitor plate and the top capacitor plate. The gap region does not include any liquid or solid material. The solder ball is electrically connected to the electrically conductive line. The top capacitor plate is disposed between the dielectric layer and the solder ball.

Abstract: An integrated metal-insulator-metal capacitor is formed so that there is an extension portion of its top plate that does not face any portion of the bottom plate, and an extension portion of its bottom plate that does not face any portion of the top plate. Vias connecting the MIM capacitor plates to conductors in an overlying metallization layer are formed so as to contact the extension portions of the top and bottom plates. Etching of the via holes is simplified because it is permissible for the via holes to punch through the extension portions of the capacitor plates. The bottom plate of the MIM capacitor is inlaid. The top plate of the MIM capacitor may be inlaid.

Abstract: An embodiment generally relates a method of forming capacitors. The method includes forming a plurality of holes within a protective overcoat or backend dielectric layer of an integrated circuit and depositing multiple layers of metal, each layer of metal electrically tied to an associated electrode. The method also includes alternately depositing multiple layers of dielectric between the multiple layers of metal and coupling a bottom layer of the multiple layers of metal to a contact node in a top metal layer of the integrated circuit.

Abstract: The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.

Abstract: By forming metal capacitors in the metallization structures of semiconductor devices, complex manufacturing sequences in the device level may be avoided. The process of manufacturing the metal capacitors may be performed on the basis of well-established patterning regimes of modern metallization systems by using appropriately selected etch stop materials, which may enable a high degree of compatibility for forming via openings in a metallization layer while providing a capacitor dielectric of a desired high dielectric constant in the capacitor.

Abstract: Methods of making MIM structures and the resultant MIM structures are provided. The method involves forming a top electrode layer over a bottom electrode and an insulator on a substrate and forming a top electrode by removing portions of the top electrode layer. The bottom electrode, insulator, or combination thereof is isolated from the top electrode forming process, thereby mitigating damage to the resultant metal-insulator-metal structure. The resultant MIM structure can be a portion of a resistive memory cell.

Abstract: The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device region; forming caps made of one or more layers of a cap material over said plurality of gate stacks in said memory cell region and over said at least one gate stack in said peripheral device region; depositing a first protective layer made of carbon or made of a carbon containing material over said memory cell region and peripheral device region; forming a mask layer on said first protective layer in said memory cell region; exposing said cap of said at least one gate stack in said peripheral device region by removing said first protective layer in said peripheral device region in an etch step wherein said mask layer acts as a mask in said memory cell region; removing said mask layer and said first protective layer from said memory cell region; for

Abstract: A manufacturing process for a capacitor in an interconnection layer includes the following stages: Deposit of a first metallic layer (21); Deposit of a first insulator layer (31) on the first metallic layer (21); Deposit of a second metallic layer (41) on the first insulator layer (31); Formation of an upper electrode (4) in the second layer metallic (41); Deposit of a second insulator layer (13) covering the upper electrode (4); Etching of the second insulator layer to form a spacer (14) on this first insulator layer surrounding the upper electrode (4); then Formation of a lower electrode (2) and a dielectric (3) by removal of parts from the first metallic layer and insulator not covered by the upper electrode (4) or the spacer (14); and Formation of an interconnection line (5). This process allows for manufacturing capacitors with an increased performance, in a simplified fashion at lower cost and with an auto-alignment.

Abstract: Integrated circuit devices including metal-insulator-metal (MIM) capacitors are provided. The MIM capacitors may include an upper electrode having first and second layers. The first layer of the upper electrode includes a physical vapor deposition (PVD) upper electrode and the second layer of the upper electrode includes an ionized PVD (IPVD) upper electrode on the PVD upper electrode. Related methods are also provided.

Abstract: A printed circuit board having embedded capacitors includes a double-sided copper-clad laminate including first circuit layers formed in the outer layers thereof, the first circuit layers including bottom electrodes and circuit patterns; dielectric layers formed by depositing alumina films on the first circuit layers by atomic layer deposition; second circuit layers formed on the dielectric layers and including top electrodes and circuit patterns; one-sided copper-clad laminates formed on the second circuit layers; blind via-holes and through-holes formed in predetermined portions of the one-sided copper-clad laminates; and plating layers formed in the blind via-holes and the through-holes. The manufacturing method of the printed circuit board is also disclosed.

Abstract: Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

Abstract: In a capacitor and a capacitor array configured for reducing an effect of parasitic capacitance, the capacitor array can have a matrix configuration that includes a plurality of unit capacitors. The unit capacitors include a lower electrode and an upper electrode that constitute a plate capacitor, as well as shielding structures which enclose the capacitor. The unit capacitors are connected by an upper electrode connecting line with a first direction to constitute a plurality of capacitor columns, wherein the unit capacitors are also arranged in rows, in a second direction perpendicular to the first direction, and wherein lower electrode lead lines are disposed between the capacitor columns, the lower electrode lead lines being connected to the respective lower electrodes of each of the unit capacitors.

Abstract: Method (200) and apparatus (30, 50-53) are described for MOS capacitors (MOS CAPs). The apparatus (30, 50-53) comprises a substrate (31) having Ohmically coupled N and P semiconductor regions (32, 34; 54, 56; 92, 94) covered by a dielectric (35, 57, 95). A conductive electrode (36, 58, 96) overlies the dielectric (35, 57, 95) above these N and P regions (32, 34; 54, 56; 92, 94). Use of the Ohmically coupled N and P regions (32, 34; 54, 56; 92, 94) substantially reduces the variation (40, 64, 70, 80) of capacitance with applied voltage associated with ordinary MOS CAPs. When these N and P regions (32, 34; 54, 56; 92, 94) have unequal doping, the capacitance variation (40, 64, 70, 80) may still be substantially compensated by adjusting the properties of the dielectric (57, 95) above the N and P regions (54, 56; 92, 94) and/or relative areas of the N and P regions (54, 56; 92, 94) or both.

Abstract: A microelectronic device, a method of fabricating the device, and a system including the device. The method includes: providing a substrate including an underlying conductive layer and a polymer build-up layer overlying the underlying conductive layer; providing a passive microelectronic structure; embedding the passive structure in the polymer build-up layer of the substrate; and patterning the passive structure after embedding, patterning including over-etching the bottom electrode layer. The passive microelectronic structure being embedded includes an unpatterned bottom electrode layer; an unpatterned capacitor dielectric layer overlying the bottom electrode layer; and an unpatterned top electrode layer overlying the capacitor dielectric layer.

Abstract: A method for fabricating a metal/insulator/metal (MIM) structure capacitor includes forming a nitride film that is an insulating layer on a bottom electrode metal layer; forming titanium/titanium nitride (Ti/TiN) that is a top electrode metal layer on the nitride film; coating photo-resist on the top electrode metal layer and patterning a photo-resist layer; selectively etching the top metal electrode layer so that the nitride film remains using the patterned photo-resist layer as an etching mask and using the nitride film as an end point; and removing the remaining nitride film.

Abstract: Provided is a capacitor for a semiconductor device. The capacitor comprises a bottom electrode, a dielectric pattern, and a top electrode. The bottom electrode has an uneven surface. The dielectric pattern is on the bottom electrode, and the top electrode is on the dielectric pattern. The bottom electrode has a first height in edge and center regions thereof, and a protrusion between the edge region and the center region of the bottom electrode having a second height greater than the first height.

Abstract: A semiconductor device includes: a lower hydrogen-barrier film; a capacitor formed on the lower hydrogen-barrier film and including a lower electrode, a capacitive insulating film, and an upper electrode; an interlayer dielectric film formed so as to cover the periphery of the capacitor; and an upper hydrogen-barrier film covering the top and lateral portions of the capacitor. An opening, which exposes the lower hydrogen-barrier film where the lower hydrogen-barrier film is located around the capacitor, and which is tapered and flares upward, is formed in the interlayer dielectric film, and the upper hydrogen-barrier film is formed along the lateral and bottom faces of the opening, and is in contact with the lower hydrogen-barrier film in the opening.

Abstract: The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium oxide (HfO2) doped with dysprosium (Dy) and a method of fabricating such a combination gate and dielectric layer produces a reliable structure for use in a variety of electronic devices. Forming the dielectric structure includes depositing hafnium oxide using atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing dysprosium oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure.

Abstract: A method for manufacturing a metal-insulator-metal capacitor of a semiconductor device method for manufacturing a semiconductor device. In one example embodiment, a method for manufacturing a semiconductor device includes various steps. First, a logic metal and a capacitor lower metal is formed on a first insulating film that is formed on a semiconductor substrate. Next, a portion of the capacitor lower metal is selectively etched to a predetermined depth. Then, a second insulating film is formed over an entire upper surface of the logic metal, the first insulating film, and the capacitor lower metal. Next, a capacitor upper metal is formed on the second insulating film in a region corresponding to the etched portion of the capacitor lower metal. Finally, a third insulating film is formed on an entire upper surface of the second insulating film and the capacitor upper metal.