Abstract: Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and subsequently processed to form praseodymium oxide dielectrics. Monolayers that contain titanium or other metals are deposited onto a substrate and subsequently processed to form metal electrodes. Resulting capacitor structures includes properties such as improved dimensional control. One improved dimensional control includes thickness. Some resulting capacitor structures also include properties such as an amorphous or nanocrystalline microstructure. Selected components of capacitors formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.

Abstract: A method for fabrication of single crystal silicon micromechanical resonators using a two-wafer process, including either a Silicon-on-insulator (SOI) or insulating base and resonator wafers, wherein resonator anchors, a capacitive air gap, isolation trenches, and alignment marks are micromachined in an active layer of the base wafer; the active layer of the resonator wafer is bonded directly to the active layer of the base wafer; the handle and dielectric layers of the resonator wafer are removed; viewing windows are opened in the active layer of the resonator wafer; masking the single crystal silicon semiconductor material active layer of the resonator wafer with photoresist material; a single crystal silicon resonator is machined in the active layer of the resonator wafer using silicon dry etch micromachining technology; and the photoresist material is subsequently dry stripped.

Abstract: A method for fabricating an interconnect structure is described. A substrate with a conductive part thereon is provided, a first porous low-k layer is formed on the substrate, and then a first UV-curing step is conducted. A damascene structure is formed in the first porous low-k layer to electrically connect with the conductive part, and then a first UV-absorption layer is formed on the first porous low-k layer and the damascene structure. A second porous low-k layer is formed on the first UV-absorption layer, and a second UV-curing step is conducted.

Abstract: On a silicon substrate, a first insulation layer, a lower conductive layer, a capacitor-insulator layer, and an upper conductive layer are formed in that order. Then, a first resist pattern is formed, the upper conductive layer is etched to form an upper electrode, and the capacitor-insulator layer is successively etched partway under the same etching condition as that of the upper conductive layer. Next, second resist pattern is formed, the remaining part of the capacitor-insulator layer is etched to form a second insulation layer, and the lower conductive layer is successively etched under the same etching condition as that of the capacitor-insulator layer so as to form a lower electrode and a lower wiring. In this manner, an MiM capacitor element constituted by the upper electrode, a part of the second insulation layer, and the lower electrode can be fabricated.

Abstract: A method of forming a semiconductor device, includes forming a lower electrode including a metal and a nitrogen on a semiconductor substrate, irradiating a reducing gas to a surface of the lower electrode, and irradiating a gas containing silicon to the surface of the lower electrode to form a projection containing silicide by reacting the metal with the silicon in an island shape on the surface of the lower electrode. Then, a capacitor film is formed on the lower electrode and the projection, and an upper electrode is formed on the capacitor film.

Abstract: Devices and methods for their formation, including electronic devices containing capacitors, are described. In one embodiment, a device includes a substrate and a capacitor is formed on the substrate. The capacitor includes first and second electrodes and a capacitor dielectric between the first and second electrodes. At least one of the first and second electrodes includes a metal layer having carbon nanotubes coupled thereto. In one aspect of certain embodiments, the carbon nanotubes are at least partially coated with an electrically conductive material. In another aspect of certain embodiments, the substrate comprises an organic substrate and the capacitor dielectric comprises a polymer material. Other embodiments are described and claimed.

Abstract: In a memory cell area of a semiconductor device, first, second, and third inter-layer insulating films respectively cover a cell transistor, a bit wiring line, and a capacitor which are connected to each other. In an adjacent peripheral circuit area, a peripheral-circuit transistor is covered with the first inter-layer insulating film, a first-layer wiring line connected to the peripheral-circuit transistor is provided on the first inter-layer insulating film and covered with the second inter-layer insulating film, and a second-layer wiring line is provided on the third inter-layer insulating film. In the memory cell area, a landing pad is provided on the second inter-layer insulating film and between the capacitor and a contact plug for connecting the capacitor to the cell transistor. An assist wiring line connected to the first-layer wiring line is provided on the main surface of the second inter-layer insulating film, on which the landing pad is provided.

Abstract: There is provided a semiconductor device which includes a base insulating film formed on a semiconductor substrate, a capacitor formed on the base insulating film, an interlayer insulating film covering the capacitor, a first layer metal wiring formed on the interlayer insulating film, a single-layer first insulating film which covers the interlayer insulating film and the first layer metal wiring and has a first film thickness above the first layer metal wiring, a first capacitor protective insulating film formed on the first insulating film, a first cover insulating film which is formed on the first capacitor protective insulating film and has a second film thickness thicker than the first film thickness, above the first layer metal wiring, a third hole formed in the insulating films on the first layer metal wiring, and a fifth conductive plug formed in the third hole.

Abstract: Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

Abstract: A capacitor includes a lower electrode, a first dielectric layer formed over the lower electrode, a second dielectric layer formed over the first dielectric layer, wherein the second dielectric layer includes an amorphous high-k dielectric material, a third dielectric layer formed over the second dielectric layer, and an upper electrode formed over the third dielectric layer.

Abstract: A semiconductor device including: a substrate; an insulating film formed over the substrate; a copper interconnect, having a plurality of hillocks formed over the surface thereof, buried in the insulating film; a first insulating interlayer formed over the insulating film and the copper interconnect; a second insulating interlayer formed over the first insulating interlayer; and an electroconductive layer formed over the second insulating interlayer, wherein the top surface of at least one hillock highest of all hillocks is brought into contact with the lower surface of the second insulating interlayer is provided.

Abstract: Provided herein are methods of forming a metal oxide layer that include providing an organometallic compound and an oxidizing agent to the substrate to form the metal oxide layer on the substrate. The organometallic compound may have the general formula of M(NR1R2)3R3, wherein M is a metal; R1 and R2 are each independently hydrogen or alkyl; and R3 is selected from the group consisting of alkyl, cycloalkyl, heterocycloalkyl, aryl and heteroaryl.

Abstract: The present subject matter includes a capacitor stack disposed in a case, the capacitor stack including one or more substantially planar electrode layers. The one or more substantially planar electrode layers have an etched surface, an unetched surface, and a grade bordering the etched surface and the unetched surface. Also, the present subject matter includes a lid conforming sealingly connected to the material defining the first aperture. Additionally, the present subject matter includes a feedthrough assembly connected to the capacitor stack and passing through the feedthrough hole and sealingly connected to the material defining the feedthrough hole. In the present subject matter, the one or more substantially planar electrode layers are made by printing a curable resin mask onto the one or more substantially planar electrode layers and etching the layers, the curable resin mask defining the grade and adapted to resist etching.

Abstract: A semiconductor device including a multilayer dielectric film and a method for fabricating the semiconductor device are disclosed. The multilayer dielectric film includes a type-one dielectric film having a tetragonal crystalline structure, wherein the type-one dielectric film comprises a first substance. The multilayer dielectric film also comprises a type-two dielectric film also having a tetragonal crystalline structure, wherein the type-two dielectric film comprises a second substance different from the first substance and a dielectric constant of the type-two dielectric film is greater than a dielectric constant of the type-one dielectric film.

Abstract: In this invention, the film thicknesses of an upper barrier film of a lower electrode of a capacitive element and an upper barrier film of a metallic interconnect layer formed in the same layer as this is made thicker than the film thicknesses of upper barrier films of other metallic interconnect layers. Moreover, in this invention, the film thickness of the upper barrier film of the lower electrode of the capacitive element is controlled to be 110 nm or more, more preferably, 160 nm or more. A decrease in the dielectric voltage of the capacitive dielectric film due to cracks in the upper barrier film does not occur and the deposition temperature of the capacitive dielectric film can be made higher, so that a semiconductor device having a MIM capacitor with high performance and high capacitance can be achieved, where the dielectric voltage of the capacitive dielectric film is improved.

Abstract: A semiconductor device comprises an insulation film that is provided on a semiconductor substrate, a first contact plug that is provided in the insulation film and includes a metal, a first adhesive film that is provided on the insulation film, has a higher oxygen affinity than the metal, and includes an oxide, a second adhesive film that is provided on the first contact plug and has a film thickness that is smaller than a film thickness of the first adhesive film, a first capacitor electrode that is provided on the contact plug and the first adhesive film, has a part in direct contact with the first contact plug, a capacitor insulation film that is provided on the first capacitor electrode, and a second capacitor electrode that is provided on the capacitor insulation film.

Abstract: An electronic assembly (98) includes a substrate (20), a capacitor having first and second conductors (38,54) formed over the substrate, a first set of conductive members (76) formed over the substrate and being electrically connected to the first conductor of the capacitor, and a second set of conductive members (78) formed over the substrate and being electrically connected to the second conductor of the capacitor.

Abstract: A process for producing an activated carbon for an electrode of an electric double-layer capacitor, includes a step of subjecting a carbonized material to an alkali activating treatment, wherein the carbonized material has an average true specific gravity of 1.450 to 1.650 and a variation of the true specific gravities of 0.025 or less.

Abstract: Capacitive decoupling circuits and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip with a first power rail for a first no-load bias level and a ground rail. A first voltage divider is electrically coupled between the first power rail and the ground rail and has a midpoint node. A first pair of capacitors is electrically coupled between the first power rail, the midpoint node and the ground rail to provide capacitive decoupling for power delivered to the first power rail. A second power rail has a second no-load bias less than the first no-load bias. A second pair of capacitors is electrically coupled between the ground rail and the second power rail to provide capacitive decoupling for power delivered to the second power rail.

Abstract: A semiconductor device of the present invention includes a plurality of lower electrodes covering the entire surfaces of a plurality of trenches formed in a first interlayer insulating film, a capacitive insulating film covering the entire surfaces of the plurality of lower electrodes, and an upper electrode covering the surfaces of the plurality of lower electrodes from above with the capacitive insulating film interposed between the upper electrode and the plurality of lower electrodes. The upper electrode is formed with a stress-relieving part, such as a crack, a notch or a recess.

Abstract: In a semiconductor device having a substrate which has a metal surface, an insulating film which is formed on the substrate having the metal surface, and a pixel unit which is formed on the insulating film; the pixel unit includes a TFT, and wiring lines connected with the TFT, and a storage capacitor is constituted by the substrate (11) having the metal surface, the insulating film (12), and the wiring line (21). As the insulating film is thinner, and as the area of a region where the insulating film and the wiring line lie in contact is larger, the storage capacitor is endowed with a larger capacity.

Abstract: This disclosure provides methods for assembling multiple anode stacked capacitor configurations with a temporary adhesive to aide in the alignment of separator materials and electrodes without sacrificing energy density, and electrolytic capacitors comprising such configurations. The temporary adhesive for use in the electrode assemblies will preferably comprise a polymer that is substantially soluble in a solvent-based electrolyte for use in an electrolytic capacitor.

Abstract: A dry titanium nitride (TiN) powder abrasion method roughens the surface of a valve metal foil for use as a cathode in an electrolytic capacitor. This increases the surface area of the foil, thereby increasing the double-layer capacitance of the cathode, and also mechanically alloys TiN powder to the surface of the foil, thereby increasing the pseudo-capacitance of the cathode. In one embodiment, a piece of thin titanium foil is mounted on a hard metal backing and at least one surface of the foil is abraded with fine titanium nitride powder. In another embodiment, a continuous metal foil tape is fed into a bead blasting box and at least one surface of the metal foil tape is abraded with TiN powder delivered by a bead blasting nozzle located within the bead blasting box. Accordingly, a cathode having increased capacitance capability is provided to more closely match the capacitance of a poly-anode stack.

Abstract: A structure and associated method for forming a structure. The structure comprises a first doped region, a second doped region, a third doped region, and a first shallow trench isolation structure formed within a substrate. The first doped region comprises a first dopant having a first polarity. The second doped region forms a first electrode of a capacitor. The third doped region forms a second electrode of the capacitor. Each of the second doped region and the third doped region comprises a second dopant having a second polarity. The first shallow trench isolation structure is formed between the second doped region and the third doped region. The capacitor comprises a main capacitance. The structure comprises a first parasitic capacitance and a second parasitic capacitance. The first parasitic capacitance is about equal to the second parasitic capacitance.

Abstract: The present invention discloses a metal-insulator-metal (MIM) capacitor and a method for fabricating the MIM capacitor, comprising forming a bottom insulation layer, a capacitor electrode material layer, and a hard mask material layer on a semiconductor substrate having a metal wire thereon; forming a hard mask by etching the hard mask material layer using a photosensitive mask; forming a capacitor electrode by etching the capacitor electrode material layer using the hard mask as an etching mask; and forming a top insulation layer on an entire surface of the semiconductor.

Abstract: A thin film capacitor including a substrate, a capacitor portion having an upper conductor, a lower conductor, and a dielectric thin film, and a resin protective layer for protecting the capacitor portion. A barrier layer is interposed between the capacitor portion and the resin protective layer. The barrier layer includes a crystalline dielectric barrier layer formed in contact with the capacitor portion and having the same composition system as the dielectric thin film, and an amorphous inorganic barrier layer formed on the surface of the crystalline dielectric barrier layer and composed of silicon nitride having non-conductivity. The inorganic barrier layer prevents deterioration in the properties of the dielectric thin film by blocking diffusion of the constituent elements of the inorganic barrier layer toward the capacitor portion.

Abstract: A micromechanical component includes a substrate, on which at least one layer sequence is situated, which includes at least one micromechanical functional element, and on which at least one layer sequence is situated that is able to act as at least one macroelectronic, passive component.

Abstract: A semiconductor device has a MIM capacitor including a first insulating film formed on a semiconductor substrate, a lower electrode composed of a first metal film formed on the first insulating film, a capacitor insulating film formed on the lower electrode, and an upper electrode composed of a second metal film formed on the capacitor insulating film. The semiconductor device further has a lower interconnect composed of the first metal film formed on the first insulating film and an upper interconnect composed of the second metal film formed on the lower interconnect. The upper interconnect and the upper electrode are formed integrally.

Abstract: A display device includes a substrate, a capacitor lower electrode having a polycrystalline silicon film formed over the substrate and a contact metal film provided over the polycrystalline silicon film, a gate insulating film formed over the capacitor lower electrode and a gate metal electrode formed to a position opposing the capacitor lower electrode over the gate insulating film and formed to be disposed inner side of the capacitor lower electrode in top view.

Abstract: Embodiments relate to a metal-insulator-metal (MIM) capacitor that may include a lower insulation layer where a capacitor lower metal layer is already formed, an intermediate structure, a first conductive structure, and a second conductive structure. The intermediate structure may include a first capacitor insulation pattern, a capacitor middle metal layer, a second capacitor insulation pattern, a capacitor upper metal layer, and an insulation pattern formed in sequence over the lower insulation layer. The first conductive structure may include a copper-based material and may be coupled between the capacitor upper metal layer and the capacitor lower metal layer. The second conductive structure may include a copper-based material and is coupled to the capacitor middle metal layer.

Abstract: Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

Abstract: A fixed parallel plate micro-mechanical systems (MEMS) based sensor is fabricated to allow a dissolved dielectric to flow through a porous top plate, coming to rest on a bottom plate. A post-deposition bake ensures further purity and uniformity of the dielectric layer. In one embodiment the dielectric is a polymer. In one embodiment, a support layer is deposited onto the top plate for strengthening the sensor. In another embodiment, the bottom plate is dual-layered for a narrowed gap. Integrated circuit arrays of such sensors can be made, having multiple devices separated from each other by a physical barrier, such as a polycrystalline containment rim or trough, for preventing polymer material from one sensor from interfering with that of another.

Abstract: Means for Solution: This interposer (10) comprises the silicon substrate (12), a plurality of through-hole conductors (20) formed on the above-described silicon substrate, and a capacitor (15) formed with the upper electrodes (14) and the lower electrodes (18) formed by extending the land portions of the above-described through-hole conductors and the dielectric layer (16) formed between the both electrodes. The rewiring layers (23-1, 23-2) formed as desired are formed on the layers other than the above-described capacitor layer.

Abstract: In a semiconductor device and a method of fabrication thereof, a semiconductor device comprises a substrate including transistors and partitioned into a memory region and a logic region. A bit line is electrically connected to at least one of the transistors in the memory region. A logic capacitor is formed on the logic region. The logic capacitor includes a logic lower metal electrode of a same layer as that of the bit line, a logic dielectric film, and a logic upper metal electrode.

Abstract: A microelectronic device, a method of fabricating the device, and a system including the device. The method includes: providing a substrate including an underlying conductive layer and a polymer build-up layer overlying the underlying conductive layer; providing a passive microelectronic structure; embedding the passive structure in the polymer build-up layer of the substrate; and patterning the passive structure after embedding, patterning including over-etching the bottom electrode layer. The passive microelectronic structure being embedded includes an unpatterned bottom electrode layer; an unpatterned capacitor dielectric layer overlying the bottom electrode layer; and an unpatterned top electrode layer overlying the capacitor dielectric layer.

Abstract: The invention describes an in-situ method of fabricating a metal insulator metal (MIM) capacitor and products formed by the same. The method utilizes atomic layer deposition (ALD) or metal-organic chemical vapor deposition (MOCVD). In the method, a metal precursor is sequentially reacted with a nitrogen source, oxidant, and then a nitrogen source again. Reaction with the nitrogen source generates the outermost conductive metal nitride (MN) layers (121). Reaction with the oxidant generates an inner dielectric metal oxide (MOx) layer (110). Alternatively, or in addition, the metal precursor can be reacted with a mixture of oxidant and nitrogen source to generate inner dielectric layer(s) (231, 232, 310) of metal oxynitride (MOxNy). Because the same metal is used throughout the capacitor, the layers in the MIM capacitor exhibits excellent compatibility and stability.

Abstract: A method of forming a dielectric layer in a capacitor adapted for use in a semiconductor device is disclosed. The method includes forming a first ZrO2 layer, forming an interfacial layer using a plasma treatment on the first ZrO2 layer, and forming a second ZrO2 layer on the interfacial layer.

Abstract: A printed circuit board having embedded capacitors includes a double-sided copper-clad laminate including first circuit layers formed in the outer layers thereof, the first circuit layers including bottom electrodes and circuit patterns; dielectric layers formed by depositing alumina films on the first circuit layers by atomic layer deposition; second circuit layers formed on the dielectric layers and including top electrodes and circuit patterns; one-sided copper-clad laminates formed on the second circuit layers; blind via-holes and through-holes formed in predetermined portions of the one-sided copper-clad laminates; and plating layers formed in the blind via-holes and the through-holes. The manufacturing method of the printed circuit board is also disclosed.

Abstract: A production method for a solid electrolytic capacitor comprises the steps of mixing a metal alkoxybenzenesulfonate and/or a metal alkylsulfonate as an oxidizing agent and an electrically conductive polymer in a solvent, immersing a capacitor element in the resulting mixture solution, and forming an electrically conductive polymer layer in the capacitor element by thermal polymerization.

Abstract: The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device region; forming caps made of one or more layers of a cap material over said plurality of gate stacks in said memory cell region and over said at least one gate stack in said peripheral device region; forming a first contact hole between two neighboring gate stacks in said memory cell region; depositing a first protective layer over said memory cell region and peripheral device region; exposing said cap of said at least one gate stack in said peripheral device region; modifying said exposed cap of said at least one gate stack in said peripheral device region in a process step wherein said first protective layer acts as a mask in said memory cell region; forming a second protective layer over said modified cap in said peripheral device region; partly

Abstract: A method of manufacturing a semiconductor device includes: forming a transistor with first and second ends of a main current path, and a control electrode, covering the transistor with a first insulating film, forming first through third openings that expose the first and second ends and the control electrode, and burying or filling first to third conductive materials in the first to third openings respectively, forming the ferroelectric capacitor by laminating the first electrode, the ferroelectric film, and the second electrode, laminating the second insulating film and the moisture diffusion protective film, forming the fourth opening to expose the third conductive material through the second insulating film and the moisture diffusion protective film, and forming a first wiring layer, which has electrical connection with the control electrode.

Abstract: Embodiments of the invention provide flat-type capacitors that prevent degradation of the dielectric layer, thereby improving the electrical properties of the capacitor. The capacitor includes a lower interconnection formed in a predetermined portion of a semiconductor substrate, a lower electrode formed on the lower interconnection that is electrically coupled to the lower interconnection; a concave dielectric layer formed on the lower electrode; a concave upper electrode formed on the dielectric layer; a first upper interconnection that is electrically coupled to the lower interconnection; and a second upper interconnection that is coupled to the upper electrode. The concave upper electrode is larger than the lower electrode.

Abstract: Provided is a method of manufacturing a capacitor embedded printed circuit board. In the method, a laminated body is prepared, including a laminated plate having first and second copper films on both sides thereof, where at least one bottom electrode is provided on at least one side. A dielectric layer is formed on the at least one bottom electrode. A metal layer is formed on a top surface of the dielectric layer where a capacitor is to be formed. A conductive paste layer is formed on at least one region of a top surface of the metal layer, where the conductive paste layer and the metal layer is provided as a top electrode. An insulation resin layers are formed on both sides of the laminated plate, respectively. A conductive via is formed in the insulation resin layer such that it is connected to the conductive paste layer.

Abstract: A new method to form a SRAM memory cell in an integrated circuit device is achieved. The method comprises providing a bi-stable flip-flop cell having a data storage node and a data bar storage node. A first capacitor is formed coupled to the data bar storage node, and a second capacitor is formed coupled to the data storage node. The first and second capacitors comprise a first conductor layer overlying a second conductor layer with a dielectric layer therebetween. One of the first and second conductor layers is coupled to ground. A new SRAM device is disclosed.

Abstract: A carbon containing masking layer is patterned to include a plurality of container openings therein having minimum feature dimensions of less than or equal to 0.20 micron. The container openings respectively have at least three peripheral corner areas which are each rounded. The container forming layer is plasma etched through the masking layer openings. In one implementation, such plasma etching uses conditions effective to both a) etch the masking layer to modify shape of the masking layer openings by at least reducing degree of roundness of the at least three corners in the masking layer, and b) form container openings in the container forming layer of the modified shapes. Capacitors comprising container shapes are formed using the container openings in the container forming layer. Other implementations and aspects are disclosed.

Abstract: A method for forming a capacitor in a semiconductor device is disclosed. The method includes forming a storage node electrode on a semiconductor substrate, forming a dielectric layer having a high dielectric constant on the storage node electrode, depositing a plate electrode on the dielectric layer, thereby forming by-product impurities, and removing by-product impurities remaining on the plate electrode by introducing a hydrogen (H) atom-containing gas onto the semiconductor substrate while depositing a capping layer on the plate electrode.

Abstract: A thin film transistor substrate of a LCD device and a fabricating method thereof are disclosed for simplifying a fabricating process and enlarging a capacitance value of a storage capacitor without any reduction of aperture ratio. The LCD device includes: a double-layered gate line having a first transparent conductive layer and a second opaque conductive layer, the second opaque conductive layer have a step coverage; a gate insulation layer film on the gate line; a data line crossing the gate line to define a pixel region; a TFT connected to the gate line and the data line; a pixel electrode connected to the TFT via a contact hole of a protective film on the TFT; and a storage capacitor overlapping the pixel electrode and having a lower storage electrode formed of the first transparent conductive layer.

Abstract: Providing through-wafer interconnections in a semiconductor wafer includes forming a sacrificial membrane in a pre-existing semiconductor wafer, depositing metallization over one side of the wafer so as to cover exposed portions of the sacrificial membrane facing the one side of the wafer, removing exposed portions of the sacrificial membrane facing the other side of the wafer, and depositing metallization over the other side of the wafer so as to contact the previously deposited metallization. Techniques also are disclosed for providing capacitive and other structures using thin metal membranes.

Abstract: Methods of manufacturing a metal-insulator-metal capacitor are provided.

Abstract: A semiconductor device and a relatively simple fabrication process which may maximize fabrication yield. A semiconductor device may include at least one of the following: A first substrate including a capacitor cell. A second substrate including a circuit unit having a transistor and a wire. A connection electrode which electrically connects the capacitor cell and the circuit unit.