Including Selectively Removing Material To Undercut And Expose Storage Node Layer Patents (Class 438/397)
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Patent number: 8263457Abstract: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive metal nitride-comprising material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Inner sidewalls of the conductive material within the trench are annealed in a nitrogen-comprising atmosphere. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area. The conductive material within the array area is incorporated into a plurality of capacitors.Type: GrantFiled: October 10, 2011Date of Patent: September 11, 2012Assignee: Micron Technology, Inc.Inventors: Vishwanath Bhat, Kevin R. Shea
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Patent number: 8252641Abstract: In a method of manufacturing a semiconductor device, first contact holes reaching diffusion regions of a cell transistor, bit line contact holes reaching diffusion regions of the cell transistor, and interconnect grooves communicating with the bit line contact holes are buried in a first insulating film. In addition, first contact plugs and bit line contacts are respectively formed by burying conductive materials in the first contact holes, the bit line contact holes and the interconnect grooves, and the first contact plugs are electrically connected to a capacitor formed in a third insulating film through an opening formed in a second insulating film.Type: GrantFiled: July 14, 2010Date of Patent: August 28, 2012Assignee: Renesas Electronics CorporationInventor: Yasuyuki Aoki
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Patent number: 8207568Abstract: Method of fabricating a MIM capacitor and MIM capacitor. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.Type: GrantFiled: September 19, 2005Date of Patent: June 26, 2012Assignee: International Business Machines CorporationInventors: Anil K. Chinthakindi, Douglas D. Coolbaugh, Keith E. Downes, Ebenezer E. Eshun, Zhong-Xiang He, Robert M. Rassel, Anthony K. Stamper
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Patent number: 8163613Abstract: A method of forming a plurality of capacitors includes forming a plurality of individual capacitor electrodes using two masking steps. An earlier of the two masking steps is used to form an array of first openings over a plurality of storage node contacts. A later of the two masking steps is used to form an array of second openings received partially over and partially offset from the array of first openings. Overlapping portions of the first and second openings are received over the storage node contacts. After both of the two masking steps, conductive material of the individual capacitor electrodes is deposited into the overlapping portions of each of the first and second openings. The individual capacitor electrodes are incorporated into a plurality of capacitors. Other aspects and implementations are contemplated.Type: GrantFiled: June 25, 2010Date of Patent: April 24, 2012Assignee: Micron Technology, Inc.Inventor: Fred D. Fishburn
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Patent number: 8153486Abstract: A method for fabricating a capacitor includes forming an etch stop layer, a first isolating insulation layer, and a floating layer over a substrate including storage node contact plugs to form a resulting substrate structure; etching the floating layer, the first isolating insulation layer, and the etch stop layer to form a plurality of open regions; forming a conductive layer over the substrate structure; forming a second isolating insulation layer over the conductive layer, the second isolating insulation layer filling upper portions of the open regions; etching portions of the remaining floating layer to form a floating pattern; performing a storage node isolation process in a manner that the floating pattern is exposed to form a plurality of storage nodes having sidewalls supported by the floating pattern; and removing the etched first isolating insulation layer.Type: GrantFiled: November 5, 2009Date of Patent: April 10, 2012Assignee: Hynix Semiconductor Inc.Inventor: Seok-Ho Jie
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Patent number: 8148223Abstract: Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.Type: GrantFiled: May 22, 2006Date of Patent: April 3, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Ching Lin, Chun-Yao Chen, Chen-Jong Wang, Shou-Gwo Wuu, Chung S. Wang, Chien-Hua Huang, Kun-Lung Chen, Ping Yang
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Patent number: 8142522Abstract: Capacitive devices are described having electrical interconnects of electrodes which possess efficient electrical contact between current collectors, electrical isolation of electrodes, and/or electrochemical stability, while minimizing the mechanical stress and strain applied to the electrodes. The capacitive devices are adaptable to a wide range of electrode dimensions and electrode stack heights.Type: GrantFiled: June 9, 2010Date of Patent: March 27, 2012Assignee: Corning IncorporatedInventors: Roy Joseph Bourcier, Todd P St Clair, Andrew R Nadjadi, Vitor Marino Schneider
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Patent number: 8138572Abstract: The present invention relates to a semiconductor and manufacturing method thereof, in which a nano tube structure is vertically grown to form a lower electrode of a cell region and a via contact of peripheral circuit region. Therefore, capacitance of the lower electrode is secured without an etching process for high aspect ratio. Also, the via contact can be formed for corresponding to the height of the lower electrode.Type: GrantFiled: December 17, 2009Date of Patent: March 20, 2012Assignee: Hynix Semiconductor IncInventor: Keon Yoo
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Patent number: 8129240Abstract: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive metal nitride-comprising material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Inner sidewalls of the conductive material within the trench are annealed in a nitrogen-comprising atmosphere. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area. The conductive material within the array area is incorporated into a plurality of capacitors.Type: GrantFiled: August 16, 2010Date of Patent: March 6, 2012Assignee: Micron Technology, Inc.Inventors: Vishwanath Bhat, Kevin R. Shea
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Patent number: 8129251Abstract: A METAL-INSULATOR-METAL structured capacitor is formed with polysilicon instead of an oxide film as a sacrificial layer material that defines a storage electrode region. A MPS (Meta-stable Poly Silicon) process is performed to increase the surface area of the sacrificial layer that defines the storage electrode region and also increase the area of the storage electrode formed over sacrificial layer. This process results in increasing the capacity of the capacitor in a stable manner.Type: GrantFiled: November 13, 2006Date of Patent: March 6, 2012Assignee: Hynix Semiconductor Inc.Inventor: Won Sun Seo
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Patent number: 8114765Abstract: The embodiments generally relate to methods of making semiconductor devices, and more particularly, to methods for making semiconductor pillar structures and increasing array feature pattern density using selective or directional gap fill. The technique has application to a variety of materials and can be applied to making monolithic two or three-dimensional memory arrays.Type: GrantFiled: April 5, 2010Date of Patent: February 14, 2012Assignee: SanDisk 3D LLCInventors: Huiwen Xu, Yung-Tin Chen, Steven J. Radigan
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Publication number: 20120012979Abstract: An improved semiconductor capacitor and method of fabrication is disclosed. A nitride stack, comprising alternating sublayers of slow-etch and fast-etch nitride is deposited on a substrate. The nitride stack is etched via an anisotropic etch technique such as reactive ion etch. A wet etch then etches the nitride stack, forming a corrugated shape. The corrugated shape increases surface area, and hence increases the capacitance of the capacitor.Type: ApplicationFiled: July 15, 2010Publication date: January 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Vaclav Horak, Shom Ponoth, Hosadurga Shobha, Chih-Chao Yang
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Patent number: 8084323Abstract: The invention provides a method for forming a stack capacitor of a memory device, including providing a substrate, forming a patterned sacrificial layer with a plurality of first openings over the substrate, conformally forming a first conductive layer on the patterned sacrificial layer and in the first openings, forming a second conductive layer on the first conductive layer to seal the first openings with a void formed therein, removing a portion of the first and second conductive layers to expose the patterned sacrificial layer, and removing at least a portion of the patterned sacrificial layer to form bottom cell plates.Type: GrantFiled: December 17, 2009Date of Patent: December 27, 2011Assignee: Nanya Technology CorporationInventor: Shin-Yu Nieh
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Publication number: 20110312152Abstract: Methods of fabricating integrated circuit devices include forming an integrated circuit capacitor on a substrate. This integrated circuit capacitor includes a lower capacitor electrode, a capacitor dielectric region on the lower capacitor electrode and an upper capacitor electrode on the capacitor dielectric region. The upper capacitor electrode has a smaller surface area relative to the lower capacitor electrode. An interlayer insulating layer is formed on the integrated circuit capacitor. This interlayer insulating layer is polished to have a planarized surface thereon that is spaced from an upper surface of the upper capacitor electrode by a first distance and spaced from an upper surface of the lower capacitor electrode by a second distance greater than the first distance.Type: ApplicationFiled: June 16, 2010Publication date: December 22, 2011Inventors: Yoon-Hae Kim, Je-Don Kim, Young-Mook Oh
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Patent number: 8053308Abstract: In a method of forming a pattern, a mold layer having an opening is formed on a substrate. A conductive layer is formed on the mold layer having the opening, the conductive layer having a substantially uniform thickness. A buffer layer pattern is formed in the opening having the conductive layer, the buffer layer pattern having a cross-linked structure of water-soluble copolymers including a repeating unit of N-vinyl-2-pyrrolidone and a repeating unit of acrylate. An upper portion of the conductive layer exposed over the buffer layer pattern is etched. Accordingly, a conductive pattern for a semiconductor device is formed on the substrate. The method of forming a pattern may simplify manufacturing processes for a capacitor and a semiconductor device, and may improve their efficiencies.Type: GrantFiled: November 27, 2007Date of Patent: November 8, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-Min Kim, Jae-Ho Kim, Young-Ho Kim, Myung-Sun Kim
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Patent number: 8053326Abstract: A semiconductor device, includes: a first storage node contact plug penetrating a first interlayer insulation layer and partially protruding above the first interlayer insulation layer; a second storage node contact plug contacting the first storage node contact plug that protrudes above the first interlayer insulation layer; a storage node contacting a top surface of the second storage node contact plug; and a second interlayer insulation layer formed over the first interlayer insulation layer, wherein the second interlayer insulation layer surrounds an outer sidewall at a bottom region of the first storage node, and the second storage node contact plug, and wherein the first storage node contact plug protruding above the first interlayer insulation layer and the second storage node contact plug.Type: GrantFiled: December 30, 2008Date of Patent: November 8, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jong-Bum Park, Han-Sang Song, Jong-Kook Park
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Patent number: 8048757Abstract: A method for fabricating a capacitor includes forming an isolation layer over a cell region and a peripheral region of a substrate. The isolation layer forms a plurality of open regions in the cell region. Storage nodes are formed on surfaces of the open regions. An upper portion of the isolation layer is etched to expose upper outer walls of the storage nodes. A sacrificial pattern is formed over the isolation layer to enclose the upper outer walls of the storage nodes. The isolation layer in the peripheral region is etched to expose side portions of the resulting structure obtained after forming the sacrificial pattern in the cell region. With the sacrificial pattern supporting the storage nodes, the isolation layer in the cell region is removed. The sacrificial pattern is then removed.Type: GrantFiled: March 22, 2011Date of Patent: November 1, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jae-Sung Roh, Kee-Jeung Lee, Han-Sang Song, Seung-Jin Yeom, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim
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Patent number: 8048756Abstract: A microelectronic substrate and method for removing adjacent conductive and nonconductive materials from a microelectronic substrate. In one embodiment, the microelectronic substrate includes a substrate material (such as borophosphosilicate glass) having an aperture with a conductive material (such as platinum) disposed in the aperture and a fill material (such as phosphosilicate glass) in the aperture adjacent to the conductive material. The fill material can have a hardness of about 0.04 GPa or higher, and a microelectronics structure, such as an electrode, can be disposed in the aperture, for example, after removing the fill material from the aperture. Portions of the conductive and fill material external to the aperture can be removed by chemically-mechanically polishing the fill material, recessing the fill material inwardly from the conductive material, and electrochemically-mechanically polishing the conductive material.Type: GrantFiled: March 24, 2010Date of Patent: November 1, 2011Assignee: Micron Technology, Inc.Inventors: Whonchee Lee, Scott G. Meikle, Guy T. Blalock
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Patent number: 8048758Abstract: A method for fabricating a capacitor includes forming an isolation layer over a cell region and a peripheral region of a substrate. The isolation layer forms a plurality of open regions in the cell region. Storage nodes are formed on surfaces of the open regions. A sacrificial pattern is formed over the isolation layer and covers the cell region. The isolation layer is etched in the peripheral region to expose side portions of the resulting structure obtained after forming the sacrificial pattern in the cell region. With the sacrificial pattern supporting the storage nodes, the isolation layer in the cell region is removed. The sacrificial pattern is then removed.Type: GrantFiled: March 22, 2011Date of Patent: November 1, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jae-Sung Roh, Kee-Jeung Lee, Han-Sang Song, Seung-Jin Yeom, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim
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Patent number: 8044467Abstract: A semiconductor device with reduced contact resistance between a substrate and a plug includes a gate electrode disposed over the substrate, the plug formed over the substrate at both sides of the gate electrode and having a sidewall with a positive slope, a capping layer disposed between the gate electrode and the plug, and a gate hard mask layer whose sidewall disposed over the gate electrode is extended to a top surface of the capping layer. By employing the capping layer having a sidewall with a negative slope, the plug having the sidewall with a positive slope can be formed regardless of a shape or profile of the sidewall of the gate electrode. As a result, the contact area between the substrate and the plug is increased.Type: GrantFiled: December 24, 2008Date of Patent: October 25, 2011Assignee: Hynix Semiconductor Inc.Inventor: Byung-Duk Lee
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Patent number: 8017475Abstract: A method of fabricating a high-performance capacitor that may be incorporated into a standard CMOS fabrication process suitable for submicron devices is described. The parameters used in the standard CMOS process may be maintained, particularly for the definition and etch of the lower electrode layer. To reduce variation in critical dimension width, an Anti-Reflective Layer (ARL) is used, such as a Plasma Enhanced chemical vapor deposition Anti-Reflective Layer (PEARL) or other Anti-Reflective Coatings (ARCS), such as a conductive film like TiN. This ARL formation occurs after the capacitor specific process steps, but prior to the masking used for defining the lower electrodes. A Rapid Thermal Oxidation (RTO) is performed subsequent to removing the unwanted capacitor dielectric layer from the transistor poly outside of the capacitor regions, but prior to the PEARL deposition.Type: GrantFiled: July 20, 2010Date of Patent: September 13, 2011Assignee: IXYS CH GmbHInventors: Timothy K. Carns, John L. Horvath, Lee J. DeBruler, Michael J. Westphal
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Patent number: 8008162Abstract: Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a more nonlinear, asymmetric I-V curve and enhanced rectifying behavior in the select devices. The select devices may comprise, for example, a metal-insulator-insulator-metal (MIIM) diode. Various methods may be used to form select devices and memory systems including such select devices. Memory devices and electronic systems include such select devices.Type: GrantFiled: November 19, 2008Date of Patent: August 30, 2011Assignee: Micron Technology, Inc.Inventors: Bhaskar Srinivasan, Gurtej S. Sandhu
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Patent number: 7998825Abstract: A method for fabricating a semiconductor device includes: forming an etch stop pattern over a conductive layer, the etch stop pattern having a first opening exposing a top surface of the conductive layer; forming an insulation layer over the etch stop pattern; selectively etching the insulation layer to form a second opening exposing the top surface of the conductive layer; and enlarging the second opening until the etch stop pattern is exposed.Type: GrantFiled: December 24, 2008Date of Patent: August 16, 2011Assignee: Hynix Semiconductor Inc.Inventors: Han-Sang Song, Jong-Bum Park, Jong-Kook Park
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Publication number: 20110165756Abstract: A semiconductor device includes a guard ring surrounding a memory cell region; a peripheral circuit region outside of the guard ring; a supporting film formed on the guard ring and on the peripheral circuit region; and a contact plug formed in the peripheral circuit region. The guard ring and the contact plug are completely filled with the same conductive material.Type: ApplicationFiled: January 5, 2011Publication date: July 7, 2011Applicant: Elpida Memory, IncInventor: Satoru ISOGAI
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Patent number: 7960241Abstract: A manufacturing method for double-side capacitor of stack DRAM has steps of: forming a sacrificial structure in the isolating trench and the capacitor trenches; forming a first covering layer and a second covering layer on the sacrificial structure; modifying a part of the second covering layer; removing the un-modified second covering layer and the first covering layer to expose the sacrificial structure; removing the exposed part of the sacrificial structure to expose the electrode layer; removing the exposed electrode layer to expose the oxide layer; and removing the oxide layer and sacrificial structure to form the double-side capacitors.Type: GrantFiled: February 2, 2010Date of Patent: June 14, 2011Assignee: Inotera Memories, Inc.Inventors: Shin-Bin Huang, Tzung-Han Lee, Chung-Lin Huang
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Publication number: 20110129982Abstract: A semiconductor device that is capable of preventing a storage node bunker defect or a defect due to loss of a barrier layer, and a method for forming a capacitor thereof. The semiconductor memory device includes a contact hole formed in an interlayer dielectric layer on a semiconductor substrate; a barrier layer formed on the bottom of the contact hole; a first storage node contact formed of a conductive layer that fills the rest of the contact hole; a second storage node contact formed on the result formed with the first storage node contact so as to be shifted by a given distance from the first storage node contact; an insulation layer formed between the second storage node contacts; a storage electrode connected with the second storage node contact and isolated on a per cell basis; and dielectric layer and plate electrode for covering the storage electrode.Type: ApplicationFiled: January 14, 2011Publication date: June 2, 2011Applicant: HYNIX SEMICONDUCTOR INCInventor: Jong Bum Park
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Patent number: 7951682Abstract: A method for fabricating a capacitor in a semiconductor device includes forming an insulation layer over a substrate, forming a storage node contact plug passing through the insulation layer and coupled to the substrate, recessing the storage node contact plug to a certain depth to obtain a sloped profile, forming a barrier metal over the surface profile of the recessed storage node contact plug, forming a sacrificial layer over the substrate structure, etching the sacrificial layer to form an opening exposing the barrier metal, forming a bottom electrode over the surface profile of the opening, and removing the etched sacrificial layer.Type: GrantFiled: May 4, 2009Date of Patent: May 31, 2011Assignee: Hynix Semiconductor Inc.Inventor: Soung-Min Ku
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Patent number: 7919386Abstract: The invention includes methods of forming pluralities of capacitors. In one implementation, a method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes within a capacitor array area over a substrate. The capacitor electrodes comprise outer lateral sidewalls. The plurality of capacitor electrodes is supported at least in part with a retaining structure which engages the outer lateral sidewalls. The retaining structure is formed at least in part by etching a layer of material which is not masked anywhere within the capacitor array area to form said retaining structure. The plurality of capacitor electrodes is incorporated into a plurality of capacitors. Other aspects and implementations are contemplated.Type: GrantFiled: April 27, 2009Date of Patent: April 5, 2011Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, D. Mark Durcan
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Patent number: 7910452Abstract: A method for fabricating a capacitor includes forming an isolation layer over a substrate. The isolation layer forms a plurality of open regions. Storage nodes are formed on surfaces of the open regions. An upper portion of the isolation layer is etched to expose upper outer walls of the storage nodes. A sacrificial layer is formed over the isolation layer to enclose the upper outer walls of the storage nodes. The isolation layer and the sacrificial layer are then removed.Type: GrantFiled: June 29, 2007Date of Patent: March 22, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jae-Sung Roh, Kee-Jeung Lee, Han-Sang Song, Seung-Jin Yeom, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim
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Patent number: 7875526Abstract: A semiconductor device includes a semiconductor substrate divided into a cell array region, a core region, and a peripheral region. Bit lines are formed in the respective regions. Storage node contact plugs are formed in the cell array region, and blocking patterns are simultaneously formed around the bit lines of the core region and the peripheral region. Capacitors are formed in the cell array region to come into contact with the storage node contact plugs, and metal contact plugs are formed to come into contact with the capacitors of the cell array region and the bit lines of the core region and the peripheral region. In the semiconductor device, even if the metal contact plugs are not aligned with the bit lines, the blocking pattern works to stabilize the contact between the metal contact plugs and the bit lines.Type: GrantFiled: May 19, 2010Date of Patent: January 25, 2011Assignee: Hynix Semiconductor Inc.Inventor: Dong Chul Koo
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Patent number: 7858483Abstract: A method for forming a capacitor of a semiconductor device includes forming a first insulation layer having a storage node plug on a semiconductor substrate; forming an etch stop layer and a second insulation layer sequentially on the substrate having the first insulation layer; forming a hole exposing a portion of the storage node plug by selectively etching the second insulation layer by using the etch stop layer; recessing a portion of the storage node plug exposed by the hole; forming a barrier metal layer on a surface of the recessed storage node plug; forming a storage node electrode connected to the storage node plug through the barrier metal layer in the hole; and forming a dielectric layer and a metal layer for a plate electrode sequentially on the storage node electrode.Type: GrantFiled: June 15, 2005Date of Patent: December 28, 2010Assignee: Hynix Semiconductor Inc.Inventors: Hyung Bok Choi, Jong Bum Park, Kee Jeung Lee, Jong Min Lee
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Patent number: 7858465Abstract: A semiconductor device according to an embodiment of the present invention includes: a transistor including, a gate insulator formed of an insulating layer deposited on a substrate, and a gate electrode formed of an electrode layer deposited on the insulating layer; a capacitor including, a first capacitor electrode formed of the electrode layer, a first capacitor insulator formed on the first capacitor electrode, a second capacitor electrode formed on the first capacitor insulator, a second capacitor insulator formed on the second capacitor electrode, and a third capacitor electrode formed on the second capacitor insulator; and line patterns which are in contact with a contact plug for the transistor, a contact plug for the first capacitor electrode, a contact plug for the second capacitor electrode, and the third capacitor electrode.Type: GrantFiled: February 14, 2008Date of Patent: December 28, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Toshiaki Komukai, Hideaki Harakawa
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Patent number: 7846809Abstract: A method for forming a capacitor of a semiconductor device includes the steps of forming first and second sacrificial insulation layers over a semiconductor substrate divided into first and second regions. The second and first sacrificial insulation layers in the first region are etched to define in the first region of the semiconductor substrate. Storage nodes on surfaces of the holes are formed. A partial thickness of the second sacrificial insulation layer is etched to partially expose upper portions of the storage nodes. A mask pattern is formed to cover the first region while exposing the second sacrificial insulation layer remaining in the second region. The exposed second sacrificial insulation layer in the second region is removed to expose the first sacrificial insulation layer in the second region. The exposed first sacrificial insulation layer in the second region and the first sacrificial insulation layer in the first region is removed. The mask pattern is removed.Type: GrantFiled: December 28, 2007Date of Patent: December 7, 2010Assignee: Hynix Semiconductor Inc.Inventor: Gyu Hyun Kim
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Patent number: 7838385Abstract: A method for manufacturing a reservoir capacitor of a semiconductor device reduces the resistance of the reservoir capacitor to secure reliability of the semiconductor device. The method comprises: forming a dummy pattern having a lattice structure over a transistor; forming a first interlayer insulating film over the resulting structure including the dummy pattern; etching the first interlayer insulating film to form a line-structured storage node contact region between the lattice structures; and filling a conductive layer in the line-structured storage node contact region to form a line-structured storage node contact.Type: GrantFiled: June 21, 2009Date of Patent: November 23, 2010Assignee: Hynix Semiconductor IncInventor: Won Ho Shin
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Patent number: 7824998Abstract: A method includes forming an amorphous carbon layer over a first dielectric layer formed over a substrate, forming a second dielectric layer over the amorphous carbon layer; and forming an opening within the amorphous carbon layer and second dielectric layer by a first etch process to partially expose a top surface of the first dielectric layer. A substantially conformal metal-containing layer is formed over the second dielectric layer and within the opening. The second dielectric layer and a portion of the metal-containing layer are removed. The amorphous carbon layer is removed by an oxygen-containing plasma process to expose a top surface of the first dielectric layer. An insulating layer is formed over the metal-containing layer, and a second metal-containing layer is formed over the insulating layer to form a capacitor.Type: GrantFiled: January 22, 2009Date of Patent: November 2, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yuan-Hung Liu, Ming Chyi Liu, Yeur-Luen Tu, Chi-Hsin Lo, Chia-Shiung Tsai
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Publication number: 20100267215Abstract: In a semiconductor device according to embodiments of the invention, a capacitor includes a storage electrode having a cylindrical storage conductive layer pattern and connecting members formed on the upper portion of the cylindrical storage conductive layer pattern. The connecting member connects to an adjacent connecting member of another storage electrode. A dielectric layer and a plate electrode are successively formed on the storage electrode. All of the capacitors are connected by one another by forming cylindrical storage electrodes so that the storage electrode does not fall down when the capacitors have an extremely large aspect ratio. Thus, the capacitance of the capacitors may be improved to the desired level. A semiconductor device that includes these capacitors may have improved reliability and the throughput of a semiconductor manufacturing process may be increased.Type: ApplicationFiled: April 26, 2010Publication date: October 21, 2010Inventor: Je-Min Park
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Patent number: 7816222Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes cylinder type bottom electrodes connected to a contact plug formed over a semiconductor substrate, and a supporting pattern formed between the cylinder type bottom electrodes, wherein a portion of sidewalls of the bottom electrodes is higher than the supporting pattern and the other portion of the sidewalls of the bottom electrode is lower than the supporting pattern.Type: GrantFiled: May 27, 2008Date of Patent: October 19, 2010Assignee: Hynix Semiconductor Inc.Inventors: Jong Kuk Kim, Seung Bum Kim
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Patent number: 7816202Abstract: A method for fabricating a capacitor includes providing a substrate having a capacitor region is employed, forming a first Ru1?xOx layer over the substrate, forming a Ru layer for a lower electrode over the first Ru1?xOx layer and deoxidizing the first Ru1?xOx layer, forming a dielectric layer over the Ru layer for a lower electrode, and forming a conductive layer for an upper electrode over the dielectric layer, wherein the first Ru1?xOx layer contains oxygen in an amount less than an oxygen amount of a RuO2 layer.Type: GrantFiled: June 27, 2008Date of Patent: October 19, 2010Assignee: Hynix Semiconductor Inc.Inventors: Kwan-Woo Do, Jae-Sung Roh, Kee-Jeung Lee, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim, Kyung-Woong Park
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Patent number: 7807542Abstract: A highly reliable semiconductor device and a method fabricating the same are provided, the semiconductor device having a low resistance electrode structure. The semiconductor device includes an interlayer insulation film formed on a semiconductor substrate. A storage node electrode is formed on the interlayer insulation film. A protection film is formed on the storage node electrode and includes a nitrided metal film. A dielectric film overlies the protection film. A plate electrode is formed on the dielectric film.Type: GrantFiled: November 21, 2006Date of Patent: October 5, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Joo-Byoung Yoon, Jin-Sung Kim, Kyung-Woo Lee, Yeong-Cheol Lee, Sang-Jun Park, Hye-Sun Kim
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Patent number: 7803686Abstract: Methods for selectively etching doped oxides in the manufacture of microfeature devices are disclosed herein. An embodiment of one such method for etching material on a microfeature workpiece includes providing a microfeature workpiece including a doped oxide layer and a nitride layer adjacent to the doped oxide layer. The method include selectively etching the doped oxide layer with an etchant comprising DI:HF and an acid to provide a pH of the etchant such that the etchant includes (a) a selectivity of phosphosilicate glass (PSG) to nitride of greater than 250:1, and (b) an etch rate through PSG of greater than 9,000 ?/minute.Type: GrantFiled: October 12, 2007Date of Patent: September 28, 2010Assignee: Micron Technology, Inc.Inventor: Niraj Rana
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Patent number: 7795147Abstract: The semiconductor storage device comprises memory cell transistors formed on a semiconductor substrate 10; first insulation films 42 covering the top surfaces and the side surfaces of gate electrodes 20 of the memory cell transistors; through-holes 40 opened on first diffused layers 24; a second insulation film 36 with through-holes 40 opened on first diffused layers 24 and through-holes 38 opened on second diffused layers 26 formed in; capacitors formed on the inside walls and the bottoms of the through-holes 40 and including capacitor storage electrodes 46, connected to the first diffused layers 24; capacitor dielectric films 48 covering the capacitor storage electrodes 46, and capacitor-opposed electrodes 54 covering at least a part of the capacitor dielectric films 48; and, contact conducting films 44 formed on the inside walls and bottoms of the through-holes 38, and connected to the second diffused layers.Type: GrantFiled: March 11, 2004Date of Patent: September 14, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Taiji Ema, Tohru Anezaki
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Patent number: 7785962Abstract: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive metal nitride-comprising material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Inner sidewalls of the conductive material within the trench are annealed in a nitrogen-comprising atmosphere. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area. The conductive material within the array area is incorporated into a plurality of capacitors.Type: GrantFiled: February 26, 2007Date of Patent: August 31, 2010Assignee: Micron Technology, Inc.Inventors: Vishwanath Bhat, Kevin R. Shea
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Patent number: 7781298Abstract: A method for forming a capacitor comprises providing a substrate. A bottom electrode material layer is formed on the substrate. A first mask layer is formed on the bottom electrode material layer. A second mask layer is formed on the first mask layer. The second mask layer is patterned to form a patterned second mask layer in a predetermined region for formation of a capacitor. A plurality of hemispherical grain structures are formed on a sidewall of the patterned second mask layer. The first mask layer is etched by using the hemispherical grain structures and the patterned second mask layer as a mask, thereby forming a patterned first mask layer having a pattern. The pattern of the first mask layer is transferred to the bottom electrode material layer. And, a capacitor dielectric layer and a top electrode layer are formed on the bottom electrode material layer to form the capacitor.Type: GrantFiled: July 3, 2008Date of Patent: August 24, 2010Assignee: Industrial Technology Research InstituteInventors: Hengyuan Lee, Lurng-Shehng Lee, Ching Chiun Wang, Pei-Jer Tzeng
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Publication number: 20100207240Abstract: A semiconductor device includes: a stacked body with a plurality of conductive layers and a plurality of dielectric layers alternately stacked therein, the stacked body including a staircase structure having the plurality of conductive layers processed into a staircase shape; an interlayer dielectric layer covering the staircase structure; and a contact electrode provided inside a contact hole penetrating through the interlayer dielectric layer, the contact hole penetrating through one of the staircase-shaped conductive layers, the contact electrode being in contact with a sidewall portion of the one of the staircase-shaped conductive layers exposed into the contact hole.Type: ApplicationFiled: August 21, 2009Publication date: August 19, 2010Inventors: Junichi Hashimoto, Mitsuhiro Omura
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Patent number: 7772082Abstract: A method of fabricating a semiconductor device includes forming a buffer insulating film over a semiconductor substrate including a conductive pattern. The buffer insulating film is etched using a storage node mask to form a buffer insulating pattern exposing the conductive pattern. The buffer insulating pattern defines a region wider than a storage node region. An etch stop film is formed over the conductive pattern and the buffer insulating pattern. An interlayer insulating film is formed over the etch stop film. The interlayer insulating film is etched using the storage node mask to expose the etch stop film. The exposed etch stop film is etched to form the storage node region exposing conductive pattern. A lower storage node is formed over the storage node region.Type: GrantFiled: December 6, 2007Date of Patent: August 10, 2010Assignee: Hynix Semiconductor, Inc.Inventor: Joong Il Choi
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Patent number: 7766981Abstract: Capacitive devices are described having electrical interconnects of electrodes which possess efficient electrical contact between current collectors, electrical isolation of electrodes, and/or electrochemical stability, while minimizing the mechanical stress and strain applied to the electrodes. The capacitive devices are adaptable to a wide range of electrode dimensions and electrode stack heights.Type: GrantFiled: June 26, 2008Date of Patent: August 3, 2010Assignee: Corning IncorporatedInventors: Roy Joseph Bourcier, Todd St. Clair, Andrew Nadjadi, Vitor Marino Schneider
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Patent number: 7759193Abstract: A method of forming a plurality of capacitors includes forming a plurality of individual capacitor electrodes using two masking steps. An earlier of the two masking steps is used to form an array of first openings over a plurality of storage node contacts. A later of the two masking steps is used to form an array of second openings received partially over and partially offset from the array of first openings. Overlapping portions of the first and second openings are received over the storage node contacts. After both of the two masking steps, conductive material of the individual capacitor electrodes is deposited into the overlapping portions of each of the first and second openings. The individual capacitor electrodes are incorporated into a plurality of capacitors. Other aspects and implementations are contemplated.Type: GrantFiled: July 9, 2008Date of Patent: July 20, 2010Assignee: Micron Technology, Inc.Inventor: Fred Fishburn
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Patent number: 7749854Abstract: A self-converged memory material element is created during the manufacture of a memory cell comprising a base layer, with a bottom electrode, and an upper layer having a third, planarization stop layer over the base layer, a second layer over the third layer, and the first layer over the second layer. A keyhole opening is formed through the upper layer to expose the bottom electrode. The first layer has an overhanging portion extending into the opening. A dielectric material is deposited into the keyhole opening so to create a self-converged void within the keyhole opening. An anisotropic etch forms a sidewall of the dielectric material in the keyhole opening with an electrode hole aligned with the void and exposing the bottom electrode. A memory material is deposited into the electrode hole in contact with the bottom electrode and is planarized down to the third layer to create the memory material element.Type: GrantFiled: December 16, 2008Date of Patent: July 6, 2010Assignee: Macronix International Co., Ltd.Inventor: Hsiang Lan Lung
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Patent number: 7749856Abstract: A method of fabricating a storage node with a supported structure is provided. A dielectric stacked comprising an etch stop layer, a first dielectric layer, a support layer and a second dielectric layer is formed on a substrate. An opening is etched into the dielectric stacked. A conductive layer is formed on the second dielectric layer and inside the opening. The conductive layer directly above the second dielectric layer is removed to form columnar node structure. The second dielectric layer is then removed. A spacer layer is deposited on the support layer and the columnar node structure. A tilt-angle implant is performed to implant dopants into the spacer layer. The undoped spacer layer is removed to form a hard mask. The support layer not covered by the hard mask is etched away to expose the first dielectric layer. The first dielectric layer and the hard mask are removed.Type: GrantFiled: September 24, 2008Date of Patent: July 6, 2010Assignee: Nanya Technology Corp.Inventors: Shih-Fan Kuan, Le-Tien Jung
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Publication number: 20100159668Abstract: A method for manufacturing a reservoir capacitor of a semiconductor device reduces the resistance of the reservoir capacitor to secure reliability of the semiconductor device. The method comprises: forming a dummy pattern having a lattice structure over a transistor; forming a first interlayer insulating film over the resulting structure including the dummy pattern; etching the first interlayer insulating film to form a line-structured storage node contact region between the lattice structures; and filling a conductive layer in the line-structured storage node contact region to form a line-structured storage node contact.Type: ApplicationFiled: June 21, 2009Publication date: June 24, 2010Applicant: Hynix Semiconductor Inc.Inventor: Won Ho Shin