Abstract: A method for forming a capacitor comprises providing a substrate. A bottom electrode material layer is formed on the substrate. A first mask layer is formed on the bottom electrode material layer. A second mask layer is formed on the first mask layer. The second mask layer is patterned to form a patterned second mask layer in a predetermined region for formation of a capacitor. A plurality of hemispherical grain structures are formed on a sidewall of the patterned second mask layer. The first mask layer is etched by using the hemispherical grain structures and the patterned second mask layer as a mask, thereby forming a patterned first mask layer having a pattern. The pattern of the first mask layer is transferred to the bottom electrode material layer. And, a capacitor dielectric layer and a top electrode layer are formed on the bottom electrode material layer to form the capacitor.

Abstract: The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least partially dissociated to form gaps extending to the substrate. An electrically conductive surface is formed to extend across the at least partially dissociated layer and within the gaps. The electrically conductive surface has a rugged topography imparted by the at least partially dissociated layer and the gaps. The topographically rugged surface can be incorporated into capacitor constructions. The capacitor constructions can be incorporated into DRAM cells, and such DRAM cells can be incorporated into electrical systems.

Abstract: A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g. ruthenium oxide regions, at grain boundaries of a metal layer, e.g., platinum. Preferably, the metal oxide regions are formed by diffusion of oxygen through grain boundaries of the metal layer, e.g., platinum, to oxidize a metal layer thereon, e.g, ruthenium layer. The structure is particularly advantageous for use in capacitor structures and memory devices, such as dynamic random access memory (DRAM) devices.

Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.

Abstract: The invention includes methods of forming a substrate having a surface comprising at least one of Pt, Pd, Co and Au in at least one of elemental and alloy forms. In one implementation, a substrate is provided which has a first substrate surface comprising at least one of Pt, Pd, Co and Au in at least one of elemental and alloy forms. The first substrate surface has a first degree of roughness. Within a chamber, the first substrate surface is exposed to a PF3 comprising atmosphere under conditions effective to form a second substrate surface comprising at least one of Pt, Pd, Co and Au in at least one of elemental and alloy forms which has a second degree of roughness which is greater than the first degree of roughness. The substrate having the second substrate surface with the second degree of roughness is ultimately removed from the chamber.

Abstract: Described are integrated circuit electrodes and method for fabricating an electrode, which include, in an embodiment forming a silicon, first portion of the electrode in a lower region of a substrate opening. The method may further include forming a second portion of the electrode in the opening and overlying the first portion, the insulative layer encompassing a sidewall of the second portion. The method may further include forming a third portion of the electrode overlying the second portion and overlying at least a portion of the insulative layer, wherein the first portion and the second portion are different materials. In an embodiment, the second portion is a diffusion barrier layer and the third portion is an oxidation resistant layer. In an embodiment, the method includes encompassing a lower sidewall of the third portion with the insulative layer.

Abstract: An integrated circuit device structure (and methods). The structure includes a semiconductor substrate comprising a surface. A first doped polysilicon liner is defined within a first trench region formed on a first plug coupled to the surface of the substrate and a second doped polysilicon liner is defined within a second trench region on a second plug coupled to the surface of the substrate. The first trench region is separated from the second trench region by a predetermined dimension. The structure also has a first rugged polysilicon material overlying surfaces of the first doped polysilicon material within the first trench region and a second rugged polysilicon material overlying surfaces of the second doped polysilicon material in the second trench region. The first rugged polysilicon material is free from a possibility of electrical contact with the second rugged polysilicon material.

Abstract: In a storage electrode of a semiconductor device, and a method of forming the same, the storage electrode includes an outer cylinder including a first outer cylindrical portion having a first outer diameter, and a second outer cylindrical portion that is formed on the first outer cylindrical portion and having a second outer diameter, which is less than the first outer diameter, the first and second outer cylindrical portions having substantially equal inner diameters, and an inner cylinder formed on inner surfaces of the outer cylinder.

Abstract: Systems, devices, structures, and methods are described that inhibit dielectric degradation at high temperatures. An enhanced capacitor is discussed. The enhanced capacitor includes a first electrode, a dielectric that includes ditantalum pentaoxide, and a second electrode having a compound. The compound includes a first substance and a second substance. The second electrode includes a trace amount of the first substance. The morphology of the semiconductor structure remains stable when the trace amount of the first substance is oxidized during crystallization of the dielectric. In one embodiment, the crystalline structure of the dielectric describes substantially a (001) lattice plane.

Abstract: A polysilicon film is formed with enhanced selectivity by flowing chlorine during the formation of the film. The chlorine acts as an etchant to insulative areas adjacent polysilicon structures on which the film is desired to be formed. Bottom electrodes for capacitors are formed using this process, followed by an anneal to create hemishperical grain (HSG) polysilicon. Multilayer capacitor containers are formed in a non-oxidizing ambient so that no oxide is formed between the layers. The structure formed is planarized to form separate containers made from doped and undoped amorphous silicon layers. Selected ones of undoped layers are seeded in a chlorine containing environment and annealed to form HSG. A dielectric layer and second electrode are formed to complete the cell capacitor.

Abstract: A RF MOS- or nonlinear device-based surveillance and/or identification tag, and methods for its manufacture and use. The tag generally includes (a) an inductor, (b) a first capacitor plate coupled to the inductor, (c) a dielectric film on the first capacitor plate, (d) a semiconductor component on the dielectric film, and (e) a conductor that provides electrical communication between the semiconductor component and the inductor. The method of manufacture generally includes (1) depositing a semiconductor material (or precursor) on a dielectric film; (2) forming a semiconductor component from the semiconductor material/precursor; (3) forming a conductive structure at least partly on the semiconductor component; and (4) etching the electrically functional substrate to form (i) an inductor and/or (ii) a second capacitor plate.

Abstract: The invention includes a method of forming a semiconductor construction. A semiconductor substrate is provided, and a conductive node is formed to be supported by the semiconductor substrate. A first conductive material is formed over the conductive node and shaped as a container. The container has an opening extending therein and an upper surface proximate the opening. The container opening is at least partially filled with an insulative material. A second conductive material is formed over the at least partially filled container opening and physically against the upper surface of the container. The invention also includes semiconductor structures.

Abstract: The invention includes a method of depositing a noble metal. A substrate is provided. The substrate has a first region and a second region. The first and second regions are exposed to a mixture comprising a precursor of a noble metal and an oxidant. During the exposure, a layer containing the noble metal is selectively deposited onto the first region relative to the second region. In particular applications, the first region can comprise borophosphosilicate glass, and the second region can comprise either aluminum oxide or doped non-oxidized silicon. The invention also includes capacitor constructions and methods of forming capacitor constructions.

Abstract: Capacitors for use in an integrated circuit are provided. One aspect of this disclosure relates to a method of making a capacitor. According to various embodiments of the method a bottom electrode adapted to act as an etch stop is formed, a substantially cone-shaped first plate of conductive material is formed having an interior and exterior surface and terminating at the bottom electrode, a layer of dielectric material is formed on at least a portion of the interior and exterior surface of the first plate and substantially conforming to the shape of the first plate, and a second plate of conductive material is formed over the layer of dielectric material. Other aspects and embodiments are provided herein.

Abstract: A capacitor fabrication method may include atomic layer depositing a conductive barrier layer to oxygen diffusion over the first electrode. A method may instead include chemisorbing a layer of a first precursor at least one monolayer thick over the first electrode and chemisorbing a layer of a second precursor at least one monolayer thick on the first precursor layer, a chemisorption product of the first and second precursor layers being comprised by a layer of a conductive barrier material. The barrier layer may be sufficiently thick and dense to reduce oxidation of the first electrode by oxygen diffusion from over the barrier layer. An alternative method may include forming a first capacitor electrode over a substrate, the first electrode having an inner surface area per unit area and an outer surface area per unit area that are both greater than an outer surface area per unit area of the substrate. A capacitor dielectric layer and a second capacitor electrode may be formed over the dielectric layer.

Abstract: Disclosed is a method for forming a capacitor of a semiconductor device. An etch stop layer, first oxide layer and second oxide layer are sequentially deposited on an insulating interlayer of a substrate. Contact holes through which portions of the etch stop layer are exposed above plugs of the insulating interlayer are formed. The contact holes are cleaned by a cleaning solution having an etching selectivity which is higher for the first oxide layer than for the second oxide layer, thereby enlarging lower portions of the contact holes. A spacer nitride layer is formed on surfaces of the contact holes and the second oxide layer. Portions of the spacer nitride layers located on the second oxide layer and above the plugs together with portions of the etch stop layer located on the plugs are removed. A double polysilicon layer is formed on the spacer nitride layer segments.

Abstract: A capacitor for a semiconductor device includes a lower electrode, a dielectric layer formed on a lower electrode, and an upper electrode formed on the dielectric layer. The lower electrode includes a first layer having a cylindrical shape and a mesh second layer formed on inner sidewalls and the bottom surface of the first layer. Beneficially, the first layer is connected to a conductive region of a semiconductor substrate by a contact plug. The lower electrode can be formed by injecting a catalyst into an opening in which the cylindrical first layer is to be formed before forming the cylindrical first layer.

Abstract: Thin film metal-insulator-metal capacitors having enhanced surface area are formed by a substituting metal for silicon in a preformed electrode geometry. The resulting metal structures are advantageous for high-density DRAM applications since they have good conductivity, enhanced surface area and are compatible with capacitor dielectric materials having high dielectric constant.

Abstract: Disclosed herein is a method of forming a reliable high performance capacitor using an isotropic etching process to optimize the surface area of the lower electrodes while preventing an electrical bridge from forming between the lower electrodes. This method includes multiple sacrificial oxide layers that are formed over a substrate, an insulating layer with contact plugs, and an etch stopping layer. The sacrificial oxide layers are patterned and additionally isotropically etched to form an expanded capacitor hole. An exposed portion of the etch stopping layer is then etched to form a final capacitor hole exposing an upper portion of the contact plug and a portion of the insulating layer adjacent thereto. The semiconductor substrate having the final capacitor hole is cleaned to remove a native oxide film on the exposed upper portion of the contact plug.

Abstract: Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the capacitor. The semiconductor structure also includes a relatively smooth surface abutting the rough surface, wherein the relatively smooth surface is formed from a polycrystalline material.

Abstract: In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from being adsorbed onto the surface of the first conductive layer. In one embodiment, a second conductive layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates an oxide formed between the two layers as a result of subsequent thermal treatments. In another embodiment, a dielectric layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates the ability of the first conductive layer to incorporate oxygen from the dielectric.

Abstract: A method of forming a device is disclosed. The method includes forming a capacitor, and forming the capacitor includes forming a first electrode. The first electrode includes at least one non-smooth surface and is formed from a material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof. Forming the capacitor also includes forming a dielectric on the first electrode, and forming a second electrode on the dielectric. The second electrode includes at least one non-smooth surface.

Abstract: The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric. The present invention further discloses a device including a substrate; a lower conductor located over the substrate; a conducting nanostructure located over the lower conductor; a thin dielectric located over the conducting nanostructure; and an upper conductor located over the thin dielectric.

Abstract: Provided herein are vertical nanotube semiconductor devices and methods for making the same. An embodiment of the semiconductor devices comprises a vertical transistor/capacitor cell including a nanotube. The device includes a vertical transistor and a capacitor cell both using a single nanotube to form the individual devices.

Abstract: The present invention refers to a method of forming a silicon dioxide layer by thermally oxidizing at least one monocrystalline silicon surface region on a semiconductor substrate. The silicon surface region has a curved surface. The method can include providing a semiconductor substrate having at least one monocrystalline silicon surface region having a curved surface, roughening the surface of the at least one monocrystalline silicon surface region to produce a layer of porous silicon, and thermally oxidizing the at least one roughened monocrystalline silicon surface.

Abstract: Capacitors, DRAM circuitry, and methods of forming the same are described. In one embodiment, a capacitor comprises a first container which is joined with a substrate node location and has an opening defining a first interior area. A second container is joined with the node location and has an opening defining a second interior area. The areas are spaced apart from one another in a non-overlapping relationship. A dielectric layer and a conductive capacitor electrode layer are disposed operably proximate the first and second containers. In another embodiment, the first and second containers are generally elongate and extend away from the node location along respective first and second central axes. The axes are different and spaced apart from one another. In yet another embodiment, a conductive layer of material is disposed over and in electrical communication with a substrate node location. The layer of material has an outer surface with a first region and a second region spaced apart from the first region.

Abstract: The invention includes a method of forming a semiconductor construction. A semiconductor substrate is provided, and a conductive node is formed to be supported by the semiconductor substrate. A first conductive material is formed over the conductive node and shaped as a container. The container has an opening extending therein and an upper surface proximate the opening. The container opening is at least partially filled with an insulative material. A second conductive material is formed over the at least partially filled container opening and physically against the upper surface of the container. The invention also includes semiconductor structures.

Abstract: A method of forming a roughened layer of platinum, including: a) providing a substrate within a reaction chamber; b) forming an adhesion layer over the substrate; c) flowing an oxidizing gas into the reaction chamber; d) flowing a platinum precursor into the reaction chamber and depositing platinum from the platinum precursor onto the adhesion layer in the presence of the oxidizing gas; and e) maintaining a temperature within the reaction chamber at from about 0° C. to less than 300° C. during the depositing.

Abstract: The invention provides robust and cost effective techniques to fabricate a semiconductor device having double-sided hemispherical silicon grain (HSG) electrodes for container capacitors. In an embodiment, this is accomplished by forming a layer of hemispherical silicon grain (HSG) polysilicon over interior surfaces of a container formed in a substrate. Any HSG polysilicon and barrier layers formed over the substrate and around the container opening during the forming of the HSG polysilicon and barrier layers are removed. An inside surface of the formed HSG polysilicon layer is nitridized to form a nitridation layer. A layer of cell nitride is deposited over the nitridation layer and the outside HSG polysilicon layer. A top electrode is formed over the deposited cell nitride layer.

Abstract: A method of forming a capacitor is disclosed. The method includes forming a first substrate layer, and forming a first electrode on the first substrate layer. The first electrode includes at least one non-smooth surface and is formed from a material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof. The method also includes forming a dielectric on the first electrode and the first substrate layer, and forming a second electrode on the dielectric and the first substrate layer. The second electrode includes at least one non-smooth surface. The method further includes forming a second substrate layer on the second electrode.

Abstract: In one embodiment, a first transistor is configured to switch ON to discharge accumulated charges on an interconnect line during a metallization process. This advantageously protects a second transistor, which is coupled to the interconnect line, from charge buildup. The gate of the first transistor may be coupled to the interconnect line by way of a coupling capacitor. The gate of the first transistor may remain floating during the metallization process, and subsequently coupled to ground at a topmost metal level. The metallization process may be physical vapor deposition, for example.

Abstract: Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the capacitor. The semiconductor structure also includes a relatively smooth surface abutting the rough surface, wherein the relatively smooth surface is formed from a polycrystalline material.

Abstract: A method for fabricating a semiconductor device capable of preventing an electric short between lower electrodes caused by leaning lower electrodes, or lifted lower electrodes and of securing a sufficient capacitance of a capacitor by increasing an effective capacitor area. The method includes the steps of: preparing a semi-finished semiconductor substrate; forming a sacrificial layer on the semi-finished semiconductor substrate; patterning the sacrificial layer by using an island-type photoresist pattern, thereby obtaining at least one contact hole to expose portions of the semi-finished semiconductor substrate; and forming a conductive layer on the sacrificial layer.

Abstract: An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to the dielectric formation, the hemispherical grained polysilicon layer may be optionally subjected to a nitridization or anneal process. A dielectric layer of aluminum oxide (Al2O3), or a composite stack of interleaved layers of aluminum oxide and other metal oxide dielectric materials, is fabricated over the hemispherical grained polysilicon layer and after the optional nitridization or anneal process. The dielectric layer of aluminum oxide (Al2O3) or the aluminum oxide composite stack may be optionally subjected to a post-deposition treatment to further increase the capacitance and decrease the leakage current. A metal nitride upper electrode is formed over the dielectric layer or the composite stack by a deposition technique or by atomic layer deposition.

Abstract: A method of forming a capacitor is disclosed. The method includes forming a substrate assembly, and forming a first electrode on the substrate assembly. The first electrode includes at least one non-smooth surface and is formed from a material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof. The method further includes forming a dielectric on the first electrode and an uppermost surface of the substrate assembly, and forming a second electrode on the dielectric and the uppermost surface of the substrate assembly. The second electrode includes at least one non-smooth surface.

Abstract: A process for forming a DRAM stacked capacitor structure with increased surface area, has been developed. The process features forming lateral grooves in the sides of a polysilicon storage node structure, during a dry etching procedure used to define the storage node structure. The grooves are selectively, and laterally formed in ion implanted veins, which in turn had been placed at various depths in an intrinsic polysilicon layer via a series of ion implantation steps, each performed at a specific implant energy. An isotopic component of the storage node structure, defining dry etch procedure, selectively etches the highly doped, ion implanted veins at a greater rate than the non-ion implanted regions of polysificon, located between the ion implanted veins, resulting in a necked profile, storage node structure, featuring increased surface area as a result of the formation of the lateral grooves.

Abstract: The present invention provides a method of preparing a surface of a silicon wafer for formation of HSG structures. The method contemplates providing a wafer having at least one HSG template comprising polysilicon formed in BPSG, the HSG template being covered by silicon dioxide. The wafer is treated with a cleaning agent to clean the surface of the wafer. Next, the wafer is treated with a conditioning agent. The conditioning agent removes native oxide from the HSG template without excessively etching structural BPSG. Preferably, the conditioning agent also removes a thin layer of polysilicon on the HSG template. The wafer is then transferred to a process chamber for HSG formation.

Abstract: Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.

Abstract: A phase changeable memory device includes a substrate having a lower electrode disposed thereon. A phase changeable pattern is disposed on the lower electrode and an upper electrode is disposed on the phase changeable pattern that has a tip that extends therefrom and is directed toward the lower electrode.

Abstract: The present invention provides a method for forming an improved dielectric layer for semiconductor devices such as gate structures and capacitors. The method utilizes a layer of (TaO)1?x(TiO)xN (x defined herein) as a substitute for SiO2, together with one or more additional procedures to minimize or prevent channel leakage and other problems that can minimize the performance of the structure.

Abstract: On a silicon oxide film including the interior of an opening a semispherical RGP film is deposited. At a temperature lower than that allowing a crystal of silicon to be grown a BPTEOS film is deposited to fill the opening. Then a portion other than the semispherical RGP film introduced in the opening is chemically mechanically polished and thus removed. This contributes to reduced crystal growth of silicon at the semispherical RGP film and hence reduced scattering and/or removal of the RGP film for example when a CMP step is performed. Subsequently the semispherical RGP film is annealed to grow a crystal of silicon to form a generally spherical RGP film. Thus a storage node can have an increased surface area and a capacitor can have increased capacity.

Abstract: A method is taught for applying and accurately locating a plurality of caps to a plurality of microfabricated devices at the wafer stage. The method involves using a two part mold to make a plurality of first hollow molded caps. The caps are made from a layer of thermoplastic material which is placed in the mold. Each cap having a central portion and a perimeter wall. The mold is opened so that the caps are carried by the first half. The caps are applied to a wafer using the first half. After the caps are applied, the wafer may be separated into individual chips.

Abstract: The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least partially dissociated to form gaps extending to the substrate. An electrically conductive surface is formed to extend across the at least partially dissociated layer and within the gaps. The electrically conductive surface has a rugged topography imparted by the at least partially dissociated layer and the gaps. The topographically rugged surface can be incorporated into capacitor constructions. The capacitor constructions can be incorporated into DRAM cells, and such DRAM cells can be incorporated into electrical systems.

Abstract: Methods of forming conductive capacitor plugs, methods of forming capacitor contact openings, and methods of forming memory arrays are described. In one embodiment, a conductive capacitor plug is formed to extend from proximate a substrate node location to a location elevationally above all conductive material of an adjacent bit line. In another embodiment, a capacitor contact opening is etched through a first insulative material received over a bit line and a word line substantially selective relative to a second insulative material covering portions of the bit line and the word line. The opening is etched to a substrate location proximate the word line in a self-aligning manner relative to both the bit line and the word line. In another embodiment, capacitor contact openings are formed to elevationally below the bit lines after the bit lines are formed. In a preferred embodiment, capacitor-over-bit line memory arrays are formed.

Abstract: An MTJ (magnetic tunneling junction) device particularly suitable for use as an MRAM (magnetic random access memory) or a tunneling magnetoresistive (TMR) read sensor, is formed on a seed layer which allows the tunneling barrier layer to be ultra-thin, smooth, and to have a high breakdown voltage. The seed layer is a layer of NiCr which is formed on a sputter-etched layer of Ta. The tunneling barrier layer for the MRAM is formed from a thin layer of Al which is radically oxidized (ROX), in-situ, to form the layer with characteristics described above. The tunneling barrier layer for the read sensor formed from a thin layer of Al or a HfAl bilayer which is naturally oxidized (NOX), in situ, to form the barrier layer. The resulting device has generally improved performance characteristics in terms of GMR ratio and junction resistance.

Abstract: A capacitor including a first electrode selected from a group consisting of transition metals, conductive metal-oxides, alloys thereof, and combinations thereof. The capacitor also includes a second electrode and a dielectric between the first and second electrodes. The present invention may be used to form devices, such as memory devices and processors. The present invention also includes a method of making a capacitor. The method includes forming a first electrode selected from a group consisting of transition metals, conductive metal-oxides, and alloys thereof. The method also includes forming a second electrode and forming a dielectric between the first and second electrodes.

Abstract: An apparatus and method for forming a HSG silicon layer on a capacitor lower electrode of a semiconductor memory device. The apparatus includes a processing chamber having a plurality of source gas supply nozzles, the lengths of the nozzles being different from one another so as to uniformly supply a source gas. A loadlock chamber is placed under the processing chamber. A boat loaded with wafers is moved from the loadlock chamber to the processing chamber, with the boat being rotated while the source gas is supplied. The processing chamber and loadlock chambers are connected to a vacuum system having two vacuum pumps for maintaining a vacuum in the chambers. A third vacuum pump, connected to the processing chamber, is operated when the vacuum in the processing chamber reaches a predetermined value.

Abstract: Disclosed is a method for depositing a silicon nitride layer of a semiconductor device. The method includes the steps of providing Al-based compound as a catalyst, and reacting DCS with NH3 by using the Al catalyst, thereby depositing the silicon nitride layer. DCS is reacted with NH3 by using the Al catalyst when depositing the silicon nitride layer, so dissolution of DCS is promoted by means of the Al catalyst, so that the silicon nitride layer is deposited at a high speed, thereby improving productivity of semiconductor devices. The silicon nitride layer is deposited by using DCS under a low-temperature condition of about 500 to 800° C., without deteriorating device characteristics.

Abstract: Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjacent container structures. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: A hemispherical grain (HSG) formation process for enlarging the surface area of a capacitor electrode, wherein stable, defect-free HSG, having outstanding selectivity, is formed. An amorphous silicon layer, which constitutes a capacitor electrode, is formed on an Si wafer, on which is formed a silicon-based dielectric layer, which constitutes an interlevel dielectric layer. An HSG layer, in which there exists practically no defects, is formed on the amorphous silicon layer at a crystal nuclei formation temperature of under 620° C. Further, in accordance with properly controlling the crystal nuclei formation temperature, and the flow rate of monosilane (SiH4), which is supplied for crystal nuclei formation, it is possible to furnish selectivity such that HSG nuclei are formed solely on the amorphous silicon layer, without being formed on a silicon-based dielectric layer.