Abstract: A semiconductor wafer has a main surface. A main chip region is formed on the main surface. A sub-chip region is smaller in area than the main chip region, and positioned on an edge side of the semiconductor wafer relative to the main chip region. The sub-chip region is identical to the main chip region in design pattern. Accordingly, a semiconductor device in which occurrence of a pattern failure at the edge of the wafer can be prevented when chips are arranged in the surface of the semiconductor wafer and a method of manufacturing the same can be obtained.

Abstract: A method for registering a pattern on a semiconductor wafer with an oxide surface includes etching into the surface four sets of two trenches each. Each trench in a set is parallel to the other. The trenches are configured such that each set forms one side of a box shape. The trenches are overfilled with a first metal layer, the excess of which is removed so that the height of the metal is level with the height of the oxide. An overlay setting is then obtained between a photoresist mask and the filled trenches before depositing a second metal layer over the oxide and trenches. The second metal layer is coated with the photoresist according to the overlay setting.

Abstract: A method for fabricating a backside illuminated image sensor is provided. An exemplary method can include providing a substrate with a front surface and a back surface; forming a first alignment mark for global alignment on the front surface of the substrate; forming a second alignment mark for fine alignment in a clear-out region on the front surface of the substrate; aligning the substrate from the back surface using the first alignment mark; and removing a portion of the back surface of the substrate at the clear-out region for locating the second alignment mark.

Abstract: A semiconductor substrate is provided in which an alignment mark is formed that can be used for an aligment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an N+-type substrate. This trench is used to leave voids after the formation of an N?-type layer. Then, the voids formed in the N+-type substrate can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.

Abstract: The generation of an identification number of a chip supporting at least one integrated circuit, including the step of causing a cutting of at least one conductive section by cutting of the chip among several first conductive sections parallel to one another and perpendicular to at least one edge of the chip, the first sections being individually connected, by at least one of their ends, to the chip, and exhibiting different lengths, the position of the cutting line with respect to the chip edge conditioning the identification number.

Abstract: A substrate for forming a semiconductor layer includes a plurality of linear convexes or grooves on a surface of the substrate by crystal growth. The plurality of linear convexes or grooves are formed along a direction of a cleavage plane of the semiconductor layer.

Abstract: A backside illuminated image sensor comprises a sensor layer implementing a plurality of photosensitive elements of a pixel array, and an oxide layer adjacent a backside surface of the sensor layer. The sensor layer comprises a seed layer and an epitaxial layer formed over the seed layer, with the seed layer having a cross-sectional doping profile in which a designated dopant is substantially confined to a pixel array area of the sensor layer. The doping profile advantageously reduces dark current generated at an interface between the sensor layer and the oxide layer. The image sensor may be implemented in a digital camera or other type of digital imaging device.

Abstract: A semiconductor device includes an SOI substrate, a first STI-type isolation region, a second STI-type isolation region, and an alignment mark region. The SOI substrate includes a support substrate, an insulating layer deposited on the support substrate, and a semiconductor layer which includes a thin film region and a thick film region. The thin film region includes a first semiconductor layer deposited on the support substrate, and the thick film region includes the first semiconductor layer and a second semiconductor layer deposited on a part of the first semiconductor layer. The first STI-type isolation region is disposed at the thin film region. The second STI-type isolation region is disposed at the thick film region. The alignment mark region is disposed at the thick film region. An alignment mark to be used for alignment of the second STI-type isolation region is disposed at the alignment mark region.

Abstract: An overlay target on a substrate is disclosed, the overlay target including a periodic array of structures wherein every nth structure is different from the rest of the structures. The periodic array is desirably made of two interlaced gratings, one of the gratings having a different pitch from the other grating in order to create an asymmetry in the array. This asymmetry can then be measured by measuring the diffraction spectra of radiation reflected from the overlay target. Variation in the asymmetry indicates the presence of an overlay error in layers on the substrate, where overlay targets are printed on subsequent layers.

Abstract: According to the present invention, there is provided a semiconductor device fabrication method comprising, bringing a mold having a predetermined pattern into contact with at least a portion of an imprinting material formed on a substrate to be processed, and forming the pattern on the substrate to be processed by sequentially transferring the pattern for each shot, wherein one of a dicing region and a monitor pattern formation region of the substrate to be processed is coated with the imprinting material.

Abstract: A self-alignment method for a recess channel dynamic random access memory includes providing a substrate with a target layer, a barrier layer and a lining layer, wherein the target layer has shallow trench isolation structures; patternizing the lining layer, barrier layer and target layer to form recess trench channels; depositing a dielectric layer onto the recess trench channel; forming an ion doped region in the target layer; removing a portion of the dielectric layer to expose a portion of the recess trench channel; forming a filler layer covered onto the recess trench channel; removing a portion of the filler layer to expose a portion of the recess trench channel; forming a passivation layer onto the recess trench channel; removing the passivation layer on the lining layer; and removing the lining layer to form a plurality of structural monomers disposed at the recess trench channel and protruded from the target layer.

Abstract: A method includes determining relative positional relationships between applied fields on a substrate, one of the applied fields including a first field; in a lithographic apparatus, using an alignment apparatus to obtain at least one absolute positional relationship between the position of at least the first field of the substrate and a part of the lithographic apparatus; and determining an absolute positional relationship between at least one field, other than the first field, and a part of the lithographic apparatus using the relative positional relationships and the at least one obtained absolute relationship.

Abstract: A semiconductor package comprising alignment members is provided. The semiconductor package includes a semiconductor die, first connection terminals disposed on a first surface of the semiconductor die, and a tape substrate including a substrate portion, and second connection terminals disposed on the substrate portion and disposed corresponding to the first connection terminals. The semiconductor package further includes a first alignment member disposed on the first surface of the semiconductor die, and a second alignment member disposed on the substrate portion of the tape substrate and disposed corresponding to the first alignment member.

Abstract: A compound semiconductor is placed in a reaction vessel (12) of which the inner gas is subjected to replacement with a low-vapor-pressure gas (2) whose equilibrium vapor pressure at the melting point of the compound semiconductor is 1 atm or lower. The low-vapor-pressure gas is urged to flow along the surface of the compound semiconductor while keeping the internal pressure of the reaction vessel at a value not lower than that equilibrium vapor pressure. The surface of the compound semiconductor is irradiated with a pulsed-laser light (3) whose photon energy is higher than the band gap of the compound semiconductor. Thus, only that part of the compound semiconductor which is located at the pulsed-laser light irradiation position is instantly heated and melted while keeping the atmospheric temperature of the low-vapor-pressure gas at a room temperature or a temperature equal to or lower than the decomposition temperature.

Abstract: The chip for the multi-chip semiconductor device having the markings for alignment formed on the front surface and/or the back surface of the chip only by the processing from the front surface of the chip (photolithography, etch) and the method for manufacturing same are presented, without adding any dedicated process step to the formation process for the marking for alignment. In the chip for the multi-chip semiconductor device having two or more electroconductive through plug in one chip for the multi-chip semiconductor device, one or more electroconductive through plugs are employed for the marking for alignment, and the chip is configured to allow identification of the marking for alignment on the front surface and/or the back surface of the chip for the multi-chip semiconductor device. Then, an insulating film is provided on the front surface and/or the back surface of the electrically conducting through plug.

Abstract: The invention includes a lithographic system having a first source for generating radiation with a first wavelength and an alignment system with a second source for generating radiation with a second wavelength. The second wavelength is larger than the first wavelength. A marker structure is provided having a first layer and a second layer. The second layer is present either directly or indirectly on top of said first layer. The first layer has a first periodic structure and the second layer has a second periodic structure. At least one of the periodic structures has a plurality of features in at least one direction with a dimension smaller than 400 nm. Additionally, a combination of the first and second periodic structure forms a diffractive structure arranged to be illuminated by radiation with the second wavelength.

Abstract: An alignment system for a lithographic apparatus has a source of alignment radiation; a detection system that has a first detector channel and a second detector channel; and a position determining unit in communication with the detection system. The position determining unit is constructed to process information from said first and second detector channels in a combination to determine a position of an alignment mark on a work piece, the combination taking into account a manufacturing process of the work piece. A lithographic apparatus has the above mentioned alignment system. Methods of alignment and manufacturing devices with a lithographic apparatus use the above alignment system and lithographic apparatus, respectively.

Abstract: An overlay mark for determining the relative shift between two or more successive layers of a substrate and methods for using such overlay mark are disclosed. In one embodiment, the overlay mark includes at least one test pattern for determining the relative shift between a first and a second layer of the substrate in a first direction. The test pattern includes a first set of working zones and a second set of working zones. The first set of working zones are disposed on a first layer of the substrate and have at least two working zones diagonally opposed and spatially offset relative to one another. The second set of working zones are disposed on a second layer of the substrate and have at least two working zones diagonally opposed and spatially offset relative to one another. The first set of working zones are generally angled relative to the second set of working zones thus forming an “X” shaped test pattern.

Abstract: A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields.

Abstract: A substrate for fixing an integrated circuit element includes: a plurality of metal columns that are aligned in a longitudinal direction and a lateral direction in a planar view, each of the plurality of metal columns having a first face and a second face facing opposite direction to the first face; and a connecting part that connects the plurality of metal columns one another at a part of each of the plurality of metal columns between the first face and the second face. In the substrate, a recognition mark is formed on the first face of one of the plurality of metal columns.

Abstract: An aligning method of patterned electrode in a selective emitter structure includes the following steps. A substrate is provided. A barrier layer is then formed on the substrate. The barrier layer is patterned, and thus the substrate is partially exposed to form a patterned electrode region. Thereafter, the surface property of the substrate located in the patterned electrode region is changed, so as to form a visible patterned mark. Subsequently, the barrier layer is removed, and the visible patterned mark is used as alignment mark.

Abstract: An integrated circuit includes a visually discernable indicator formed as part of the integrated circuit to indicate a directionality of a non-visually discernable characteristic of the integrated circuit.

Abstract: A semiconductor device includes a semiconductor substrate of n-type silicon including, in an upper portion thereof, a first polarity inversion region and a second polarity inversion regions spaced from each other and doped with a p-type impurity. A first HFET including a first active layer and a second HFET including a second active layer both made of a group III-V nitride semiconductor are independently formed on the respective polarity inversion regions in the semiconductor substrate, and the HFETs are electrically connected to each other through interconnects.

Abstract: In a portion of a gate signal line and a portion of a common signal line, cutouts which are arranged perpendicular to the extending direction of these lines and open to face each other in an opposed manner are formed. A cruciform shape in appearance is formed by combining a gap defined between the gate signal line and the common signal line extending parallel to each other and the cutouts to each other. The cruciform portion formed in this manner is used as an alignment mark in the exposure of a photolithography step of a layer formed later. Due to such a constitution, in manufacturing a thin film transistor substrate, it is possible to realize the highly accurate alignment without forming a pattern only used for alignment.

Abstract: The present invention relates to a CO2 laser-transparent material having a mark on the surface thereof and the method for making the same. The method includes the following steps: providing a first substrate, which has a top surface and a bottom surface; providing a second substrate which has a top surface; putting the bottom surface of the first substrate on the top surface of the second substrate; irradiating a CO2 laser beam to the top surface of the second substrate by passing through the top surface and the bottom surface of the first substrate; and forming a mark on the bottom surface of the first substrate. The material of the mark is oxide of the second substrate or the same as the material of the second substrate. Whereby the cheap CO2 laser is utilized to form the mark on the first substrate, and the mark can be erased easily by a proper chemical for recycling the first substrate.

Abstract: In an overlay metrology method used during semiconductor device fabrication, an overlay alignment mark facilitates alignment and/or measurement of alignment error of two layers on a semiconductor wafer structure, or different exposures on the same layer. A target is small enough to be positioned within the active area of a semiconductor device combined with appropriate measurement methods, which result in improved measurement accuracy.

Abstract: A method of measuring warpage of a rear surface of a substrate includes a substrate detection step, a best fit plane calculation step, and a warpage calculation step. Further, the method of measuring warpage of a rear surface of a substrate can further includes after the substrate detection step and before the best fit plane calculation step: a noise removal step and an outer peripheral portion removal step; the outer peripheral portion removal step and a smoothing step; or the noise removal step, the outer peripheral portion removal step, and the smoothing step. Thereby, a method of measuring warpage of a rear surface with a high surface roughness of a substrate can be provided.

Abstract: Semiconductor lasers, such as VCSELs having active regions with flattening layers associated with nitrogen-containing quantum wells are disclosed. MEE (Migration Enhanced Epitaxy) is used to form a flattening layer upon which a quantum well is formed and thereby enhance smoothness of quantum well interfaces and to achieve narrowing of the spectrum of light emitted from nitrogen containing quantum wells. A cap layer is also formed over the quantum well.

Abstract: A system and method of manufacturing a semiconductor device lithographically and an article of manufacture involving a lithographic double patterning process having a dye added to either the first or second lithographic pattern are provided. The dye is used to detect the location of the first lithographic pattern and to directly align the second lithographic pattern to it. The day may be fluorescent, luminescent, absorbent, or reflective at a specified wavelength or a given wavelength band. The wavelength may correspond to the wavelength of an alignment beam. The dye allows for detection of the first lithographic pattern even when it is over coated with a radiation sensitive-layer (e.g., resist).

Abstract: Exact alignment of a recrystallized region, which is to be formed in an amorphous or polycrystalline film, is facilitated. An alignment mark is formed, which is usable in a step of forming an electronic device, such as a thin-film transistor, in the recrystallized region. In addition, in a step of obtaining a large-grain-sized crystal-phase semiconductor from a semiconductor film, a mark structure that is usable as an alignment mark in a subsequent step is formed on the semiconductor film in the same exposure step. Thus, the invention includes a light intensity modulation structure that modulates light and forms a light intensity distribution for crystallization, and a mark forming structure that modulates light and forms a light intensity distribution including a pattern with a predetermined shape, and also forms a mark indicative of a predetermined position on a crystallized region.

Abstract: Disclosed is a method and a system for forming alignment marks on a transparent substrate. A light reflective layer is deposited over an optically transparent substrate of a wafer. A region is defined around an alignment mark on the optically transparent substrate. The light reflective layer is removed from a substantial portion of the transparent substrate excluding the region. In addition, a micro electro-mechanical systems device is disclosed. The device comprises an optically transparent substrate, at least one optically partially transparent alignment mark on the optically transparent substrate, and a plurality of reflective elements or imaging pixels attached to the optically transparent substrate.

Abstract: A semiconductor device and a method for manufacturing the same prevents copper from being exposed to a surface of a passivation film after a copper metal line formation, to avoid contamination of processing equipment and the process environment. The method includes providing a substrate with a scribe lane and a chip area in which metal wiring layers are formed, forming a dielectric film, forming a conductive film on the dielectric film in a chip area and an alignment mark on the dielectric film in a scribe lane, forming passivation films, exposing the conductive film by removing the passivation films in a bonding pad portion in a chip area, forming another conductive film in the bonding pad portion to electrically connect with the conductive film, forming another passivation film, and selectively removing the passivation films.

Abstract: An alignment target with geometry designs provides a desired alignment offset for processes (both symmetric and asymmetric) on a wafer substrate. The alignment target includes one or more sub-targets, where each sub-target is defined as having a left portion and a right portion having a different geometric pattern, and where the left portion has a geometry density and the right portion has a geometry density.

Abstract: A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of said metal layers, wherein said monocrystalline layer comprises second alignment marks; and performing a lithography using an alignment based on a misalignment between said first alignment marks and said second alignment marks.

Abstract: Dicing structures for semiconductor substrates and methods of fabrication thereof are described. In one embodiment, a semiconductor wafer includes a first chip disposed in a substrate, a second chip disposed adjacent the first chip and disposed in the substrate, and a dicing street disposed between the first and the second chip. A first and a second metal level are disposed over the dicing street, wherein the second metal level is disposed above the first metal level. A first alignment mark is disposed in the first metal level above a first portion of the dicing street, and first metal features disposed in the second metal level above the first portion of the dicing street.

Abstract: Different types of test structures are formed during semiconductor processing. One type of test structure comprises features that are aligned with one another and that are formed from different layers. Other types of test structures comprise features formed from respective layers that are not aligned with other test structure features. The different types of test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent layers are patterned. The different types of test structures can provide insight into performance characteristics of different types of devices as the semiconductor process proceeds.

Abstract: A magnetic memory device including a Magnetic Tunnel Junction (MTJ) device comprises a substrate and Front End of Line (FEOL) circuitry. A Via level (VA) InterLayer Dielectric (ILD) layer, a bottom conductor layer, and an MTJ device formed over the top surface of the VA ILD layer are formed over a portion of the substrate. An alignment region including alignment marks extends through the bottom conductor layer and extends down into the device below the top surface of the VA ILD layers is juxtaposed with the MJT device.

Abstract: An electronic device is formed by epitaxially growing a Si substrate on a Si layer of an SOI substrate in which the Si layer is deposited on a front surface of a substrate with an insulating layer interposed therebetween; forming an element on a front-surface side of the Si substrate; and forming a back-surface element aligned with respect to the element, on a back-surface side of the Si substrate after the substrate is etched. A mark is formed by etching and removing the Si layer and the insulating layer in a predetermined position of the SOI substrate. The element is formed using a concave part as a reference position. The concave part appears on the front surface of the Si substrate epitaxially grown on the mark. The back-surface element is formed using the mark as a reference position. The mark appears after the substrate is etched.

Abstract: An alignment mark mask element protects an underlying alignment mark during subsequent processing of a fabrication substrate. The alignment mark mask element is formed concurrent with formation of a photomask from a dual-tone photoresist that exhibits a pattern reversal upon exposure to an energy level. A portion of the dual-tone photoresist above the alignment mark is exposed to an energy sufficient to reverse a positive tone resist to a negative tone, which remains above the alignment mark after developing. The remainder of the dual-tone photoresist is exposed through a reticle at a lesser energy level and patterned to define aperture locations of a photomask for formation of semiconductor device features. In addition, a photomask for use on a fabrication substrate and an intermediate semiconductor device are disclosed. Methods of forming a photomask and an intermediate semiconductor device structure are also disclosed.

Abstract: Provided are an alignment key, a method for fabricating the alignment key, and a method for fabricating a thin film transistor substrate using the alignment key. The method for fabricating the alignment key includes forming a first metal layer on a base substrate, forming a first alignment key and a first mark portion of a second alignment key by selectively patterning the first metal layer, forming a dielectric on the first metal layer, forming a second metal layer on the dielectric, and forming a second mark portion of the second alignment key on the dielectric by selectively patterning the second metal layer.

Abstract: Large-area ICs (e.g., silicon wafer-based solar cells) are produced by positioning a mask between an extrusion head and the IC wafer during extrusion of a dopant bearing material or metal gridline material. The mask includes first and second peripheral portions that are positioned over corresponding peripheral areas of the wafer, and a central opening that exposes a central active area of the wafer. The extrusion head is then moved relative to the wafer, and the extrusion material is continuously extruded through outlet orifices of the extrusion head to form elongated extruded structures on the active area of the wafer. The mask prevents deposition of the extrusion material along the peripheral edges of the wafer, and facilitates the formation of unbroken extrusion structures. The mask may be provided with a non-rectangular opening to facilitate the formation of non-rectangular (e.g., circular) two-dimensional extrusion patterns.

Abstract: A substrate for fixing an integrated circuit (IC) element comprises: a substrate for fixing an integrated circuit element includes: a plurality of metal posts that are aligned in a longitudinal direction and a lateral direction in plan view, each of the plurality of metal posts having a first surface and a second surface facing an opposite direction to the first surface, the plurality of metal posts being configured identically; and a joining section that joins each of the plurality of metal posts together at a portion of each of the plurality of metal posts between the first surface and the second surface.

Abstract: A method for fabricating the semiconductor device comprises providing a semiconductor substrate having a device region and a testkey region. A first trench is formed in the device region and a second trench is formed in the testkey region. A conductive layer with a first etching selectivity is formed in the first and second trenches. A first implantation process is performed in a first direction to form a first doped region with a first impurity and an undoped region in the conductive layer simultaneously and respectively in the device region and in the testkey region. A second implantation process is performed in the second trench to form a second doped region with a second impurity in the conductive layer, wherein the conductive layer in the second trench has a second etching selectivity higher than the first etching selectivity.

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a semiconductor layer of polysilicon on an insulating substrate; forming a gate insulating layer on the semiconductor layer; forming a gate electrode on the gate insulating layer; forming a source region and a drain region by doping conductive impurities in the semiconductor layer; forming an interlayer insulating layer covering the gate electrode; forming a source electrode and a drain electrode respectively connected to the source and the drain regions; forming a passivation layer covering the source and the drain electrodes; forming a pixel electrode connected to the drain electrode; and forming a first alignment key when forming one selected from the semiconductor layer, the gate electrode, the source and the drain electrodes, and the pixel electrode, wherein one selected from the semiconductor layer, the gate electrode, the source and the drain electrodes, and the pixel electrode is at least formed by photol

Abstract: An alignment mark formed by using a first mask used in forming a same memory cell pattern on a substrate and formed together with the memory cell pattern includes: a first pattern for position detection used for alignment in forming a first wiring pattern; and a first irregular reflection prevention mark that suppresses, when a position detection signal is irradiated as alignment in forming a second wiring pattern further on an upper layer side than the first wiring pattern, irregular reflection of a position detection signal from a second pattern for position detection formed further in a lower layer than the first pattern for position detection.

Abstract: A semiconductor device manufacturing method includes: forming a via pattern in an insulating film by use of an alignment mark of a lower wiring line; forming, by use of an alignment mark of the via pattern, an upper wiring groove pattern in an upper insulating film in which the via pattern is embedded; and repeating etching in a self-aligning manner to form a via and a wiring groove in an insulating film previously stacked under the insulating film in which the via pattern has been formed.

Abstract: A method is disclosed for producing an integrated circuit arrangement with an auxiliary indentation, particularly with aligning marks, and an integrated circuit arrangement. The invention also relates to a method for producing aligning marks. During the method, a planarization is carried out before material is removed from an auxiliary indentation.

Abstract: A semiconductor device manufacturing method includes: forming an element-isolating insulating film in an element-forming region, and an underlying insulating film in a peripheral region; forming a gate material film; etching the gate material film to form a gate pattern and removing the gate material film on the underlying insulating film to form an alignment mark-forming region; forming an interlayer insulating film; etching the interlayer insulating film to form a contact hole, and a mark hole in the alignment mark-forming region; forming a first conductive film so as to fill the contact hole but not to fill the mark hole; removing the first conductive film outside the contact hole and the mark hole; forming a second conductive film so as not to fill the mark hole; and performing lithographic alignment by taking advantage of a level difference created by a recess left inside the mark hole.

Abstract: An object of the present inventions is to overcome a problem that the presence of a metal film, which is opaque to a visible light, between a lower layer alignment mark and a photoresist prevents the detection of the lower layer alignment mark, to make the pattern formation difficult. In the present inventions, an insulating film is placed beneath the alignment mark in structure; an alignment mark consisting of said multi-layered film comprising an alignment mark layer and the insulating film, which constitutes a stepped part with an increased difference in level, is first formed, inside a mark hole, in a manner of self-alignment; and then the metal film which is the very cause of the above problem is formed thereon. Since the metal film itself has a stepped shape corresponding to the alignment mark, alignment can be made with great accuracy.

Abstract: A method and apparatus for correcting overlay errors in a lithography system. During lithographic exposure, features being exposed on the wafer need to overlay existing features on the wafer. Overlay is a critical performance parameter of lithography tools. The wafer is locally heated during exposure. Thermal expansion causes stress between the wafer and the wafer table, which will cause the wafer to slip if it exceeds the local frictional force. To increase the amount of expansion allowed before slipping occurs, the wafer chuck is uniformly expanded after the wafer has been loaded. This creates an initial stress between the wafer and the wafer table. As the wafer expands due to heating during exposure, the expansion first acts to relieve the initial stress before causing an opposite stress from thermal expansion. The wafer may be also be heated prior to attachment to the wafer chuck, creating the initial stress as the wafer cools.