Having Air-gap Dielectric (e.g., Groove, Etc.) Patents (Class 438/421)
  • Patent number: 6479366
    Abstract: A semiconductor device is fabricated first by thermocompression-bonding a silicon oxide film onto a plurality of conductive films under vacuum using a film having the silicon oxide film formed thereon and then by separating the base film from the silicon oxide film. During the separation, the base film, being composed of a fluorine-containing resin, has smaller surface energy than a silicon oxide film and thus is easy to separate, leaving the silicon oxide film on the conductive films. As a result, the silicon oxide film is adhered on the conductive films so as to cover the conductive films, and an air gap is hence provided between the conductive films. Thus, a highly reliable semiconductor device capable of high-speed-operation is provided by controlling parasitic capacitances between interconnections arranged accurately and adequately adjacent to each other so that recent needs for further miniaturization and higher integration of semiconductor elements can be met.
    Type: Grant
    Filed: February 20, 2001
    Date of Patent: November 12, 2002
    Assignee: Nippon Steel Corporation
    Inventor: Yasushi Miyamoto
  • Patent number: 6479378
    Abstract: An integrated circuit having at least one electrical interconnect for connecting at least two components and a process for forming the same are disclosed.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: November 12, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Philip J. Ireland
  • Patent number: 6472257
    Abstract: The integrated inductor comprises a coil of metal which is formed in the second metal level. The coil is supported by a bracket extending above spaced from a semiconductor material body by an air gap obtained by removing a sacrificial region formed in the first metal level. The bracket is carried by the semiconductor material body through support regions which are arranged peripherally on the bracket and are separated from one another by through apertures which are connected to the air gap. A thick oxide region extends above the semiconductor material body, below the air gap, to reduce the capacitive coupling between the inductor and the semiconductor material body. The inductor thus has a high quality factor, and is produced by a process compatible with present microelectronics processes.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: October 29, 2002
    Assignee: STMicroelectronics S.r.l.
    Inventors: Paolo Ferrari, Armando Manfredi, Benedetto Vigna
  • Patent number: 6472285
    Abstract: The present invention provides a high-Q inductance device and a method for fabricating the same. The inductance device is formed on a semiconductor substrate and includes at least one spiral conducting line and a passivation layer formed above the spiral conducting line, the passivation layer including a spiral air gap formed within the space around the spiral conducting line. By means of the at least one spiral conducting line, the resistance of the inductance device can be decreased. Moreover, the parasitic capacitance can be decreased by means of the air gap with a low dielectric constant. Therefore, the Q value of the inductance device of the present invention can be effectively increased.
    Type: Grant
    Filed: April 30, 1999
    Date of Patent: October 29, 2002
    Assignee: Winbond Electronics Corporation
    Inventor: Ping Liou
  • Patent number: 6468877
    Abstract: A method of fabricating an air-gap spacer of a semiconductor device, comprising the following steps. A semiconductor substrate having at least a pair of STIs defining an active region is provided. A gate electrode is formed on the substrate within the active region. The gate electrode having an underlying gate dielectric layer. A liner oxide layer is formed over the structure, covering the sidewalls of the gate dielectric layer, the gate electrode, and over the top surface of the gate electrode. A liner nitride layer is formed over the liner oxide layer. A thick oxide layer is formed over the structure. The thick oxide, liner nitride, and liner oxide layers are planarized level with the top surface of the gate electrode, and exposing the liner oxide layer at either side of the gate electrode.
    Type: Grant
    Filed: July 19, 2001
    Date of Patent: October 22, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan, Elgin Quek, Ravi Sundaresan, Yang Pan, James Yong Meng Lee, Ying Keung Leung
  • Patent number: 6451669
    Abstract: One embodiment of the invention is directed to a method of forming a metallization level of an integrated circuit including the steps of forming metal areas of a metallization level laterally separated by a first insulating layer, removing the first insulating layer, non-conformally depositing a second insulating layer so that gaps can form between neighboring metal areas, or to obtain a porous layer. The removal of the first insulating layer is performed through a mask, to leave in place guard areas of the first insulating layer around the portions of the metal areas intended for being contacted by a via crossing the second insulating layer.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: September 17, 2002
    Assignee: STMicroelectronics S.A.
    Inventors: Joaquim Torres, Philippe Gayet, Michel Haond
  • Patent number: 6452267
    Abstract: An integrated circuit device includes electrical conductors providing electrical communication between a substrate and a silicon chip. The silicon chip has first electronics and second electronics. The second electronics are for operating at higher frequencies than the first electronics. A first portion of electrical conductors are in communication with the first electronics and a second portion of electrical conductors are in communication with the second electronics. A first medium is positioned adjacent to the first portion of electrical conductors and a second medium is positioned adjacent to the second portion of electrical conductors. The second medium is different from the solid first medium.
    Type: Grant
    Filed: April 4, 2000
    Date of Patent: September 17, 2002
    Assignee: Applied Micro Circuits Corporation
    Inventors: Timothy L. LeClair, Mary Jo Nettles
  • Patent number: 6426267
    Abstract: The present invention provides a method for fabricating a high-Q inductance device. First, a first dielectric layer is formed on a semiconductor substrate. A spiral conducting line is formed above the first dielectric layer. Then, a passivation layer is formed above the spiral conducting line and the first dielectric layer, such that a spiral air gap is formed in the passivation layer within the space around the spiral conducting line. Finally, the inductance device is immersed in an acid solution so as to increase the size of the spiral air gap. When an additional dielectric layer and spiral conducting line are formed between the first dielectric layer and the passivation layer, the air gap can be formed not only in the passivation layer, but also in the additional dielectric layer. Therefore, the inductance device of the present invention can have a plurality of air gaps that are formed in the passivation layer or formed in both of the passivation layer and the dielectric layers.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: July 30, 2002
    Assignee: Winbond Electronics Corp.
    Inventor: Ping Liou
  • Publication number: 20020090794
    Abstract: An air gap semiconductor structure and corresponding method of manufacture. The method includes forming a sacrificial polymer film over a substrate having metal lines thereon. A portion of the sacrificial polymer film is subsequently removed to form first spacers. A micro-porous structure layer is formed over the substrate and the metal lines and between the first spacers. A portion of the micro-porous structure layer is removed to form second spacers. The first spacers are removed by thermal dissociation to form air gaps. A dielectric layer is formed over the substrate and the metal lines and between the second spacers.
    Type: Application
    Filed: March 18, 2002
    Publication date: July 11, 2002
    Inventors: Ting-Chang Chang, Yi-Shien Mor, Po-Tsun Liu
  • Patent number: 6413827
    Abstract: Techniques of shallow trench isolation and devices produced therefrom are provided. The techniques of shallow trench isolation utilize foamed polymers, cured aerogels or air gaps as the insulation medium. Such techniques facilitate lower dielectric constants than the standard silicon dioxide due to the cells of gaseous components inherent in foamed polymers, cured aerogels or air gaps. Lower dielectric constants reduce capacitive coupling concerns and thus permit higher device density in an integrated circuit device.
    Type: Grant
    Filed: February 14, 2000
    Date of Patent: July 2, 2002
    Inventor: Paul A. Farrar
  • Patent number: 6406975
    Abstract: A method of manufacturing a shallow trench isolation (STI) with an air gap that is formed by decomposing an organic filler material through a cap layer. A pad layer and a barrier layer are formed over the substrate. The pad layer and the barrier layer are patterned to form a trench opening. We form a trench in substrate by etching through the trench opening. A first liner layer is formed on the sidewalls of the trench. A second liner layer over the barrier layer and the first liner layer. A filler material is formed on the second liner layer to fill the trench. In an important step, a cap layer is deposited over the filler material and the second liner layer. The filler material is subjected to a plasma and heated to vaporize the filler material so that the filler material diffuses through the cap layer to form a gap. An insulating layer is deposited over the cap layer. The insulating layer is planarized. The barrier layer is removed.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: June 18, 2002
    Assignee: Chartered Semiconductor Manufacturing Inc.
    Inventors: Victor Seng Keong Lim, Young-Way Teh, Ting-Cheong Ang, Alex See, Yong Kong Siew
  • Patent number: 6406992
    Abstract: A fabrication of a damascene structure is described. A substrate having a first conductive layer formed thereon is provided. A silicon nitride type of first dielectric layer is formed on the substrate, followed by patterning the first dielectric layer to form a trench like structure. A silicon oxide type of second dielectric layer is then formed on the first dielectric layer and in the trench like structure and an air-gap is concurrently formed in the second dielectric layer that is in the trench like structure. Thereafter, the second dielectric layer is planarized until a surface of the first dielectric layer is exposed. The first dielectric layer is then removed to form a trench, followed by filling the trench with a second conductive layer.
    Type: Grant
    Filed: May 29, 2001
    Date of Patent: June 18, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Akira Mao, Min-Hung Wang
  • Patent number: 6403430
    Abstract: A semiconductor structure includes a first substrate portion having a surface and a first active region disposed in the first substrate portion. An insulator region is disposed on the first substrate portion outside of the first active region and extends out from the surface. A second substrate portion is disposed on the insulator region, and a second active region is disposed in the second substrate portion. Thus, by disposing a portion of the substrate on the isolation region, the usable substrate area is dramatically increased.
    Type: Grant
    Filed: July 10, 2000
    Date of Patent: June 11, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Darwin A. Clampitt
  • Patent number: 6376286
    Abstract: A silicon on insulator (SOI) field effect transistor (FET) structure is formed on a conventional bulk silicon wafer. The structure includes an electrical coupling between the channel region of the FET with the bulk silicon substrate to eliminate the floating body effect caused by charge accumulation in the channel regions due to historical operation of the FET. The method of forming the structure includes isolating the FET active region from other structures in the silicon substrate by forming an insulating trench about the perimeter of the FET and forming an undercut beneath the active region to reduce or eliminate junction capacitance between the source and drain regions and the silicon substrate.
    Type: Grant
    Filed: October 20, 1999
    Date of Patent: April 23, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Dong-Hyuk Ju
  • Patent number: 6376330
    Abstract: A dielectric material is provided having air gaps purposely formed within the dielectric. The dielectric is deposited, and air gaps formed, between respective interconnect lines. The geometries between interconnect lines is purposely controlled to achieve a large aspect ratio necessary to produce air gaps during CVD of the dielectric. Air gaps exist between interconnects to reduce the line-to-line capacitance, and thereby reduce the propagation delay associated with closely spaced interconnects.
    Type: Grant
    Filed: June 5, 1996
    Date of Patent: April 23, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: H. Jim Fulford, Jr., Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, Mark W. Michael, William S. Brennan
  • Patent number: 6369430
    Abstract: Insulating layers between transistors that are very close together may have voids. When contacts are formed in these areas between these close transistors, the contact hole is formed at the void location. These voids may extend between the contact locations that are close together so that the deposition of the conductive material into these contact holes may extend sufficiently into the void to short two such contacts. This is prevented by placing a liner in the contact hole, which constricts the void size in the contact hole, prior to depositing the conductive material. This restricts ingress of conductive material into the void. This prevents the void from being an unwanted conduction path between two contacts that are in close proximity. The bottoms of the contact holes are etched to remove the liner prior to depositing the conductive material.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: April 9, 2002
    Assignee: Motorola, Inc.
    Inventors: Olubunmi O. Adetutu, Yeong-Jyh T. Lii, Paul A. Grudowski
  • Patent number: 6368939
    Abstract: A semiconductor device has an air-gap/multi-level interconnection structure. The interconnects are insulated from one another by an air gap in the same layer, and by an interlevel dielectric film between layers and from a semiconductor substrate. A high-speed semiconductor device is obtained due to a lower parasitic capacitance.
    Type: Grant
    Filed: March 22, 2000
    Date of Patent: April 9, 2002
    Assignee: NEC Corporation
    Inventor: Makoto Sasaki
  • Patent number: 6365918
    Abstract: The present invention relates to a method and device for interconnecting radio frequency power SiC field effect transistors. To improve the parasitic source inductance advantage is taken of the small size of the transistors, wherein the bonding pads are placed on both sides of the die in such a way that most of the source bonding wires (6) go perpendicularly to the gate and drain bonding wires (7, 8). Multiple bonding wires can be connected to the source bonding pads, reducing the source inductance. An additional advantage comes from such arrangement by reducing the mutual inductance between source/gate and between source/drain due to the orthogonal wire placement.
    Type: Grant
    Filed: October 12, 1999
    Date of Patent: April 2, 2002
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Andrej Litwin, Ted Johansson
  • Patent number: 6365489
    Abstract: An integrated circuit having at least one electrical interconnect for connecting at least two components and a process for forming the same are disclosed. The integrated circuit comprises: a substrate, a plurality of adjacent conductive strips, a layer of dielectric material, and a conductive material. The has a surface and the plurality of adjacent conductive strips is disposed on the substrate surface with each adjacent conductive strip having a length. The layer of dielectric material is deposited over the substrate surface and over and around the plurality of adjacent conductive strips to form at least two opposing, contoured, merging dielectric surfaces, each of which overhangs the substrate surface located between at least two of the plurality of adjacent conductive strips. The at least two opposing, contoured, merging dielectric surfaces define at least one elongated passageway which has at least one opening and is substantially encased therein and which extends along the length.
    Type: Grant
    Filed: June 15, 1999
    Date of Patent: April 2, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Philip J. Ireland
  • Patent number: 6362072
    Abstract: A process for forming, on a semiconductor substrate, an isolation structure between two zones of an integrated circuit wherein active regions of electronic components integrated thereto have already been defined, comprises the steps of: defining an isolation region on a layer of silicon oxide overlying a silicon layer; selectively etching the silicon to provide the isolation region; growing thermal oxide over the interior surfaces of the isolation structure; depositing dielectric conformingly; and oxidizing the deposited dielectric.
    Type: Grant
    Filed: October 26, 1999
    Date of Patent: March 26, 2002
    Assignee: STMicroelectronics S.r.l.
    Inventor: Raffaele Zambrano
  • Patent number: 6362073
    Abstract: Disclosed is a method for forming a semiconductor device; and, more particularly, to a method for forming a semiconductor device with low parasite capacitance by using an air gap and a self-aligned contact plug formed by a selective epitaxial growing method. A method for forming a semiconductor according to the present invention comprises the steps of: forming word lines over a semiconductor substrate, wherein a plurality of contact areas are formed between the word lines; forming epitaxial layers for contact plugs on the contact areas, thereby forming a resulting structure; forming air gaps on non-contact areas on which the epitaxial layers is not formed, by depositing an interlayer insulation layer on the resulting structure; and patterning the interlayer insulation layer so as to expose the epitaxial layers. Accordingly, the present invention using the air gap as a gap filling materials reduces the parasite capacitance loaded on a bit line and omits an additional gap filling process.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: March 26, 2002
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Jin-Woong Kim
  • Patent number: 6355535
    Abstract: The structure of a high-Q inductor applied in a monolithic circuit according to the invention comprises a plurality of spiral metal lines and a plurality of dielectric layers, each dielectric layer formed between two adjacent spiral metal lines. Furthermore, via plugs are formed in each dielectric layer to electrically connect two adjacent spiral metal lines. A spiral air trench is formed along the spacing of the spiral metal lines in the dielectric layers. Therefore, the 3D-structure of the inductor of the invention can greatly reduce the series resistance thereof without widening the spiral metal lines. In addition, the spiral air trench, filled with air which has a lower dielectric constant, can efficiently reduce the parasitic capacitance between the spacing of the spiral metal lines. As a result, the inductor of the invention has a higher quality factor at a proper RF operating frequency region.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: March 12, 2002
    Assignee: Winbond Electronics Corp.
    Inventor: Ping Liou
  • Publication number: 20020025653
    Abstract: A semiconductor device has an air-gap/multi-level interconnection structure. The interconnects are insulated from one another by an air gap in the same layer, and by an interlevel dielectric film between layers and from a semiconductor substrate. A high-speed semiconductor device is obtained due to a lower parasitic capacitance.
    Type: Application
    Filed: March 22, 2000
    Publication date: February 28, 2002
    Inventor: Makoto Sasaki
  • Patent number: 6342427
    Abstract: A method for forming a micro cavity is disclosed. In the method for forming the cavity, a first layer is formed on a silicon layer and a trench is formed in the silicon layer by selectively etching the silicon layer. A second and a third layers are formed on the trench and on the silicon layer. Etching holes are formed through the third layer by partially etching the third layer. A cavity is formed between the silicon layer and the third layer after the second layer is removed through the etching holes. Therefore, the cavity having a large size can be easily formed and sealed in the silicon layer by utilizing the volume expansion of the silicon or the poly silicon layer. Also, a vacuum micro cavity can be formed according as a low vacuum CVD oxide layer or a nitride layer formed on the etching holes which are partially opened after the thermal oxidation process by controlling the size of the etching holes concerning the other portion of the poly silicon layer.
    Type: Grant
    Filed: December 29, 1999
    Date of Patent: January 29, 2002
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Chang Auck Choi, Chi Hoon Jun, Won Ick Jang, Yun Tae Kim
  • Patent number: 6342430
    Abstract: An isolation process which enhances the performance of silicon micromechanical devices incorporates dielectric isolation segments within the silicon microstructure, which is otherwise composed of an interconnected grid of cantilevered beams. A metal layer on top of the beams provides interconnects and also allows contact to the silicon beams, electrically activating the device for motion or transduction. Multiple conduction paths are incorporated through a metal patterning step prior to structure definition. The invention improves manufacturability of previous processes by performing all lithographic patterning steps on flat topographies, and removing complicated metal sputtering steps required of most high aspect ratio processes. With little modification, the invention can be implemented with in grated circuit fabrication sequences for fully integrated devices.
    Type: Grant
    Filed: April 13, 2000
    Date of Patent: January 29, 2002
    Assignees: Kionix, Inc., Cornell Research Foundation
    Inventors: Scott G. Adams, Kevin A. Shaw, Russell Y. Webb, Bryan W. Reed, Noel C. MacDonald, Timothy J. Davis
  • Publication number: 20020005557
    Abstract: The present invention is intended to realize low current consumption and to prevent malfunction in a semiconductor integrated circuit constituted by a mixture of an element having a low threshold voltage and an element having a high threshold voltage in a power-down mode.
    Type: Application
    Filed: February 8, 2001
    Publication date: January 17, 2002
    Inventor: Hidetaka Kodama
  • Publication number: 20020001973
    Abstract: A process for treating a silica film on a substrate, which includes reacting a suitable silica film with an effective amount of a surface modification agent, wherein the silica film is present on a substrate. The reaction is conducted under suitable conditions and for a period of time sufficient for the surface modification agent to form a hydrophobic coating on the film. The surface modification agent includes at least one type of oligomer or polymer reactive with silanols on the silica film. Dielectric films and integrated circuits including such films are also disclosed.
    Type: Application
    Filed: April 24, 2001
    Publication date: January 3, 2002
    Inventors: Hui-Jung Wu, James S. Drage
  • Patent number: 6329279
    Abstract: An outer air spacer structure, applicable to multilevel interconnects technologies, and the method of making the same are disclosed. The outer air spacer is adjacent to a metal line to provide a lower dielectric constant in a metal interconnect structure. The outer air spacer is formed by initially forming a first spacer adjacent to the metal line, followed by forming a second spacer on the first spacer. The first spacer is then removed to form an air gap between the second spacer and the metal line. The air gap is closed to form the outer air spacer by partially sealing the air gap with a portion of passivation layer that is deposited subsequently.
    Type: Grant
    Filed: March 24, 2000
    Date of Patent: December 11, 2001
    Assignee: United Microelectronics Corp.
    Inventor: Robin Lee
  • Patent number: 6326229
    Abstract: To manufacture integrated semiconductor devices comprising chemoresistive gas microsensors, a semiconductor material body is first formed, on the semiconductor material body are successively formed, reciprocally superimposed, a sacrificial region of metallic material, formed at the same time and on the same level as metallic connection regions for the sensor, a heater element, electrically and physically separated from the sacrificial region and a gas sensitive element, electrically and physically separated from the heater element; openings are formed laterally with respect to the heater element and to the gas sensitive element, which extend as far as the sacrificial region and through which the sacrificial region is removed at the end of the manufacturing process.
    Type: Grant
    Filed: September 24, 1999
    Date of Patent: December 4, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Ubaldo Mastromatteo, Benedetto Vigna
  • Patent number: 6316347
    Abstract: An air gap semiconductor structure and corresponding method of manufacture. The method includes providing a substrate having metallic lines thereon. A high molecular weight sacrificial film is formed over the substrate. A portion of the high molecular weight sacrificial layer is removed to form spacers. A dielectric layer is formed over the substrate, the top surface of the metallic lines and the spacers. Finally, a thermal dissociation operation is conducted to remove the spacers, thereby forming an air pocket on each sidewall of the metallic lines.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: November 13, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Ting-Chang Chang, Yi-Shien Mor, Po-Tsun Liu
  • Patent number: 6313046
    Abstract: The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components.
    Type: Grant
    Filed: July 14, 1998
    Date of Patent: November 6, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Werner Juengling, Kirk D. Prall, Ravi Iyer, Gurtej S. Sandhu, Guy Blalock
  • Patent number: 6313006
    Abstract: A method of field implantation. Using a photo-resist layer as a mask, a substrate is implanted with ions to forming a selectively distributed ion field.
    Type: Grant
    Filed: March 26, 1998
    Date of Patent: November 6, 2001
    Assignee: United Microelectronics, Corp.
    Inventors: C. C. Hsue, Sun-Chieh Chien
  • Patent number: 6309946
    Abstract: A void is defined between adjacent wiring lines to minimize RC coupling. The void has a low dielectric value approaching 1.0. For one approach, hollow silicon define the void. The spheres are fabricated to a known inner diameter, wall thickness and outer diameter. The spheres are ridgid enough to withstand the mechanical processes occurring during semiconductor fabrication. The spheres withstand elevated temperature up to a prescribed temperature range. At or above a desired temperature, the sphere walls disintegrate leaving the void in place. For an alternative approach, adjacent wiring lines are “T-topped” (i.e., viewed cross-sectionally). Dielectric fill deposited in the spacing between lines. As the dielectric material accumulates on the line and substrate walls, the T-tops grow toward each other. Eventually, the T-tops meet sealing off and internal void.
    Type: Grant
    Filed: December 8, 1998
    Date of Patent: October 30, 2001
    Assignee: Micron Technology, Inc.
    Inventor: John H. Givens
  • Publication number: 20010034109
    Abstract: A method of increasing trench density for semiconductor devices such as, for example, trench MOSFETs. Trenches are formed in a substrate with mesas interposed between the trenches. The initial width of the mesas are made less than target width so that a reduction in trench pitch can be realized. After a silicon layer is grown inside the trenches, the width of the mesas is increased to a final width that is two times the thickness of the silicon layer. The thickness of the silicon layer is precalculated so that it is of sufficient thickness to ensure compliance with the target mesa width.
    Type: Application
    Filed: May 1, 2001
    Publication date: October 25, 2001
    Inventors: Gordon K. Madson, Joelle Sharp
  • Patent number: 6306753
    Abstract: Wires are provided on an insulating layer, reaching the source region and drain region of a MOS transistor. Each wire is composed of a conductor and a barrier layer covering the surfaces of the conductor. An insulating layer is mounted on the wires, an insulating layer on the insulating layer, and an insulating layer on the insulating layer. Cavities are provided among the wires. The cavities are filled with air or a mixture gas of oxygen and carbon dioxide. Wires are provided on the insulating layer. Cavities are provided among the wires. These cavities are filled with air or a mixture gas of oxygen and carbon dioxide.
    Type: Grant
    Filed: March 14, 2000
    Date of Patent: October 23, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Minakshisundaran Balasubramanian Anand, Hideki Shibata, Masaki Yamada
  • Patent number: 6306754
    Abstract: A method for creating metal layers in a microelectronic device where air is the primary dielectric separating adjacent metal features within a layer. A temporary structural solid, such as a photoresist, is deposited on a substrate with exposed metal features. The photoresist is etched back to expose at least the top surfaces of the metal features. A porous dielectric is then deposited on the substrate and cured to stabilize the structure. The substrate is then treated with a supercritical fluid, such as supercritical CO2, to extract the photoresist through the pores of the porous dielectric layer.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: October 23, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Vishnu K. Agarwal
  • Patent number: 6303464
    Abstract: A reduced capacitance interconnect system. A first metal layer is formed to a predetermined level above a first dielectric layer which is formed on a semiconductor substrate. The first metal layer level forms multiple interconnect lines wherein each interconnect line is separated from each adjacent interconnect line by a trench including a trench having a highest aspect ratio. A second dielectric layer is formed on the first metal layer and in the trenches between the interconnect lines such that an enclosed void having a void tip substantially level with the top of the metal layer is formed in at least each trench having an aspect ratio above a predetermined minimum aspect ratio, wherein the enclosed void in the trench having the highest aspect ratio has a void volume which is at least 15% of the volume of the trench.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: October 16, 2001
    Assignee: Intel Corporation
    Inventors: Eng T. Gaw, Quat T. Vu, David B. Fraser, Chien Chiang, Ian A. Young, Thomas N. D. Marieb
  • Patent number: 6297145
    Abstract: A method of manufacturing a semiconductor device having a wiring layer with an air bridge construction includes the steps of forming a lower layer metal interconnect, depositing an interlayer insulation film, depositing a first and a second insulation film, patterning the second insulation film and of etching the first insulation film and the interlayer insulation film using the second insulation film as a mask so as to form a post opening part and a via hole to connect an upper layer metal interconnect with the lower layer metal interconnect, depositing a third insulation film over the entire surface, etching back so as to leave the third insulation film in a side wall of the post opening part and fill the via hole with the third insulation film, depositing a fourth insulation film over the entire surface of the structure, then removing the fourth insulation film until the via hole is exposed, and then removing the third insulation film inside the via hole, filling the via hole with a metal, and then flatten
    Type: Grant
    Filed: May 13, 1999
    Date of Patent: October 2, 2001
    Assignee: NEC Corporation
    Inventor: Shinya Ito
  • Patent number: 6297125
    Abstract: Air-bridges are formed at controlled lateral separations using the extremely high HF etch rate of a gap-fill spin-on-glass such as uncured hydrogen silsequioxane (HSQ) in combination with other dielectrics having a much slower etch rate in HF. The advantages of an air-bridge system with controlled lateral separations include providing an interconnect isolation dielectric which meets all requirements for sub-0.5 micron technologies and providing a device with reduced reliability problems.
    Type: Grant
    Filed: January 19, 1999
    Date of Patent: October 2, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Somnath S. Nag, Amitava Chatterjee, Girish A. Dixit
  • Patent number: 6277728
    Abstract: A multilevel interconnect structure with a low-k dielectric constant is fabricated in an integrated circuit structure by the steps of depositing a layer of photoresist on a substrate assembly, etching the photoresist to form openings, forming a metal layer on the photoresist layer to fill the openings and then removing the photoresist layer by, for example, ashing. The metal layer is supported by the metal which filled the openings formed in the photoresist.
    Type: Grant
    Filed: August 17, 1999
    Date of Patent: August 21, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 6277705
    Abstract: A fabrication method for an air-gap, in which method hard mask is used, is described. A patterned hard mask layer is formed on a semiconductor substrate. Taking advantage of the etching selectivity of the hard mask layer to the dielectric layer, an opening with a high aspect ratio is formed in the dielectric layer. A conductive plug is then formed in the opening, followed by forming a conductive layer on the hard mask layer to cover the conductive plug. The hard mask layer is further removed. A silicon oxide layer with poor step coverage is formed to cover the substrate. Using the space remaining after the removal of the hard mask layer, an air-gap is formed between the conductive layer and the dielectric layer to enhance the insulation effect.
    Type: Grant
    Filed: January 14, 2000
    Date of Patent: August 21, 2001
    Assignee: United Microelectronics Corp.
    Inventor: Robin Lee
  • Patent number: 6268262
    Abstract: Disclosed is a method for making an air bridge in an electronic device. This method uses amorphous silicon carbide to protect electrical conductors in the device during formation of the bridge. The silicon carbide also provides hermetic and physical protection to the device after formation.
    Type: Grant
    Filed: August 11, 1997
    Date of Patent: July 31, 2001
    Assignee: Dow Corning Corporation
    Inventor: Mark Jon Loboda
  • Patent number: 6268261
    Abstract: A process for manufacturing a semiconductor circuit. The process comprises creating a plurality of adjacent conductive lines having a solid fill between the conductive lines; creating one or more layers above the lines and the fill; creating one or more pathways to the fill through the layers; and converting the fill to a gas that escapes through the pathways, leaving an air void between adjacent lines. To protect the lines from oxidation during processing, a related process for encapsulating conductive lines in one or more adhesion-promotion barrier layers may be performed. The encapsulation process may also be practiced in conjunction with other semiconductor manufacturing processes. The processes result in a multi-layer semiconductor circuit comprising conductive lines, wherein the lines have air as a dielectric between them, are encapsulated by an adhesion-promotion barrier layer, or both.
    Type: Grant
    Filed: November 3, 1998
    Date of Patent: July 31, 2001
    Assignee: International Business Machines Corporation
    Inventors: Kevin S. Petrarca, Rebecca D. Mih
  • Patent number: 6268276
    Abstract: A new method of forming air gaps between adjacent conducting lines of a semiconductor circuit by using a “holes everywhere” or a “reverse metal holes” mask that can be used to create holes in a dielectric layer. The dielectric that is being etched has been deposited across conducting lines, the holes that are being formed in this manner are closed by depositing a dielectric across the top of the holes. The holes can be etched across the entire layer of the deposited dielectric or can be etched in between the conducting lines.
    Type: Grant
    Filed: December 21, 1998
    Date of Patent: July 31, 2001
    Assignees: Chartered Semiconductor Manufacturing Ltd., Nanyang Technological University of Singapore
    Inventors: Lap Chan, Kheng Chok Tee, Kok Keng Ong, Chin Hwee Seah
  • Patent number: 6261942
    Abstract: A method for introducing air into the gaps between neighboring conducting structures in a microelectronics fabrication in order to reduce the capacitative coupling between them. A patterned metal layer is deposited on a substrate. The layer is lined with a CVD-oxide. A disposable gap-filling material is deposited over the lined metal layer. A two layer “air-bridge” is formed over the gap-fill by depositing a layer of TiN over a layer of CVD-oxide. This structure is rendered porous by several chemical processes. An oxygen plasma is passed through the porous air-bridge to react with and dissolve the gap-fill beneath it. The reaction products escape through the porous air-bridge resulting in air-filled gaps.
    Type: Grant
    Filed: January 24, 2000
    Date of Patent: July 17, 2001
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Mei Sheng Zhou, Simon Chooi, Xu Yi
  • Publication number: 20010007788
    Abstract: An air gap semiconductor structure and corresponding method of manufacture. The method includes forming a sacrificial polymer film over a substrate having metal lines thereon. A portion of the sacrificial polymer film is subsequently removed to form first spacers. A micro-porous structure layer is formed over the substrate and the metal lines and between the first spacers. A portion of the micro-porous structure layer is removed to form second spacers. The first spacers are removed by thermal dissociation to form air gaps. A dielectric layer is formed over the substrate and the metal lines and between the second spacers.
    Type: Application
    Filed: January 17, 2001
    Publication date: July 12, 2001
    Inventors: Ting-Chang Chang, Yi-Shien Mor, Po-Tsun Liu
  • Patent number: 6258724
    Abstract: A low dielectric constant material and a process for controllably reducing the dielectric constant of a layer of such material is provided and comprises the step of exposing the layer of dielectric material to a concentration of an oxygen plasma at a temperature and a pressure sufficient for the oxygen plasma to etch the layer of dielectric material to form voids in the layer of dielectric material. The process may also include the step of controlling the reduction of the dielectric constant by controlling the size and density of the voids. The size and density of the voids can be controlled by varying the pressure under which the reaction takes place, by varying the temperature at which the reaction takes place, by varying the concentration of the oxygen plasma used in the reaction or by varying a combination of these parameters. The process of the present invention is particularly useful in the fabrication of semiconductor devices.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: July 10, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Sujit Sharan
  • Patent number: 6251798
    Abstract: A method for the formation of an air gap structure for use in inter-metal applications. A metal pattern of metal lines is formed, a layer of Plasma Polymerized Methylsilane (PPMS) resist is deposited on top of this pattern. The surface of the PPMS resist is subjected to selective exposure. The unexposed PPMS is removed after which the process is completed by closing up the openings within the PPMS.
    Type: Grant
    Filed: July 26, 1999
    Date of Patent: June 26, 2001
    Assignees: Chartered Semiconductor Manufacturing Company, National University of Singapore, Nanyang Technological University of Singapore
    Inventors: Choi Pheng Soo, Kheng Chok Tee, Kok Keng Ong, Lap Chan
  • Patent number: 6248622
    Abstract: A fabrication method for an ultra short channel device comprising a self-aligned landing pad is described in which a first opening is formed in the oxide layer to define a gate structure region. A pad oxide layer is then formed in the first opening covering the substrate followed by forming a spacer on the inner sidewall of the first opening. Using the spacer as an etching mask, a portion of the oxide layer is removed to form a second opening exposing the substrate. A gate oxide layer is then deposited in the second opening, followed by forming a first conductive layer to fill the second opening. A third opening is then formed in the oxide layer to expose the substrate and to define the source/drain region. An ion implantation is then conducted in the substrate of the third opening to form a heavily doped region of the source/drain region. Thereafter, a landing pad is formed to fill the third opening and to electrically connect with the source/drain region.
    Type: Grant
    Filed: October 27, 1999
    Date of Patent: June 19, 2001
    Assignee: United Microelectronics Corp.
    Inventor: Robin Lee
  • Patent number: 6245637
    Abstract: STI is sometimes effected by etching back shallow trenches that have been over-filled with oxide in order to make the upper surfaces co-planar with the semiconductor. This results in the formation of a groove at the oxide-semiconductor interface which exposes the source/drain PN junction, making it vulnerable to shorting during subsequent SALICIDE processes. In the present invention, manufacture of the LDD device proceeds in the normal way except that when silicon nitride spacers are grown on the vertical sides of the gate pedestal, the depositing silicon nitride is also allowed to coat the exposed vertical walls of the trenches (i.e. inside the groove). Following standard practice, a layer of pad oxide is interposed between the trench wall and this additional silicon nitride for purposes of stress relief.
    Type: Grant
    Filed: May 10, 1999
    Date of Patent: June 12, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Chao-Chieh Tsai