Abstract: A method of forming metal contacts in a semiconductor device having an active metal contact region and a bit line contact region is provided. In the method, a contact pad is formed in the active metal contact region and the bit line contact region using a conductive plug. An etch stopper is formed on the upper sides of the conductive plug. A portion of a lower interlayer dielectric layer is etched so that the etch stopper protrudes above the lower interlayer dielectric layer. A bit line stack is formed in the bit line contact region. An etch stopper is formed in the active metal contact region. An upper interlayer dielectric layer is etched to expose the surfaces of the etch stopper and bit line capping layer pattern of the bit line stack. The exposed surfaces of the etch stopper and bit line capping layer pattern are etched to form a contact hole which exposes the conductive plug and a bit line conductive layer of the bit line stack. The contact hole is filled with a conductive layer.

Abstract: A semiconductor apparatus is provided which includes a lateral high-voltage semiconductor device which comprises a silicon substrate, a pair of main electrodes formed on the silicon substrate, and a silicon oxide film formed on the silicon substrate, such that at least a part of the silicon oxide film is located between the main electrodes. The semiconductor device further includes a voltage withstanding structure formed on the silicon oxide film, which structure includes a first silicon nitride film having a refractive index of not lower than 2.8, and a second silicon nitride film formed on the first silicon nitride film and having a refractive index of not higher than 2.2.

Abstract: A method for crystallizing an amorphous silicon film which includes the steps of: preparing a substrate having the amorphous silicon film, the amorphous silicon film being formed on an intermediate layer in which an inner space exists; applying an energy to the amorphous silicon film in order to crystallize the amorphous silicon film, wherein the step of preparing the substrate includes the steps of: forming a material layer for forming the space on an insulating substrate, forming the intermediate layer to cover the material layer, forming the amorphous silicon film on the intermediate layer,selectively removing the amorphous silicon film and the intermediate layer to expose a part of the material layer for forming space, and removing the material layer for forming space; or forming a material layer for forming the space on an insulating substrate, forming the intermediate layer to cover the material layer, selectively removing the intermediate layer to expose a part of the material layer, removing the mater

Abstract: A silicon-containing polymer is deposited in a recess on the surface of the substrate. The substrate is then heated to a given temperature. The surface of the substrate, heated to the given temperature and having the silicon-containing polymer deposited thereon, is subjected to gas or vapor activated by a plasma or other electromagnetic radiation which is distinct from a source of heat used to heat the substrate to the given temperature.

Abstract: A pin plate used to print a high density array printing of materials such as biological inks and a method for manufacturing the pin plate are described herein. The pin plate can be manufactured by coating a top surface of a silica wafer with a substantially thick layer of photoresist material. Next, a photolithography process is used to remove selected areas of the photoresist material from the silica wafer. Thereafter, a reactive ion etching process is used to form the pins in the silica wafer by etching away a predetermined amount of the top surface from the silica wafer that is not covered by the photoresist material. Afterwards, the remaining photoresist material is removed from the silica wafer which now resembles the pin plate.

Abstract: A method creates structured cavities with submicrometer dimensions in a cavity layer of a semiconductor device. A processing material that incorporates a swelling agent is deposited on ridges of a working layer that is constructed of ridges and trenches. The processing material expands over the trenches during swelling; and covered cavities thus emerge from the trenches.

Abstract: One aspect of the present invention relates to a method of forming an advanced low k material between metal lines on a semiconductor substrate, involving the steps of providing the semiconductor substrate having a plurality of metal lines thereon; depositing a spin-on material over the semiconductor substrate having the plurality of metal lines thereon; and at least one of heating or etching the semiconductor substrate whereby at least a portion of the spin-on material is removed, thereby forming the advanced low k material comprising at least one air void between the metal lines, the advanced low k material having a dielectric constant of about 2 or less.

Abstract: The invention is directed to a device for regulating the flow of electric current with high dielectric constant gate insulating layer and a source and/or drain forming a Schottky contact or Schottky-like region with a substrate and its fabrication method. In one aspect, the gate insulating layer has a dielectric constant greater than the dielectric constant of silicon. In another aspect, the current regulating device may be a MOSFET device, optionally a planar P-type or N-type MOSFET, having any orientation. In another aspect, the source and/or drain may consist partially or fully of a silicide.

Abstract: A process for producing a semiconductor device module comprises the steps of forming a first substrate having a separation layer having thereon a plurality of independent semiconductor layers and semiconductor devices individually formed on the plurality of semiconductor layers, electrically connecting the semiconductor devices one another on the first substrate, and separating the plurality of semiconductor layers from the first substrate at the separation layer to transfer the semiconductor layers to a second substrate.

Abstract: An air gap semiconductor structure and corresponding method of manufacture. The method includes forming a sacrificial polymer film over a substrate having metal lines thereon. A portion of the sacrificial polymer film is subsequently removed to form first spacers. A micro-porous structure layer is formed over the substrate and the metal lines and between the first spacers. A portion of the micro-porous structure layer is removed to form second spacers. The first spacers are removed by thermal dissociation to form air gaps. A dielectric layer is formed over the substrate and the metal lines and between the second spacers.

Abstract: A process for forming air gap isolation regions between a bit line contact structure and adjacent capacitor structures, to reduce the capacitance of the space between these structures, has been developed. The process features the formation of insulator spacers on the sides of capacitor openings. After formation of capacitor structures, in the capacitor openings, top portions of the insulator spacers are exposed via a first selective etch procedure, allowing a second, selective, isotropic etch procedure to completely remove the insulator spacers creating the air gap isolation regions now located between the capacitor structure and an adjacent insulator layer. Subsequent deposition of an overlying insulator layer, comprised with poor conformality properties, allows coverage of the capacitor structures, however without filling the air gap isolation regions.

Abstract: Structures and methods are disclosed for insulating a polysilicon gate adjacent to an electrically active region with a silicon base layer. A layer of silicon nitride having a thickness in a range from about 100 Å to about 150 Å is conformally deposited over the polysilicon gate. A layer of silicon dioxide is formed over the layer of silicon nitride on the polysilicon gate. The layer of silicon dioxide is subjected to a spacer etch to form spacers upon the layer of silicon nitride and on lateral sidewalls of the polysilicon gate. A portion of the layer of silicon nitride situated between the polysilicon gate and the spacer is removed by an etching process that is selective to silicon dioxide and to polysilicon. The etch forms a recess defined between the polysilicon gate, and each respective spacer. A cover layer is formed to close an opening to the recess so as to enclose a void therein.

Abstract: A TMR element includes: a free layer formed on a lower gap layer; a tunnel barrier layer formed on the free layer; and a pinned layer formed on the tunnel barrier layer. In the step of forming the tunnel barrier layer on the free layer, an Al layer used for making the tunnel barrier layer is formed through sputtering, for example, on the free layer while the substrate is cooled. The Al layer is oxidized to form the tunnel barrier layer.

Abstract: A semiconductor device is fabricated first by thermocompression-bonding a silicon oxide film onto a plurality of conductive films under vacuum using a film having the silicon oxide film formed thereon and then by separating the base film from the silicon oxide film. During the separation, the base film, being composed of a fluorine-containing resin, has smaller surface energy than a silicon oxide film and thus is easy to separate, leaving the silicon oxide film on the conductive films. As a result, the silicon oxide film is adhered on the conductive films so as to cover the conductive films, and an air gap is hence provided between the conductive films. Thus, a highly reliable semiconductor device capable of high-speed-operation is provided by controlling parasitic capacitances between interconnections arranged accurately and adequately adjacent to each other so that recent needs for further miniaturization and higher integration of semiconductor elements can be met.

Abstract: An integrated circuit having at least one electrical interconnect for connecting at least two components and a process for forming the same are disclosed.

Abstract: The integrated inductor comprises a coil of metal which is formed in the second metal level. The coil is supported by a bracket extending above spaced from a semiconductor material body by an air gap obtained by removing a sacrificial region formed in the first metal level. The bracket is carried by the semiconductor material body through support regions which are arranged peripherally on the bracket and are separated from one another by through apertures which are connected to the air gap. A thick oxide region extends above the semiconductor material body, below the air gap, to reduce the capacitive coupling between the inductor and the semiconductor material body. The inductor thus has a high quality factor, and is produced by a process compatible with present microelectronics processes.

Abstract: The present invention provides a high-Q inductance device and a method for fabricating the same. The inductance device is formed on a semiconductor substrate and includes at least one spiral conducting line and a passivation layer formed above the spiral conducting line, the passivation layer including a spiral air gap formed within the space around the spiral conducting line. By means of the at least one spiral conducting line, the resistance of the inductance device can be decreased. Moreover, the parasitic capacitance can be decreased by means of the air gap with a low dielectric constant. Therefore, the Q value of the inductance device of the present invention can be effectively increased.

Abstract: A method of fabricating an air-gap spacer of a semiconductor device, comprising the following steps. A semiconductor substrate having at least a pair of STIs defining an active region is provided. A gate electrode is formed on the substrate within the active region. The gate electrode having an underlying gate dielectric layer. A liner oxide layer is formed over the structure, covering the sidewalls of the gate dielectric layer, the gate electrode, and over the top surface of the gate electrode. A liner nitride layer is formed over the liner oxide layer. A thick oxide layer is formed over the structure. The thick oxide, liner nitride, and liner oxide layers are planarized level with the top surface of the gate electrode, and exposing the liner oxide layer at either side of the gate electrode.

Abstract: An integrated circuit device includes electrical conductors providing electrical communication between a substrate and a silicon chip. The silicon chip has first electronics and second electronics. The second electronics are for operating at higher frequencies than the first electronics. A first portion of electrical conductors are in communication with the first electronics and a second portion of electrical conductors are in communication with the second electronics. A first medium is positioned adjacent to the first portion of electrical conductors and a second medium is positioned adjacent to the second portion of electrical conductors. The second medium is different from the solid first medium.

Abstract: One embodiment of the invention is directed to a method of forming a metallization level of an integrated circuit including the steps of forming metal areas of a metallization level laterally separated by a first insulating layer, removing the first insulating layer, non-conformally depositing a second insulating layer so that gaps can form between neighboring metal areas, or to obtain a porous layer. The removal of the first insulating layer is performed through a mask, to leave in place guard areas of the first insulating layer around the portions of the metal areas intended for being contacted by a via crossing the second insulating layer.

Abstract: The present invention provides a method for fabricating a high-Q inductance device. First, a first dielectric layer is formed on a semiconductor substrate. A spiral conducting line is formed above the first dielectric layer. Then, a passivation layer is formed above the spiral conducting line and the first dielectric layer, such that a spiral air gap is formed in the passivation layer within the space around the spiral conducting line. Finally, the inductance device is immersed in an acid solution so as to increase the size of the spiral air gap. When an additional dielectric layer and spiral conducting line are formed between the first dielectric layer and the passivation layer, the air gap can be formed not only in the passivation layer, but also in the additional dielectric layer. Therefore, the inductance device of the present invention can have a plurality of air gaps that are formed in the passivation layer or formed in both of the passivation layer and the dielectric layers.

Abstract: An air gap semiconductor structure and corresponding method of manufacture. The method includes forming a sacrificial polymer film over a substrate having metal lines thereon. A portion of the sacrificial polymer film is subsequently removed to form first spacers. A micro-porous structure layer is formed over the substrate and the metal lines and between the first spacers. A portion of the micro-porous structure layer is removed to form second spacers. The first spacers are removed by thermal dissociation to form air gaps. A dielectric layer is formed over the substrate and the metal lines and between the second spacers.

Abstract: Techniques of shallow trench isolation and devices produced therefrom are provided. The techniques of shallow trench isolation utilize foamed polymers, cured aerogels or air gaps as the insulation medium. Such techniques facilitate lower dielectric constants than the standard silicon dioxide due to the cells of gaseous components inherent in foamed polymers, cured aerogels or air gaps. Lower dielectric constants reduce capacitive coupling concerns and thus permit higher device density in an integrated circuit device.

Abstract: A method of manufacturing a shallow trench isolation (STI) with an air gap that is formed by decomposing an organic filler material through a cap layer. A pad layer and a barrier layer are formed over the substrate. The pad layer and the barrier layer are patterned to form a trench opening. We form a trench in substrate by etching through the trench opening. A first liner layer is formed on the sidewalls of the trench. A second liner layer over the barrier layer and the first liner layer. A filler material is formed on the second liner layer to fill the trench. In an important step, a cap layer is deposited over the filler material and the second liner layer. The filler material is subjected to a plasma and heated to vaporize the filler material so that the filler material diffuses through the cap layer to form a gap. An insulating layer is deposited over the cap layer. The insulating layer is planarized. The barrier layer is removed.

Abstract: A fabrication of a damascene structure is described. A substrate having a first conductive layer formed thereon is provided. A silicon nitride type of first dielectric layer is formed on the substrate, followed by patterning the first dielectric layer to form a trench like structure. A silicon oxide type of second dielectric layer is then formed on the first dielectric layer and in the trench like structure and an air-gap is concurrently formed in the second dielectric layer that is in the trench like structure. Thereafter, the second dielectric layer is planarized until a surface of the first dielectric layer is exposed. The first dielectric layer is then removed to form a trench, followed by filling the trench with a second conductive layer.

Abstract: A semiconductor structure includes a first substrate portion having a surface and a first active region disposed in the first substrate portion. An insulator region is disposed on the first substrate portion outside of the first active region and extends out from the surface. A second substrate portion is disposed on the insulator region, and a second active region is disposed in the second substrate portion. Thus, by disposing a portion of the substrate on the isolation region, the usable substrate area is dramatically increased.

Abstract: A silicon on insulator (SOI) field effect transistor (FET) structure is formed on a conventional bulk silicon wafer. The structure includes an electrical coupling between the channel region of the FET with the bulk silicon substrate to eliminate the floating body effect caused by charge accumulation in the channel regions due to historical operation of the FET. The method of forming the structure includes isolating the FET active region from other structures in the silicon substrate by forming an insulating trench about the perimeter of the FET and forming an undercut beneath the active region to reduce or eliminate junction capacitance between the source and drain regions and the silicon substrate.

Abstract: A dielectric material is provided having air gaps purposely formed within the dielectric. The dielectric is deposited, and air gaps formed, between respective interconnect lines. The geometries between interconnect lines is purposely controlled to achieve a large aspect ratio necessary to produce air gaps during CVD of the dielectric. Air gaps exist between interconnects to reduce the line-to-line capacitance, and thereby reduce the propagation delay associated with closely spaced interconnects.

Abstract: Insulating layers between transistors that are very close together may have voids. When contacts are formed in these areas between these close transistors, the contact hole is formed at the void location. These voids may extend between the contact locations that are close together so that the deposition of the conductive material into these contact holes may extend sufficiently into the void to short two such contacts. This is prevented by placing a liner in the contact hole, which constricts the void size in the contact hole, prior to depositing the conductive material. This restricts ingress of conductive material into the void. This prevents the void from being an unwanted conduction path between two contacts that are in close proximity. The bottoms of the contact holes are etched to remove the liner prior to depositing the conductive material.

Abstract: A semiconductor device has an air-gap/multi-level interconnection structure. The interconnects are insulated from one another by an air gap in the same layer, and by an interlevel dielectric film between layers and from a semiconductor substrate. A high-speed semiconductor device is obtained due to a lower parasitic capacitance.

Abstract: An integrated circuit having at least one electrical interconnect for connecting at least two components and a process for forming the same are disclosed. The integrated circuit comprises: a substrate, a plurality of adjacent conductive strips, a layer of dielectric material, and a conductive material. The has a surface and the plurality of adjacent conductive strips is disposed on the substrate surface with each adjacent conductive strip having a length. The layer of dielectric material is deposited over the substrate surface and over and around the plurality of adjacent conductive strips to form at least two opposing, contoured, merging dielectric surfaces, each of which overhangs the substrate surface located between at least two of the plurality of adjacent conductive strips. The at least two opposing, contoured, merging dielectric surfaces define at least one elongated passageway which has at least one opening and is substantially encased therein and which extends along the length.

Abstract: The present invention relates to a method and device for interconnecting radio frequency power SiC field effect transistors. To improve the parasitic source inductance advantage is taken of the small size of the transistors, wherein the bonding pads are placed on both sides of the die in such a way that most of the source bonding wires (6) go perpendicularly to the gate and drain bonding wires (7, 8). Multiple bonding wires can be connected to the source bonding pads, reducing the source inductance. An additional advantage comes from such arrangement by reducing the mutual inductance between source/gate and between source/drain due to the orthogonal wire placement.

Abstract: A process for forming, on a semiconductor substrate, an isolation structure between two zones of an integrated circuit wherein active regions of electronic components integrated thereto have already been defined, comprises the steps of: defining an isolation region on a layer of silicon oxide overlying a silicon layer; selectively etching the silicon to provide the isolation region; growing thermal oxide over the interior surfaces of the isolation structure; depositing dielectric conformingly; and oxidizing the deposited dielectric.

Abstract: Disclosed is a method for forming a semiconductor device; and, more particularly, to a method for forming a semiconductor device with low parasite capacitance by using an air gap and a self-aligned contact plug formed by a selective epitaxial growing method. A method for forming a semiconductor according to the present invention comprises the steps of: forming word lines over a semiconductor substrate, wherein a plurality of contact areas are formed between the word lines; forming epitaxial layers for contact plugs on the contact areas, thereby forming a resulting structure; forming air gaps on non-contact areas on which the epitaxial layers is not formed, by depositing an interlayer insulation layer on the resulting structure; and patterning the interlayer insulation layer so as to expose the epitaxial layers. Accordingly, the present invention using the air gap as a gap filling materials reduces the parasite capacitance loaded on a bit line and omits an additional gap filling process.

Abstract: The structure of a high-Q inductor applied in a monolithic circuit according to the invention comprises a plurality of spiral metal lines and a plurality of dielectric layers, each dielectric layer formed between two adjacent spiral metal lines. Furthermore, via plugs are formed in each dielectric layer to electrically connect two adjacent spiral metal lines. A spiral air trench is formed along the spacing of the spiral metal lines in the dielectric layers. Therefore, the 3D-structure of the inductor of the invention can greatly reduce the series resistance thereof without widening the spiral metal lines. In addition, the spiral air trench, filled with air which has a lower dielectric constant, can efficiently reduce the parasitic capacitance between the spacing of the spiral metal lines. As a result, the inductor of the invention has a higher quality factor at a proper RF operating frequency region.

Abstract: A semiconductor device has an air-gap/multi-level interconnection structure. The interconnects are insulated from one another by an air gap in the same layer, and by an interlevel dielectric film between layers and from a semiconductor substrate. A high-speed semiconductor device is obtained due to a lower parasitic capacitance.

Abstract: A method for forming a micro cavity is disclosed. In the method for forming the cavity, a first layer is formed on a silicon layer and a trench is formed in the silicon layer by selectively etching the silicon layer. A second and a third layers are formed on the trench and on the silicon layer. Etching holes are formed through the third layer by partially etching the third layer. A cavity is formed between the silicon layer and the third layer after the second layer is removed through the etching holes. Therefore, the cavity having a large size can be easily formed and sealed in the silicon layer by utilizing the volume expansion of the silicon or the poly silicon layer. Also, a vacuum micro cavity can be formed according as a low vacuum CVD oxide layer or a nitride layer formed on the etching holes which are partially opened after the thermal oxidation process by controlling the size of the etching holes concerning the other portion of the poly silicon layer.

Abstract: An isolation process which enhances the performance of silicon micromechanical devices incorporates dielectric isolation segments within the silicon microstructure, which is otherwise composed of an interconnected grid of cantilevered beams. A metal layer on top of the beams provides interconnects and also allows contact to the silicon beams, electrically activating the device for motion or transduction. Multiple conduction paths are incorporated through a metal patterning step prior to structure definition. The invention improves manufacturability of previous processes by performing all lithographic patterning steps on flat topographies, and removing complicated metal sputtering steps required of most high aspect ratio processes. With little modification, the invention can be implemented with in grated circuit fabrication sequences for fully integrated devices.

Abstract: The present invention is intended to realize low current consumption and to prevent malfunction in a semiconductor integrated circuit constituted by a mixture of an element having a low threshold voltage and an element having a high threshold voltage in a power-down mode.

Abstract: A process for treating a silica film on a substrate, which includes reacting a suitable silica film with an effective amount of a surface modification agent, wherein the silica film is present on a substrate. The reaction is conducted under suitable conditions and for a period of time sufficient for the surface modification agent to form a hydrophobic coating on the film. The surface modification agent includes at least one type of oligomer or polymer reactive with silanols on the silica film. Dielectric films and integrated circuits including such films are also disclosed.

Abstract: An outer air spacer structure, applicable to multilevel interconnects technologies, and the method of making the same are disclosed. The outer air spacer is adjacent to a metal line to provide a lower dielectric constant in a metal interconnect structure. The outer air spacer is formed by initially forming a first spacer adjacent to the metal line, followed by forming a second spacer on the first spacer. The first spacer is then removed to form an air gap between the second spacer and the metal line. The air gap is closed to form the outer air spacer by partially sealing the air gap with a portion of passivation layer that is deposited subsequently.

Abstract: To manufacture integrated semiconductor devices comprising chemoresistive gas microsensors, a semiconductor material body is first formed, on the semiconductor material body are successively formed, reciprocally superimposed, a sacrificial region of metallic material, formed at the same time and on the same level as metallic connection regions for the sensor, a heater element, electrically and physically separated from the sacrificial region and a gas sensitive element, electrically and physically separated from the heater element; openings are formed laterally with respect to the heater element and to the gas sensitive element, which extend as far as the sacrificial region and through which the sacrificial region is removed at the end of the manufacturing process.

Abstract: An air gap semiconductor structure and corresponding method of manufacture. The method includes providing a substrate having metallic lines thereon. A high molecular weight sacrificial film is formed over the substrate. A portion of the high molecular weight sacrificial layer is removed to form spacers. A dielectric layer is formed over the substrate, the top surface of the metallic lines and the spacers. Finally, a thermal dissociation operation is conducted to remove the spacers, thereby forming an air pocket on each sidewall of the metallic lines.

Abstract: The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components.

Abstract: A method of field implantation. Using a photo-resist layer as a mask, a substrate is implanted with ions to forming a selectively distributed ion field.

Abstract: A void is defined between adjacent wiring lines to minimize RC coupling. The void has a low dielectric value approaching 1.0. For one approach, hollow silicon define the void. The spheres are fabricated to a known inner diameter, wall thickness and outer diameter. The spheres are ridgid enough to withstand the mechanical processes occurring during semiconductor fabrication. The spheres withstand elevated temperature up to a prescribed temperature range. At or above a desired temperature, the sphere walls disintegrate leaving the void in place. For an alternative approach, adjacent wiring lines are “T-topped” (i.e., viewed cross-sectionally). Dielectric fill deposited in the spacing between lines. As the dielectric material accumulates on the line and substrate walls, the T-tops grow toward each other. Eventually, the T-tops meet sealing off and internal void.

Abstract: A method of increasing trench density for semiconductor devices such as, for example, trench MOSFETs. Trenches are formed in a substrate with mesas interposed between the trenches. The initial width of the mesas are made less than target width so that a reduction in trench pitch can be realized. After a silicon layer is grown inside the trenches, the width of the mesas is increased to a final width that is two times the thickness of the silicon layer. The thickness of the silicon layer is precalculated so that it is of sufficient thickness to ensure compliance with the target mesa width.

Abstract: A method for creating metal layers in a microelectronic device where air is the primary dielectric separating adjacent metal features within a layer. A temporary structural solid, such as a photoresist, is deposited on a substrate with exposed metal features. The photoresist is etched back to expose at least the top surfaces of the metal features. A porous dielectric is then deposited on the substrate and cured to stabilize the structure. The substrate is then treated with a supercritical fluid, such as supercritical CO2, to extract the photoresist through the pores of the porous dielectric layer.

Abstract: Wires are provided on an insulating layer, reaching the source region and drain region of a MOS transistor. Each wire is composed of a conductor and a barrier layer covering the surfaces of the conductor. An insulating layer is mounted on the wires, an insulating layer on the insulating layer, and an insulating layer on the insulating layer. Cavities are provided among the wires. The cavities are filled with air or a mixture gas of oxygen and carbon dioxide. Wires are provided on the insulating layer. Cavities are provided among the wires. These cavities are filled with air or a mixture gas of oxygen and carbon dioxide.

Abstract: A reduced capacitance interconnect system. A first metal layer is formed to a predetermined level above a first dielectric layer which is formed on a semiconductor substrate. The first metal layer level forms multiple interconnect lines wherein each interconnect line is separated from each adjacent interconnect line by a trench including a trench having a highest aspect ratio. A second dielectric layer is formed on the first metal layer and in the trenches between the interconnect lines such that an enclosed void having a void tip substantially level with the top of the metal layer is formed in at least each trench having an aspect ratio above a predetermined minimum aspect ratio, wherein the enclosed void in the trench having the highest aspect ratio has a void volume which is at least 15% of the volume of the trench.