Having Air-gap Dielectric (e.g., Groove, Etc.) Patents (Class 438/421)
  • Patent number: 7148120
    Abstract: A method for forming a shallow trench isolation (STI) structure with improved electrical isolation performance including providing a semiconductor substrate including an overlying silicon oxide layer on the semiconductor substrate and a hardmask layer on the silicon oxide layer; dry etching in a first etching process to form a patterned hardmask opening for etching an STI opening; dry etching in a second etching process the semiconductor substrate to form an upper portion of an STI opening to form a polymer layer along sidewall portions of the STI opening; and, dry etching in a third etching process the STI opening to form rounded bottom corners and rounded top corners.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: December 12, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Jen Chen, Jen-Hsiang Leu, Yan-Chang Liu
  • Patent number: 7138329
    Abstract: An air gap structure and formation method for substantially reducing the undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device is disclosed. The air gap extends above, and may also additionally extend below, the interconnects desired to be isolated thus minimizing fringing fields between the lines. The integrated air gap structure and formation method can be utilized in conjunction with a tungsten plug process. Also, multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels while always ensuring that physical dielectric layer support is provided to the device structure underlying the interconnects.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: November 21, 2006
    Assignee: United Microelectronics Corporation
    Inventors: Water Lur, David Lee, Kuang-Chih Wang, Ming-Sheng Yang
  • Patent number: 7132348
    Abstract: Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure. One embodiment includes a solid structure of an insulator material, and a precisely determined arrangement of at least one void formed within the solid structure which lowers an effective dielectric constant of the insulator structure. One aspect is a method of forming a low-k insulator structure. In one embodiment, an insulator material is deposited, and a predetermined arrangement of at least one hole is formed in a surface of the insulator material. The insulator material is annealed such that the low-k dielectric material undergoes a surface transformation to transform the arrangement of at least one hole into predetermined arrangement of at least one empty space below the surface of the insulator material. Other aspects are provided herein.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: November 7, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Joseph E. Geusic, Paul A. Farrar, Arup Bhattacharyya
  • Patent number: 7125782
    Abstract: Methods of forming air gaps or porous dielectric materials between interconnects of integrated circuits and structures thereof. Air gaps or highly porous dielectric material having a dielectric constant of close to or equal to 1.0 are formed in a first region but not a second region of an interconnect layer. The air gaps or highly porous dielectric material are formed by depositing a first insulating material comprising an energy-sensitive material over a workpiece, depositing a second insulating material over the first insulating material, and exposing the workpiece to energy. At least a portion of the first insulating material in the first region is removed through the second insulating material. Structurally stable insulating material is disposed between conductive lines in the second region of the workpiece, providing mechanical strength for the integrated circuit.
    Type: Grant
    Filed: October 14, 2004
    Date of Patent: October 24, 2006
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Andreas Knorr, Bernd Kastenmeier, Naim Moumen
  • Patent number: 7118933
    Abstract: An optical bench on which an optical component is mounted comprises an Si substrate made of a silicon wafer, a groove disposed on the Si substrate and designed to mount the optical component thereon, and a metal thin-film wiring for driving the optical component or a driver component. The metal thin-film wiring is formed in an electroless plating process before a groove manufacturing process which forms the groove by micromachining by means of wet processing.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: October 10, 2006
    Assignee: Hitachi Maxell, Ltd.
    Inventors: Ryuzou Fukao, Tetsuhiko Sanbe
  • Patent number: 7118942
    Abstract: A method of mass-producing a solid state device comprises providing an atomically smooth, solid state material layer no more than 40 Angstroms thick. This layer is uniformly and defect-freely bonded onto a substrate to provide an acceptable device yield.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: October 10, 2006
    Inventor: Chou H. Li
  • Patent number: 7112542
    Abstract: Methods of forming insulating materials between conductive elements include forming a material adjacent a conductive electrical component comprising: partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. Other methods include forming a material between a pair of conductive electrical components comprising: forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. Some embodiments include an insulating material adjacent a conductive electrical component, such material comprising a matrix and at least one void within the matrix.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: September 26, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Werner Juengling, Kirk D. Prall, Ravi Iyer, Gurtej S. Sandhu, Guy Blalock
  • Patent number: 7105420
    Abstract: A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air columns to simultaneously exist underneath the inductor. Overlying layers of air cavities that are spatially inserted between the created overlying layers of oxide fins can be created under the invention by repetitive application of the mask used. The presence of the air wells on the surface of the substrate significantly reduces parasitic capacitances and series resistance of the inductor associated with the substrate.
    Type: Grant
    Filed: October 7, 1999
    Date of Patent: September 12, 2006
    Assignees: Chartered Semiconductor Manufacturing Ltd., National University of Singapore
    Inventors: Lap Chan, Kok Wai Johnny Chew, Cher Liang Cha, Chee Tee Chua
  • Patent number: 7105448
    Abstract: A method for peeling off a thin film semiconductor element over an insulating surface by using a void, and a method for manufacturing a semiconductor device by transferring the peeled semiconductor element. According to the peeling method of the invention, a first base layer having a plurality of recessed portions is formed over a substrate, and a second base layer having a plurality of voids is formed on the recessed portions of the first base layer. On the second base layer, a third base layer is formed and a semiconductor element is formed thereon. Then, by separating the second base layer at an intersecting surface with the voids, the semiconductor element is peeled off from the substrate.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: September 12, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Yasuyuki Arai
  • Patent number: 7094682
    Abstract: An improved electrical interconnect for an integrated circuit and methods for providing the same are disclosed. The electrical interconnect includes an air bridge extending through a gaseous medium so as to reduce the capacitance of the interconnect. The air bridge is supported at a first and second end such that the air bridge is suspended above the substrate. The air bridge comprises a highly conductive material, such as silver, so as to provide the air bridge with a reduced resistivity. To inhibit gaseous medium from contaminating the air bridge, the air bridge further comprises an adherent coating interposed between the air bridge and the gaseous medium. A method of forming the electrical interconnect is also disclosed, wherein, prior to forming the adherent coating, the conductive material is processed so as to form fewer grain boundaries, which enhances the electrical properties of the air bridge.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: August 22, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. Farrar
  • Patent number: 7091611
    Abstract: Structures and methods are provided for an improved multilevel wiring interconnect in an integrated circuit assembly. The present invention provides for a multilayer copper wiring structure by electroless, selectively deposited copper in a streamlined process which further reduces both intra-level line to line capacitance and the inter-level capacitance. In particular, an illustrative embodiment of the present invention includes a novel methodology for forming multilevel wiring interconnects in an integrated circuit assembly. The method includes forming a number of multilayer metal lines, e.g. copper lines formed by selective electroless plating, separated by air gaps above a substrate. A low dielectric constant material is deposited between the number of metal lines and the substrate using a directional process. According to the teachings of the present invention, using a directional process includes maintaining a number of air gaps in the low dielectric constant material.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: August 15, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7091092
    Abstract: A method for forming a self-aligned, recessed channel, MOSFET device that alleviates problems due to short channel and hot carrier effects while reducing inter-electrode capacitance is described. A thin pad oxide layer is grown overlying the substrate and a gate recess, followed by deposition of a thick silicon nitride layer filling the gate recess. The top surface is planarized exposing the pad oxide layer. An additional oxide layer is grown, thickening the pad oxide layer. A portion of the silicon nitride layer is etched away and additional oxide layer is again grown. This forms a tapered oxide layer along the sidewalls of the gate recess. The remaining silicon nitride layer is removed. The oxide layer at the bottom of the gate recess is removed and a gate dielectric layer is grown. Gate polysilicon is deposited filling the gate recess. S/D implantations, metallization, and passivation complete fabrication of the device.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: August 15, 2006
    Assignees: Chartered Semiconductor Manufacturing Ltd., National University of Singapore
    Inventors: Sneedharan Pillai Sneelal, Francis Poh, James Lee, Alex See, C. K. Lau, Ganesh Shankar Samudra
  • Patent number: 7078352
    Abstract: A method for the production of airgaps in a semiconductor device and device produced therefrom. The formation of airgaps is accomplished, in part, by chemically and/or mechanically changing the properties of a first dielectric layer locally, such that at least part of said first dielectric layer is converted locally and becomes etchable by a first etching substance. The local conversion of the dielectric material may be achieved during anisotropic etching of the material in oxygen containing plasma or ex-situ by performing an oxidizing step (e.g., a UV/ozone treatment or supercritical carbon dioxide with addition of an oxidizer). Formation of airgaps is achieved after creation of conductive lines and, alternatively, a barrier layer by a first etching substance. The airgaps are formed in a dual damascene structure, near the vias and/or the trenches of the damascene structure.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: July 18, 2006
    Assignees: Interuniversitair Microelektronica Centrum (IMEC vzw), Texas Instruments, Inc.
    Inventors: Gerald Beyer, Jean Paul Gueneau de Mussy, Karen Maex, Victor Sutcliffe
  • Patent number: 7078320
    Abstract: Disclosed is a method of manufacturing integrated circuit chips that partially joins an integrated circuit wafer to a supporting wafer at a limited number of joining points. Once joined, the integrated circuit wafer is chemically-mechanically polished to reduce the thickness of the integrated circuit wafer. Then, after reducing the thickness of the integrated circuit wafer, the invention performs conventional processing on the integrated circuit wafer to form devices and wiring in the integrated circuit wafer. Next, the invention cuts through the integrated circuit wafer and the supporting wafer to form chip sections. During this cutting process, the integrated circuit wafer separates from the supporting wafer in chip sections where the integrated circuit wafer is not joined to the supporting wafer by the joining points.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: July 18, 2006
    Assignee: International Business Machines Corporation
    Inventors: Louis C. Hsu, Hsichang Liu, James R. Salimeno, III
  • Patent number: 7071091
    Abstract: A method of forming air gaps surrounding conductors in a dielectric layer, the dielectric layer comprising, for example, part of the interconnect structure of an integrated circuit device. The air gaps are formed, in part, by depositing a sacrificial material within a trench and/or via that have been formed in a dielectric layer, and the sacrificial material is ultimately removed after metal deposition to create the air gaps. A porous dielectric cap may be deposited over the dielectric layer, and the sacrificial material may be removed through this porous dielectric layer. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 20, 2004
    Date of Patent: July 4, 2006
    Assignee: Intel Corporation
    Inventors: James S. Clarke, Michael D. Goodner
  • Patent number: 7049219
    Abstract: An improved electrical interconnect for an integrated circuit and methods for providing the same are disclosed. The electrical interconnect includes an air bridge extending through a gaseous medium so as to reduce the capacitance of the interconnect. The air bridge is supported at a first and second end such that the air bridge is suspended above the substrate. The air bridge comprises a highly conductive material, such as silver, so as to provide the air bridge with a reduced resistivity. To inhibit gaseous medium from contaminating the air bridge, the air bridge further comprises an adherent coating interposed between the air bridge and the gaseous medium. A method of forming the electrical interconnect is also disclosed, wherein, prior to forming the adherent coating, the conductive material is processed so as to form fewer grain boundaries, which enhances the electrical properties of the air bridge.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: May 23, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. Farrar
  • Patent number: 7041593
    Abstract: A main object of the present invention is to provide a manufacturing method of a thin-film structural body removing a sacrifice film without removing other insulating films. In order to achieve the above-mentioned object, upon forming an anchor hole (52) which forms an opening on the surface of a wiring (45), two etching steps are employed on a sacrifice film (51). In the first etching step, the sacrifice film (51) is partially removed by a dry etching process with an anisotropy above a wiring (45) with the sacrifice film (51) being left. In the second etching step, the remaining sacrifice film (51) above the wiring (45) is removed by a wet etching process with an isotropic.
    Type: Grant
    Filed: August 1, 2001
    Date of Patent: May 9, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Mika Okumura, Makio Horikawa, Kiyoshi Ishibashi
  • Patent number: 7037851
    Abstract: Method for the production of airgaps in a semiconductor device, the semiconductor device comprising a stack of layers, the stack of layers comprising at least one iteration of a sub-stack of layers.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: May 2, 2006
    Assignee: Interuniversitair Microelektronica Centrum (IMEC vzw)
    Inventors: Jean Paul Gueneau de Mussy, Gerald Beyer, Karen Maex
  • Patent number: 7033926
    Abstract: An interconnect arrangement comprises a substrate made from a first insulating material with a substrate surface, at least two interconnects which are arranged next to one another in the substrate, a buffer layer made from a second insulating material above the substrate and comprising a buffer-layer surface, which is parallel to the substrate surface, at least one cavity, which is arranged between the interconnects and, with respect to the buffer-layer surface, extends deeper into the substrate than the interconnects, and a covering layer made from a third insulating material, which is arranged above the buffer layer and completely closes off the cavity with respect to the buffer-layer surface.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: April 25, 2006
    Assignee: Infineon Technologies, AG
    Inventors: Günther Schindler, Werner Pamler, Zvonimir Gabric
  • Patent number: 7033868
    Abstract: A high-speed, low-power-consumption semiconductor device has a thin-film Si layer with a source/drain formed therein. The thin-film Si layer is curved from a region directly below a gate electrode toward a region near the source/drain. The curved thin-film Si layer develops strains in a channel region disposed directly below the gate electrode sandwiched by the source/drain in the thin-film Si layer, for thereby increasing a carrier mobility. A cavity is defined below the curved thin-film Si layer for reducing a parasitic capacitance due to a pn junction.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: April 25, 2006
    Assignee: Fujitsu Limited
    Inventors: Shunji Nakamura, Yosuke Shimamune
  • Patent number: 7033906
    Abstract: A component having an airdome enclosure that protects the component from its external environment. An airdome enclosure according to the present techniques avoids the high costs of employing special materials and/or specialized process steps in the manufacture of a component. An electronic component according to the present techniques includes a set of substructures formed on a substrate and an airdome enclosure over the substructures that protects the substructures and that hinders the formation of parasitic capacitances among the substructures.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: April 25, 2006
    Inventors: John Shi Sun Wei, Ray Myron Parkhurst, Michael James Jennison, Philip Gene Nikkel
  • Patent number: 7033867
    Abstract: The antifuse device comprises an insulating layer positioned in the trench, a conductive member positioned above the insulating layer, at least a portion of the conductive member being positioned within the trench, the conductive member adapted to have at least one programming voltage applied thereto, and at least one doped active region formed in the substrate adjacent the trench. The antifuse further comprises at least one conductive contact coupled to the conductive member, and at least one conductive contact coupled to the doped active region.
    Type: Grant
    Filed: March 4, 2004
    Date of Patent: April 25, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Stephen R. Porter
  • Patent number: 7022582
    Abstract: The present invention relates to a process for integrating air as dielectric in semiconductor devices, comprising the steps of: a. applying a layer of a dielectric (2) which is to be patterned to a substrate (1); b. patterning the dielectric layer (2) which has been applied; c. applying a conductor metal (3) for the patterned dielectric layer (2) and forming a common surface from the conductor metal (3) and the dielectric (2); d. applying a layer of an organic dielectric (4) to the layer produced in step c.; and e. bringing the coated substrate produced in this way into contact with a fluorine-containing compound in order to form an arrangement which has air as dielectric between conductor structures and has a continuous dielectric layer (4) on the top side, and to a semiconductor device with air layers as dielectric produced using this process.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: April 4, 2006
    Assignee: Infineon Technologies AG
    Inventor: Recai Sezi
  • Patent number: 7015147
    Abstract: A method for fabrication of silicon-on-nothing (SON) MOSFET using selective etching of Si1?xGex layer, includes preparing a silicon substrate; growing an epitaxial Si1?xGex layer on the silicon substrate; growing an epitaxial thin top silicon layer on the epitaxial Si1?xGex layer; trench etching of the top silicon and Si1?xGex, into the silicon substrate to form a first trench; selectively etching the Si1?xGex layer to remove substantially all of the Si1?xGex to form an air gap; depositing a layer of SiO2 by CVD to fill the first trench; trench etching to from a second trench; selectively etching the remaining Si1?xGex layer; depositing a second layer of SiO2 by CVD to fill the second trench, thereby decoupling a source, a drain and a channel from the substrate; and completing the structure by state-of-the-art CMOS fabrication techniques.
    Type: Grant
    Filed: July 22, 2003
    Date of Patent: March 21, 2006
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Jong-Jan Lee, Sheng Teng Hsu
  • Patent number: 7005717
    Abstract: Circuit (10) has a dual layer gate dielectric (29) formed over a semiconductor substrate (14). The gate dielectric includes an amorphous layer (40) and a monocrystalline layer (42). The monocrystalline layer typically has a higher dielectric constant than the amorphous layer.
    Type: Grant
    Filed: May 14, 2004
    Date of Patent: February 28, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kurt Eisenbeiser, Jun Wang, Ravindranath Droopad
  • Patent number: 6995073
    Abstract: Method and structure for integrating conductive and dielectric materials in a microelectronic structure having air gaps are disclosed. Certain embodiments of the invention comprise isolating dielectric layers from conductive layers using an etch stop layer to facilitate controlled removal of portions of the dielectric layers and formation of air gaps or voids. Capping and peripheral structural layers may be incorporated to increase the structural integrity of the integration subsequent to removal of sacrificial material.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: February 7, 2006
    Assignee: Intel Corporation
    Inventor: Huey-Chiang Liou
  • Patent number: 6992364
    Abstract: A TFT array substrate has a PAI pattern, and the PAI pattern has an over-etched portion of the pure amorphous silicon layer. This over-etched portion prevents a short between the pixel electrode and the pure amorphous silicon layer (i.e., the active layer).
    Type: Grant
    Filed: September 3, 2003
    Date of Patent: January 31, 2006
    Assignee: LG.Philips LCD Co., Ltd.
    Inventors: Soon-Sung Yoo, Dong-Yeung Kwak, Hu-Sung Kim, Yu-Ho Jung, Yong-Wan Kim, Duk-Jin Park, Woo-Chae Lee
  • Patent number: 6984577
    Abstract: A damascene interconnect that reduces interconnect intra-layer capacitance and/or inter-layer capacitance is provided. The damascene interconnect structure has air gaps between metal lines and/or metal layers. The interconnect structure is fabricated to a via level through a processing step prior to forming contact vias, then one or more air gaps are formed into the damascene structure so that the air gaps are positioned between selected metal lines. A sealing layer is then deposited over the damascene structure to seal the air gaps.
    Type: Grant
    Filed: September 20, 2000
    Date of Patent: January 10, 2006
    Assignee: Newport Fab, LLC
    Inventors: Bin Zhao, Maureen R. Brongo
  • Patent number: 6964911
    Abstract: A method for forming a semiconductor device having isolation structures decreases leakage current. A channel isolation structure decreases leakage current through a channel structure. In addition, current electrode dielectric insulation structures are formed under current electrode regions to prevent leakage between the current electrodes.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: November 15, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Marius K. Orlowski, Alexander L. Barr
  • Patent number: 6949444
    Abstract: A method for forming at least one conductive line intended to receive high-frequency or high-value currents, formed above a given portion of a solid substrate outside of which are formed other elements, including the steps of digging at least one trench in the solid substrate; forming an insulating area in the trench; and forming said conductive line above the insulating area.
    Type: Grant
    Filed: April 5, 2002
    Date of Patent: September 27, 2005
    Assignee: STMicroelectronics S.A.
    Inventors: Joaquim Torres, Vincent Arnal, Alexis Farcy
  • Patent number: 6943090
    Abstract: A typical air bridge is an aluminum conductor suspended across an air-filled cavity to connect two components of an integrated circuit, two transistors for example. The air-filled cavity has a low dielectric constant which reduces cross-talk between neighboring conductors and improves speed and efficiency of the integrated circuit. However, current air bridges must be kept short because typical aluminum conductors sag too much. Accordingly, one embodiment of the invention forms air-bridge conductors from an aluminum-beryllium alloy, which enhances stiffness and ultimately provides a 40-percent improvement in air-bridge lengths.
    Type: Grant
    Filed: April 6, 2004
    Date of Patent: September 13, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. Farrar
  • Patent number: 6940146
    Abstract: An interconnect is formed on the substrate. The conductive structure at least includes a first conductive structure and a second conductive structure, which have a gap region in-between. The substrate is exposed at the gap region. A first structured dielectric layer is formed over the substrate to cover the first and the second conductive structures. The first structured dielectric layer also has a void at the gap region between the first and the second conductive structures. The void significantly extends to the whole gap region. The first structured dielectric layer also has an indent region above the void. An anti-etch layer fills the indent region of the first structured dielectric layer. As a result, the first structured dielectric layer has a substantially planar surface. A second structured dielectric layer is formed on the first structured dielectric layer and the anti-etch layer.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: September 6, 2005
    Assignee: United Microelectronics Corp.
    Inventors: Ellis Lee, Tsing-Fong Hwang
  • Patent number: 6924222
    Abstract: An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer comprising a porous matrix, as well as a porogen in certain variations, is formed adjacent a sacrificial dielectric layer. Subsequent to other processing treatments, a portion of the sacrificial dielectric layer is decomposed and removed through a portion of the porous matrix using supercritical carbon dioxide leaving voids in positions previously occupied by portions of the sacrificial dielectric layer. The resultant structure has a desirably low k value as a result of the voids and materials comprising the porous matrix and other structures. The composite dielectric layer may be used in concert with other dielectric layers of varying porosity, dimensions, and material properties to provide varied mechanical and electrical performance profiles.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: August 2, 2005
    Assignee: Intel Corporation
    Inventors: Michael D. Goodner, Jihperng Leu
  • Patent number: 6921704
    Abstract: A method of forming a silicon-on-insulator semiconductor device including providing a substrate and forming a trench in the substrate, wherein the trench includes opposing side walls extending upwardly from a base of the trench. The method also includes depositing at least two insulating layers into the trench to form a shallow trench isolation structure, wherein an innermost of the insulating layers substantially conforms to the base and the two side walls of the trench and an outermost of the insulating layers spans the side walls of the trench so that a gap is formed between the insulating layers in the trench. The gap creates compressive forces within the shallow trench isolation structure, which in turn creates tensile stress within the surrounding substrate to enhance mobility of the device.
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: July 26, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David Wu, Akif Sultan, Bin Yu
  • Patent number: 6919259
    Abstract: A method for dry etching a feature to control an etching depth using endpoint detection and a sacrificial hardmask including providing a substrate for etching a feature opening into said substrate, said substrate provided with at least a first dielectric layer overlying the substrate; providing at least a second dielectric layer including a sacrificial hardmask at a predetermined thickness over the at least a first dielectric layer; photolithographically patterning and etching in a first dry etching process through a thickness of the at least a second dielectric layer and the at least a first dielectric layer to expose the substrate for dry etching the feature opening; and, dry etching in a second dry etching process the substrate and the sacrificial hardmask layer to endpoint detection of an underlying layer with respect to the sacrificial hardmask layer to thereby etch through a predetermined thickness of the substrate.
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: July 19, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Yao-Chi Chang, Jeff Lu
  • Patent number: 6916735
    Abstract: A temporary support layer 2 is formed on a semiconductor substrate 1, and the temporary support layer 2 is provided with a hole 4 that reaches the semiconductor substrate 1. The hole 4 is filled in with a conductor material 5, and by pressurizing the conductor material 5, the conductor material 5 and the semiconductor substrate 1 are pressure-bonded. Thereby, an aerial wiring structure whose bonding strength is improved and that has excellent self-sustainability can be obtained.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: July 12, 2005
    Assignee: Kabushiki Kaisha Kobe Seiko Sho
    Inventors: Takao Fujikawa, Tetsuya Yoshikawa
  • Patent number: 6913946
    Abstract: A method of making a semiconductor device comprising: providing a semiconductor substrate having a plurality of discrete devices formed therein, and a plurality of metal layers and support layers, the support layers comprising an uppermost support layer and other support layers, and wherein each metal layer has an associated support layer having at least a portion underlying the metal layer, and wherein the plurality of metal layers includes an uppermost metal layer including a sealing pad having an opening therethrough, and a passivation layer having at least one opening therein exposing a portion of the sealing pad including the opening therethrough, and the uppermost support layer having a portion exposed through the opening in the sealing pad; exposing the uppermost support layer to an etching material through the opening in the sealing pad and etching away the support layers; and sealing the opening in the sealing pad.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: July 5, 2005
    Assignee: Aptos Corporation
    Inventor: Charles Lin
  • Patent number: 6911404
    Abstract: A field effect transistor comprises a gate insulation layer including an anisotropic dielectric. The orientation is selected such that a first permittivity parallel to the gate insulation layer is significantly less than a second permittivity perpendicular to the gate insulation layer.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: June 28, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Karsten Wieczorek, Christian Radehaus
  • Patent number: 6908829
    Abstract: A method of forming an air gap intermetal layer dielectric (ILD) to reduce capacitive coupling between electrical conductors in proximity. The method entails forming first and second electrical conductors over a substrate, wherein the electrical conductors are laterally spaced apart by a gap. Then, forming a gap bridging dielectric layer that extends over the first electrical conductor, the gap, and the second electrical conductor. In order to form a bridge from one electrical conductor to the other electrical conductor, the gap bridging dielectric materials should have poor gap filling characteristics. This can be attained by selecting and/or modifying a dielectric material to have a sufficiently high molecular weight and/or surface tension characteristic such that the material does not substantially sink into the gap. An example of such a material is a spin-on-polymer with a surfactant and/or other additives.
    Type: Grant
    Filed: March 11, 2002
    Date of Patent: June 21, 2005
    Assignee: Intel Corporation
    Inventors: Makarem A. Hussein, Peter Moon, Jim Powers, Kevin P. O'Brien
  • Patent number: 6905938
    Abstract: The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method includes providing a semiconductor substrate and forming a first dielectric layer on the semiconductor substrate. Conductor structures are formed in the first dielectric layer. The partial first dielectric layer is removed by using the conductor structures as etching mask. A second dielectric layer is formed between the conductor structures, which has a dielectric constant smaller than the first dielectric layer. The second dielectric layer also alternatively has air voids contained therein to reduce dielectric constant.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: June 14, 2005
    Assignee: United Microelectronics Corp.
    Inventors: Ming-Sheng Yang, Chih-Chien Liu
  • Patent number: 6900110
    Abstract: A wafer level fabricated chip scale integrated circuit package having an air gap formed between the integrated circuit die of the package and compliant leads located over and conductively attached to the die is described. Contact bumps offset on the compliant leads provide for connection of the integrated circuit package to other substrates. In some embodiments, the compliant leads include a conductive layer overlaid with an outer resilient layer, and may further include an inner resilient layer beneath the conductive layer. The outer resilient layer has a via formed through it exposing the underlying conductive layer. The via is offset along the compliant lead a horizontal distance from the bond pad to which the compliant lead is conductively coupled. The chip scale package provides a highly compliant connection between the die and any substrate that the die is attached to.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: May 31, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Hem P. Takiar, Nikhil Vishwanath Kelkar
  • Patent number: 6890830
    Abstract: A semiconductor device of this invention includes a first interconnect pattern formed on a semiconductor substrate and a second interconnect pattern formed above the first interconnect pattern with an interlayer insulating film sandwiched therebetween. The first interconnect pattern includes a dummy pattern insulated from the first interconnect pattern, and the dummy pattern includes a plurality of fine patterns adjacent to each other and air gaps formed between the adjacent fine patterns.
    Type: Grant
    Filed: March 10, 2003
    Date of Patent: May 10, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Eiji Tamaoka, Hideo Nakagawa
  • Patent number: 6887766
    Abstract: A semiconductor device having an interlayer insulation film with a low capacitance and a method of fabricating the same are disclosed. An example semiconductor device having a multi-layered metal wire structure includes first and second interlayer insulation films provided between lower metal wire layers and upper metal wire layers. The example semiconductor device also includes air gaps formed in the first interlayer insulation film at an interlevel between the upper and lower metal wire layers and via holes connecting the upper and lower metal wire layers.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: May 3, 2005
    Assignee: ANAM Semiconductor Inc.
    Inventor: Kwan-Ju Koh
  • Patent number: 6881668
    Abstract: A method for controlling the position of air gaps in intermetal dielectric layers between conductive lines and a structure formed using such a method. A first dielectric layer is deposited over at least two features and a substrate and an air gap is formed between the at least two features and above the feature height. The first dielectric layer is etched between the at least two features to open the air gap. Then a second dielectric layer is deposited over the etched first dielectric layer to form an air gap between the at least two features and completely below the feature height.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: April 19, 2005
    Assignee: Mosel Vitel, Inc.
    Inventors: Tai-Peng Lee, Ching-Yueh Hu, Chuck Jang
  • Patent number: 6878578
    Abstract: A continuous and integrated cleaning/preparation process is described to condition a silicon surface for the formation of a high quality ultra thin gate oxide described. The process is conducted with the wafer surface immersed in an aqueous solution the composition of which is varied continuously according to the steps of the process. The process includes the initial removal of contaminants and particulates followed by the removal of a native oxide. Next the silicon surface is dressed in the present of both HF and ozone by removing a thin surface layer. Any interfacial contamination or surface structural defects which lay under the native oxide are thereby removed. Next a high quality chemical oxide is grown by the action of the ozone in the aqueous bath. The chemical oxide is found to be of higher purity and structural quality than native oxide and provides a superior passivation of the active surface prior to gate oxidation.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: April 12, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jih-Churng Twu, Tsung-Chieh Tsai, Roung-Hui Kao, Chia-Chun Cheng
  • Patent number: 6863769
    Abstract: A base body is provided, on which a first sealing ring and a second sealing ring are disposed. A substrate is disposed on the sealing rings in such a way that a cavity is formed between the first sealing ring, the second sealing ring, the base body and the substrate. An etching substance can be introduced into the cavity in order to etch clear a conductive layer that has been applied to the substrate. When a conductive layer that has been applied to the substrate back surface has been uncovered, an electrolyte can be introduced into the cavity, making contact with the conductive layer and therefore the substrate back surface.
    Type: Grant
    Filed: September 12, 2003
    Date of Patent: March 8, 2005
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Martin Franosch, Matthias Goldbach, Volker Lehmann, Jörn Lützen
  • Patent number: 6861333
    Abstract: A method of reducing trench aspect ratio. A trench is formed in a substrate. Using HDP-CVD, a conformal first oxide layer is formed on a surface of the trench. A conformal first nitride layer is formed on the first oxide layer. Part of the first nitride layer is removed to cause the first nitride layer to be lower than a top surface of the substrate. Using a BOE solution, the first nitride layer and part of the first oxide layer are removed to leave a remaining first oxide layer on the lower portion of the surface of the trench. Thus, the trench aspect ratio is reduced.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: March 1, 2005
    Assignee: Nanya Technology Corporation
    Inventors: Chang-Rong Wu, Seng-Hsiung Wu, Yi-Nan Chen
  • Patent number: 6861332
    Abstract: A low-k dielectric sacrificial material is formed within a microelectronic structure covered with a layer defining an exhaust vent. At an appropriate time, the underlying sacrificial material is decomposed and exhausted away through the exhaust vent. Residue from the exhausted sacrificial material accumulates at the vent location during exhaustion until the vent is substantially occluded. As a result, an air gap is created having desirable characteristics as a dielectric.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: March 1, 2005
    Assignee: Intel Corporation
    Inventors: Hyun-Mog Park, Grant M. Kloster
  • Patent number: 6855617
    Abstract: A method of filling intervals between protruding structures is provided. A substrate with a plurality of protruding structures thereon is provided. The protruding structures are distributed over the substrate such that intervals are formed between adjacent protruding structures. A first dielectric layer is formed over the substrate so that the dielectric material fills the intervals between the protruding structures and covers the protruding structures as well. The first dielectric layer has a plurality of apertures therein located at a level above a top section of the protruding structures. A chemical/mechanical polishing operation is performed to remove a portion of the dielectric layer and expose the apertures to form a plurality of openings. An anisotropic etching operation is performed to increase the width of these openings. Finally, a second dielectric layer is formed over the first dielectric layer to fill the openings completely.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: February 15, 2005
    Assignee: Macronix International Co., Ltd.
    Inventors: Chien-Hung Lu, Chin-Ta Su, Kuang-Chao Chen
  • Patent number: 6849870
    Abstract: Disclosed is an organic gate insulating film and an organic thin film transistor using the same, in which a photo-alignment group is introduced into an organic insulating polymer, so that an organic active film has superior alignment, thereby increasing mobility. Further, the organic active film has a larger grain size, enhancing transistor characteristics.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: February 1, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bon Won Koo, In Sung Song, In Seo Kee, Hwan Jae Choi, Eun Jeong Jeong, In Nam Kang