Having Air-gap Dielectric (e.g., Groove, Etc.) Patents (Class 438/421)
  • Patent number: 7811848
    Abstract: A method for the formation of buried cavities within a semiconductor body envisages the steps of: providing a wafer having a bulk region made of semiconductor material; digging, in the bulk region, trenches delimiting between them walls of semiconductor material; forming a closing layer for closing the trenches in the presence of a deoxidizing atmosphere so as to englobe the deoxidizing atmosphere within the trenches; and carrying out a thermal treatment such as to cause migration of the semiconductor material of the walls and to form a buried cavity. Furthermore, before the thermal treatment is carried out, a barrier layer that is substantially impermeable to hydrogen is formed on the closing layer on top of the trenches.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: October 12, 2010
    Assignee: STMicroelectronics S.R.L.
    Inventors: Gabriele Barlocchi, Pietro Corona, Dino Faralli, Flavio Francesco Villa
  • Patent number: 7790490
    Abstract: The invention concerns a manufacturing process, and the related micromachined capacitive ultra-acoustic transducer, that uses commercial silicon wafer 8 already covered on at least one or, more preferably, on both faces by an upper layer 9 and by a lower layer 9? of silicon nitride deposited with low pressure chemical vapour deposition technique, or deposition LPCVD deposition. One of the two layers 9 or 9? of silicon nitride, of optimal quality, covering the wafer 8 is used as emitting membrane of the transducer. As a consequence, the micro-cell array 6 forming the CMUT transducer is grown onto one of the two layers of silicon nitride, i.e. it is grown at the back of the transducer with a sequence of steps that is reversed with respect to the classical technology.
    Type: Grant
    Filed: March 2, 2006
    Date of Patent: September 7, 2010
    Assignees: Consiglio Nazionale Delle Ricerche, Esaote S.p.A.
    Inventors: Giosuè Caliano, Alessandro Caronti, Vittorio Foglietti, Elena Cianci, Antonio Minotti, Alessandro Nencioni, Massimo Pappalardo
  • Patent number: 7790567
    Abstract: Provided is a semiconductor and a method for forming the same. The method includes forming a buried insulating layer locally in a substrate. The substrate is etched to form an opening exposing the buried insulating layer, and a silicon pattern spaced in at least one direction from the substrate is formed on the buried insulating layer. A first insulating layer is formed to enclose the silicon pattern.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: September 7, 2010
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: O-Kyun Kwon, Dong-Woo Suh, Jung-Hyung Pyo, Gyung-Ock Kim
  • Patent number: 7772062
    Abstract: A transistor, such a MOSFET, having an epitaxially grown strain layer disposed over a channel region of a substrate for stressing the channel region to increase the carrier mobility in the channel, and method for making same. The strain layer is composed of a high dielectric constant material.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: August 10, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Min Cao
  • Patent number: 7767592
    Abstract: A method for forming a mask pattern for ion-implantation comprises: forming a gate line pattern over a semiconductor substrate; forming a coating layer on the surface of gate line pattern; performing a plasma treatment on the top portion of the gate line pattern; forming a photoresist layer over the resulting structure; and performing an exposure and a developing processes to form a photoresist pattern on the gate line pattern.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: August 3, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kyu Sung Kim
  • Patent number: 7749891
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a plurality of lower interconnections at intervals in a first insulating film; removing a portion of the first insulating film located between the lower interconnections, thereby forming an interconnection-to-interconnection gap; forming a second insulating film over the first insulating film in which the lower interconnections and the interconnection-to-interconnection gap are formed such that an air gap is formed out of the interconnection-to-interconnection gap; and forming, in the second insulating film, a connection portion connected to one of the lower interconnections and an upper interconnection connected to the connection portion. The connection portion is formed to be connected to one of the lower interconnections not adjacent to the air gap.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: July 6, 2010
    Assignee: Panasonic Corporation
    Inventor: Tetsuya Ueda
  • Publication number: 20100163974
    Abstract: A method for fabricating a semiconductor device including a vertical channel transistor includes providing a substrate including a semiconductor pillar, forming a gate electrode surrounding the semiconductor pillar, forming an impurity region for a bit line by doping impurities into the substrate and forming a device isolation trench by etching a portion of the substrate including the impurity region to a certain depth, thereby defining the bit line, wherein the impurity doping is performed with given concentration so as to form the impurity region under the semiconductor pillar.
    Type: Application
    Filed: June 26, 2009
    Publication date: July 1, 2010
    Inventor: Seung-Chul Oh
  • Patent number: 7745272
    Abstract: A semiconductor device has a heterostructure including a first layer of semiconductor oxide material. A second layer of semiconductor oxide material is formed on the first layer of semiconductor oxide material such that a two dimensional electron gas builds up at an interface between the first and second materials. A passivation layer on the outer surface stabilizes the structure. The device also has a source contact and a drain contact.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: June 29, 2010
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Christian G. Van de Walle, Kiesel Peter, Oliver Schmidt
  • Patent number: 7741663
    Abstract: Miniaturized complex transistor devices are formed with reduced leakage and reduced miller capacitance. Embodiments include transistors having reduced capacitance between the gate electrode and source/drain contact, as by utilizing a low-K dielectric constant sidewall spacer material. An embodiment includes forming a gate electrode on a semiconductor substrate, forming a sidewall spacer on the side surfaces of the gate electrode, forming source/drain regions by ion implantation, forming an interlayer dielectric over the gate electrode, sidewall spacers, and substrate, and forming a source/drain contact through the interlayer dielectric. The sidewall spacers and interlayer dielectric are then removed. A dielectric material, such as a low-K dielectric material, is then deposited in the gap between the gate electrode and the source/drain contact so that an air gap is formed, thereby reducing the parasitic “miller” capacitance.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: June 22, 2010
    Assignee: Globalfoundries Inc.
    Inventors: Fred Hause, Anthony C. Mowry, David G. Farber, Markus E. Lenski
  • Patent number: 7741191
    Abstract: Densely spaced gates of field effect transistors usually lead to voids in a contact interlayer dielectric. If such a void is opened by a contact via and filled with conductive material, an electrical short between neighboring contact regions of neighboring transistors may occur. By forming a recess between two neighboring contact regions, the void forms at a lower level. Thus, opening of the void by contact vias is prevented.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: June 22, 2010
    Assignee: GlobalFoundries Inc.
    Inventors: Kai Frohberg, Sven Mueller, Frank Feustel
  • Publication number: 20100144112
    Abstract: Methods of forming air gaps between interconnects of integrated circuits and structures thereof are disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.
    Type: Application
    Filed: November 13, 2009
    Publication date: June 10, 2010
    Inventors: Markus Naujok, Hermann Wendt, Alois Gutmann, Muhammed Shafi Pallachalil
  • Patent number: 7732322
    Abstract: In a first aspect, a first method of manufacturing a dielectric material with a reduced dielectric constant is provided. The first method includes the steps of (1) forming a dielectric material layer including a trench on a substrate; and (2) forming a cladding region in the dielectric material layer by forming a plurality of air gaps in the dielectric material layer along at least one of a sidewall and a bottom of the trench so as to reduce an effective dielectric constant of the dielectric material. Numerous other aspects are provided.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: June 8, 2010
    Assignee: International Business Machines Corporation
    Inventors: Louis Lu-Chen Hsu, Jack Allan Mandelman, Chih-Chao Yang
  • Patent number: 7732888
    Abstract: According to one embodiment of the present invention, a memory cell array comprises a plurality of voids, the spatial positions and dimensions of the voids being chosen such that mechanical stress occurring within the memory cell array is at least partly compensated by the voids.
    Type: Grant
    Filed: April 16, 2007
    Date of Patent: June 8, 2010
    Assignees: Qimonda AG, Altis Semiconductor, SNC
    Inventors: Wolfgang Raberg, Cay-Uwe Pinnow
  • Patent number: 7727878
    Abstract: A method for forming a passivation layer is disclosed. In the method, a substrate containing a top surface and a bottom surface opposite to the top surface is first provided, wherein a plurality of conductive pads are disposed on the top surface thereof. Thereafter, a first passivation layer is formed on the top surface of the substrate, wherein the first passivation layer has a characteristic of photoresist. A first exposure/develop step is then performed to form a plurality of first openings in the first passivation layer, wherein the conductive pads are exposed through the first openings. Then, a second passivation layer is formed on the first passivation layer, wherein the second passivation layer has a characteristic of photoresist. A second exposure/develop step is then performed to form a plurality of second openings in the second passivation layer, wherein the conductive pads are exposed through the second openings.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: June 1, 2010
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventors: Cheng-Hsueh Su, Hsing-Fu Lu, Tsung-Chieh Ho, Shyh-Ing Wu
  • Patent number: 7729171
    Abstract: The invention provides methods and apparatus. A portion of a memory array has a string of two or more non-volatile memory cells, a first select gate coupled in series with one non-volatile memory cell of the string of two or more non-volatile memory cells, and a second select gate coupled in series with the first select gate. A length of the second select gate is greater than a length of the first select gate.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: June 1, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Seiichi Aritome
  • Patent number: 7704851
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate with gate structures. A sacrificial insulating layer is formed between the gate structures at a height lower than that of the gate structures such that a portion of each gate structure is exposed above the sacrificial insulating layer. Spacers are formed on sidewalls of the exposed portions of the gate structures. A portion of the sacrificial insulating layer between the spacers is exposed. The sacrificial insulating layer is removed, thereby forming spaces below the spacers. An insulating layer is formed to fill the spaces between the spacers such that air pockets are formed between the gate structures and below the spacers.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: April 27, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Soo Jin Kim
  • Publication number: 20100084732
    Abstract: Disclosed herein is a method of manufacturing a semiconductor device that is adapted to improve the production yield. The method generally includes etching a semiconductor substrate to form a trench, filling the trench with a conductive material, separating the filled conductive material to form a plurality of gate patterns and a bit line contact region, and etching the substrate to define an isolation region.
    Type: Application
    Filed: December 29, 2008
    Publication date: April 8, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Yong Won Seo
  • Patent number: 7692264
    Abstract: A semiconductor device and a method for manufacturing the same are provided. A gate insulating film is formed under a vacuum condition to prevent deterioration of reliability of the device due to degradation of a gate insulating material and to have stable operating characteristics. The semiconductor device includes an element isolating film formed at element isolating regions of a semiconductor substrate, which is divided into active regions and the element isolating regions; a gate insulating film having openings with a designated width formed at the active regions of the semiconductor substrate; gate electrodes formed on the gate insulating film; and lightly doped drain regions and source/drain impurity regions formed in the surface of the semiconductor substrate at both sides of the gate electrodes.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: April 6, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Dong Joon Lee
  • Patent number: 7687369
    Abstract: A method of forming fine metal interconnect patterns includes forming an insulating film on a substrate, forming a plurality of mold patterns with first spaces therebetween on the insulating film, such that the mold patterns have a first layout, forming metal hardmask patterns in the first spaces by a damascene process, removing the mold patterns, etching the insulating film through the metal hardmask patterns to form insulating film patterns with second spaces therebetween, the second spaces having the first layout, and forming metal interconnect patterns having the first layout in the second spaces by the damascene process.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: March 30, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Cha-won Koh, Jeong-lim Nam, Gi-sung Yeo, Sang-jin Kim, Sung-gon Jung
  • Patent number: 7682963
    Abstract: The present disclosure provides a method for fabricating an integrated circuit. The method includes forming an energy removable film (ERF) on a substrate; forming a first dielectric layer on the ERF; patterning the ERF and first dielectric layer to form a trench in the ERF and the first dielectric layer; filling a conductive material in the trench; forming a ceiling layer on the first dielectric layer and conductive material filled in the trench; and applying energy to the ERF to form air gaps in the ERF after the forming of the ceiling layer.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: March 23, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hai-Ching Chen, Sunil Kumar Singh, Tien-I Bao, Shau-Lin Shue, Chen-Hua Yu
  • Patent number: 7678661
    Abstract: Embodiments relate to semiconductor device and a method of forming an insulating layer with a low dielectric constant in a semiconductor device. The method may include forming a plurality of metal patterns on a semiconductor substrate, depositing a first insulating layer on the entire surface of the semiconductor substrate having the plurality of metal patterns, depositing an etch stop layer on the first insulating layer, depositing a second insulating layer on the etch stop layer, removing the second insulating layer until the etch stop layer formed above each of the plurality of metal patterns is exposed, etching the exposed etch stop layer, and depositing a third insulating layer on the entire surface of the semiconductor substrate.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: March 16, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Seung Hyun Kim
  • Patent number: 7670924
    Abstract: Methods are provided for forming a structure that includes an air gap. In one embodiment, a method is provided for forming a damascene structure comprises depositing a porous low dielectric constant layer by a method including reacting an organosilicon compound and a porogen-providing precursor, depositing a porogen-containing material, and removing at least a portion of the porogen-containing material, depositing an organic layer on the porous low dielectric constant layer by reacting the porogen-providing precursor, forming a feature definition in the organic layer and the porous low dielectric constant layer, filing the feature definition with a conductive material therein, depositing a mask layer on the organic layer and the conductive material disposed in the feature definition, forming apertures in the mask layer to expose the organic layer, removing a portion or all of the organic layer through the apertures, and forming an air gap adjacent the conductive material.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: March 2, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Alexandros T. Demos, Li-Qun Xia, Bok Hoen Kim, Derek R. Witty, Hichem M'Saad
  • Patent number: 7671442
    Abstract: Air-gap insulated interconnection structures and methods of fabricating the structures, the methods including: forming a dielectric layer on a substrate; forming a capping layer on a top surface of the dielectric layer; forming a trench through the capping layer, the trench extending toward said substrate and into but not through, the dielectric layer; forming a sacrificial layer on opposing sidewalls of the trench; filling the trench with a electrical conductor; and removing a portion of the sacrificial layer from between the electrical conductor and the dielectric layer to form air-gaps.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: March 2, 2010
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Andres Bryant, Jeffrey P. Gambino, Anthony K. Stamper
  • Publication number: 20100047994
    Abstract: After forming a stack of layers (130, 140, 310) for a transistor or a charge-trapping memory over an active area (110), and before etching isolation trenches (160) in the semiconductor substrate (120) with the stack as a mask, spacers (610) are formed on the stack's sidewalls. The trench etch may include a lateral component, so the top edges of the trenches may be laterally recessed to a position under the spacers or the stack. After the etch, the spacers are removed to facilitate filling the trenches with the dielectric (to eliminate voids at the recessed top edges of the trenches). Other embodiments are also provided.
    Type: Application
    Filed: August 21, 2008
    Publication date: February 25, 2010
    Inventors: Zhong Dong, Ching-Hwa Chen
  • Patent number: 7666754
    Abstract: A method for forming an air gap structure on a substrate is described. The method comprises forming a sacrificial layer on a substrate, wherein the sacrificial layer comprises a decomposable material that thermally decomposes at a thermal decomposition temperature above approximately 350 degrees C. Thereafter, a cap layer is formed on the sacrificial layer at a substrate temperature less than the thermal decomposition temperature of the sacrificial layer. The sacrificial layer is decomposed by performing a first exposure of the substrate to ultraviolet (UV) radiation and heating the substrate to a first temperature less than the thermal decomposition temperature of the sacrificial layer, and the decomposed sacrificial layer is removed through the cap layer. The cap layer is cured to cross-link the cap layer by performing a second exposure of the substrate to UV radiation and heating the substrate to a second temperature greater than the first temperature.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: February 23, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Dorel I. Toma, Junjun Liu
  • Patent number: 7666753
    Abstract: The embodiments of the invention provide a metal capping process for a BEOL interconnect with air gaps. More specifically an apparatus is provided comprising metal lines within a first dielectric. Metal caps are over the metal lines, wherein the metal caps contact the metal lines. In addition, air gaps are between the metal lines, wherein the air gaps are between the metal caps. A second dielectric is also provided over the bottom portion of a first dielectric, wherein a top portion of the second dielectric is over the metal caps, and wherein top portions of the first dielectric and bottom portions of the second dielectric comprise sides of the air gap. The apparatus further includes dielectric caps over the metal lines, wherein the dielectric caps contact the metal caps.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: February 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Griselda Bonilla, Shyng-Tsong Chen, Matthew E. Colburn, Chih-Chao Yang
  • Patent number: 7649239
    Abstract: A plurality of metal interconnects incorporating dielectric spacers and a method to form such dielectric spacers are described. In one embodiment, the dielectric spacers adjacent to neighboring metal interconnects are discontiguous from one another. In another embodiment, the dielectric spacers may provide a region upon which un-landed vias may effectively land.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: January 19, 2010
    Assignee: Intel Corporation
    Inventors: Makarem A. Hussein, Boyan Boyanov
  • Publication number: 20100001368
    Abstract: Integrated circuit (1) comprising a substrate (2), an active component (13) above the substrate (2), a cavity (14) surrounding partially the active component (13), a low dielectric region (15) surrounding partially the cavity (14) and a protective barrier (16) arranged around the low dielectric region (15).
    Type: Application
    Filed: August 24, 2006
    Publication date: January 7, 2010
    Inventors: Clement Charbuillet, Laurent Gosset
  • Publication number: 20090315101
    Abstract: A method of forming a notched-base spacer profile for non-planar transistors includes providing a semiconductor fin having a channel region on a substrate and forming a gate electrode adjacent to sidewalls of the channel region and on a top surface of the channel region, the gate electrode having on a top surface a hard mask. a spacer layer is deposited over the gate and the fin using a enhanced chemical vapor deposition (PE-CVD) process. A multi-etch process is applied to the spacer layer to form a pair of notches on laterally opposite sides of the gate electrode, wherein each notch is located adjacent to sidewalls of the fin and on the top surface of the fin.
    Type: Application
    Filed: June 24, 2008
    Publication date: December 24, 2009
    Inventors: Willy Rachmady, Jack Kavalieros
  • Patent number: 7629225
    Abstract: Methods of forming air gaps between interconnects of integrated circuits and structures thereof are disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: December 8, 2009
    Assignee: Infineon Technologies AG
    Inventors: Markus Naujok, Hermann Wendt, Alois Gutmann, Muhammed Shafi Pallachalil
  • Publication number: 20090298256
    Abstract: A semiconductor package including an interconnect air gap and method for making the same. The semiconductor package includes a dielectric layer, a metallic interconnect, an air gap disposed between the dielectric layer and interconnect, and a spacer interspersed between the metallic interconnect and air gap. The metallic interconnect is laterally supported by and isolated from the air gap by the spacer. A method for making the same is also provided.
    Type: Application
    Filed: June 3, 2008
    Publication date: December 3, 2009
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsien-Wei Chen, Shin-Puu Jeng, Hao-Yi Tsai
  • Publication number: 20090294895
    Abstract: An integrated circuit includes an array of transistors and wordlines, where individual wordlines are coupled to a number of the transistors. Conductive structures that are insulated from the wordlines are disposed in a layer beneath the wordlines and are arranged between the transistors.
    Type: Application
    Filed: May 28, 2008
    Publication date: December 3, 2009
    Applicant: QIMONDA AG
    Inventor: Franz Hofmann
  • Publication number: 20090294898
    Abstract: Air gaps may be provided in a self-aligned manner with sub-lithography resolution between closely spaced metal lines of sophisticated metallization systems of semiconductor devices by recessing the dielectric material in the vicinity of the metal lines and forming respective sidewall spacer elements. Thereafter, the spacer elements may be used as an etch mask so as to define the lateral dimension of a gap on the basis of the corresponding air gaps, which may then be obtained by depositing a further dielectric material.
    Type: Application
    Filed: March 10, 2009
    Publication date: December 3, 2009
    Inventors: Frank Feustel, Thomas Werner, Kai Frohberg
  • Patent number: 7622368
    Abstract: A method for forming a single-crystal semiconductor layer portion above a hollowed area, including growing by selective epitaxy on an active single-crystal semiconductor region a sacrificial single-crystal semiconductor layer and a single-crystal semiconductor layer, and removing the sacrificial layer. The epitaxial growth is performed while the active region is surrounded with a raised insulating layer and the removal of the sacrificial single-crystal semiconductor layer is performed through an access resulting from an at least partial removal of the raised insulating layer.
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: November 24, 2009
    Assignee: STMicroelectronics S.A.
    Inventors: Didier Dutartre, Nicolas Loubet, Alexandre Talbot
  • Patent number: 7622359
    Abstract: A method for manufacturing a semiconductor device, includes: (a) forming a SiGe layer on a Si substrate; (b) forming a Si layer on the SiGe layer; (c) forming a dummy pattern made of SiGe in a dummy region of the Si substrate; and (d) wet-etching and removing the SiGe layer formed under the Si layer. In the step (d), an etchant is kept to contact the dummy pattern from before a complete remove of the SiGe layer to an end of the etching.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: November 24, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Juri Kato, Kei Kanemoto
  • Publication number: 20090246932
    Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming, on a surface of a semiconductor substrate, an isolation trench including sidewall parts and a bottom part, or a stepped structure including a first planar part, a second planar part, and a step part located at a boundary between the first planar part and the second planar part, and supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure by applying a predetermined voltage to the semiconductor substrate, to perform anisotropic oxidation or anisotropic nitridation of the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure.
    Type: Application
    Filed: March 27, 2009
    Publication date: October 1, 2009
    Inventors: Isao KAMIOKA, Junichi SHIOZAWA, Ryu KATO, Yoshio OZAWA
  • Publication number: 20090230505
    Abstract: The invention provides a memory cell based on variable resistance material memory element that includes an access device having a pillar structure that may also include a protective sidewall layer. The pillar access device selects and isolates the memory cell from other memory array cells and is adapted to both self-align any memory element formed thereon, and to deliver suitable programming current to the memory element. The pillar structure is formed from one or more access device layers stacked above a wordline and below the memory element. Optional resistive layers may be selectively formed within the pillar structure to minimize resistance in the access device layer and the memory element. The pillar access device may be a diode, transistor, Ovonic threshold switch or other device capable of regulating current flow to an overlying programmable memory material.
    Type: Application
    Filed: March 14, 2008
    Publication date: September 17, 2009
    Inventor: Charles H. Dennison
  • Patent number: 7585785
    Abstract: A method of forming an air gap within a semiconductor structure by the steps of: (a) using a sacrificial polymer to occupy a space in a semiconductor structure; and (b) heating the semiconductor structure to decompose the sacrificial polymer leaving an air gap within the semiconductor structure, wherein the sacrificial polymer of step (a) is a copolymer of bis[3-(4-benzocyclobutenyl)]1,n (n=2-12) alkyldiol diacrylate (such as bis[3-(4-benzocyclobutenyl)]1,6 hexanediol diacrylate) and 1,3 bis 2[4-benzocyclobutenyl(ethenyl)]benzene. In addition, a semiconductor structure, having a sacrificial polymer positioned between conductor lines, wherein the sacrificial polymer is a copolymer of bis[3-(4-benzocyclobutenyl)]1,n (n=2-12)alkyldiol diacrylate and 1,3 bis 2[4-benzocyclobutenyl(ethenyl)]benzene.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: September 8, 2009
    Assignee: Dow Global Technologies
    Inventors: Robert A. Kirchhoff, Jason Q. Niu, Yongfu Li, Kenneth L. Foster
  • Patent number: 7585744
    Abstract: In one embodiment, a reflowable layer 51 is deposited over a semiconductor device 10 and reflowed in an environment having a pressure approximately equal to that of atmosphere to form a seal layer 52. The seal layer 52 seals all openings 43 in the underlying layer of the semiconductor device 10. Since the reflow is performed at approximately atmospheric pressure a gap 50 which was coupled to the opening 43 is sealed at approximately atmospheric pressure, which is desirable for the semiconductor device 10 to avoid oscillation. The seal layer 52 is also desirable because it prevents particles from entering the gap 50. In another embodiment, the seal layer 52 is deposited in an environment having a pressure approximately equal to atmospheric pressure to seal the hole 43 without a reflow being performed.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: September 8, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Bishnu P. Gogoi, Raymond M. Roop, Hemant D. Desai
  • Patent number: 7585743
    Abstract: A method for manufacturing a semiconductor substrate of a first concentration type is described, which comprises at least a buried insulating cavity, comprising the following steps: forming on the semiconductor substrate a plurality of trenches, forming a surface layer on the semiconductor substrate in order to close superficially the plurality of trenches forming in the meantime at least a buried cavity in correspondence with the surface-distal end of the trenches.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: September 8, 2009
    Assignee: STMicroelectronics S.r.l.
    Inventors: Crocifisso Marco Antonio Renna, Luigi La Magna, Simona Lorenti, Salvatore Coffa
  • Publication number: 20090189213
    Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate having a plurality of active regions separately formed by a plurality of trenches formed in a surface of the substrate at predetermined intervals, a first gate insulating film formed on an upper surface of the substrate corresponding to each active region, a gate electrode of a memory cell transistor formed by depositing an electrical charge storage layer formed on an upper surface of the gate insulating film, a second gate insulating film and a control gate insulating film sequentially, an element isolation insulating film buried in each trench and formed from a coating type oxide film, and an insulating film formed inside each trench on a boundary between the semiconductor substrate and the element isolation insulating film, the insulating film containing nontransition metal atoms and having a film thickness not more than 5 ?.
    Type: Application
    Filed: January 15, 2009
    Publication date: July 30, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuhiro MATSUO, Masayuki TANAKA, Atsuhiro SUZUKI
  • Patent number: 7560344
    Abstract: Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: July 14, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-pil Kim, Yoon-dong Park, Jong-jin Lee, Won-joo Kim, June-mo Koo, Seung-hwan Song
  • Publication number: 20090170275
    Abstract: A method for manufacturing a semiconductor device includes forming a spin-on-carbon (SOC) film that facilitates a low temperature baking process, can prevent collapse of vertical transistors while forming a bit line, thereby providing a more simple manufacturing method and improving manufacturing yields.
    Type: Application
    Filed: June 26, 2008
    Publication date: July 2, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventor: Keun Do Ban
  • Publication number: 20090170276
    Abstract: The present invention relates to a method of forming trenches of a semiconductor device. According to the method, a hard mask pattern is formed on a semiconductor substrate so that an isolation region of the semiconductor substrate is opened. First trenches are formed in the isolation region by performing a first etch process employing the hard mask pattern. A spacer is formed on sidewalls of the first trenches. Second trenches, having a depth deeper than that of the first trenches, are formed in the isolation region by performing a second etch process employing the hard mask pattern.
    Type: Application
    Filed: June 26, 2008
    Publication date: July 2, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Choong Bae Kim
  • Publication number: 20090170277
    Abstract: A method for semiconductor processing is provided, wherein a removal of one or more layers is aided by structurally weakening the one or more layers via ion implantation. A semiconductor substrate is provided having one or more primary layers formed thereon, and a secondary layer is formed over the one or more primary layers. One or more ion species are implanted into the secondary layer, therein structurally weakening the secondary layer, and a patterned photoresist layer is formed over the secondary layer. Respective portions of the secondary layer and the one or more primary layers that are not covered by the patterned photoresist layer are removed, and the patterned photoresist layer is further removed. At least another portion of the secondary layer is removed, wherein the structural weakening of the secondary layer increases a removal rate of the at least another portion of the secondary layer.
    Type: Application
    Filed: December 29, 2008
    Publication date: July 2, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Mahalingam Nandakumar, Wayne Bather, Narendra Singh Mehta
  • Patent number: 7553756
    Abstract: An object of the present invention is to prevent formation of a badly situated via metal in a Damascene wiring portion in multiple layers having an air-gap structure. In the present invention, a via is completely separated from an air-gap 45 by forming an interlayer insulating film 44 having the air-gap 45 between adjacent Damascene wiring portions after forming a sacrifice film pillar 42 from a selectively removable insulating film in a formation region of a connection hole. The present invention can provide multiple-layered buried wiring in which a high reliable via connection and a reduced parasitic capacitance due to the air-gap are achieved.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: June 30, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Hayashi, Takayuki Oshima, Hideo Aoki
  • Patent number: 7553739
    Abstract: An improved semiconductor device, integrated circuit, and integrated circuit fabrication method introduce highly controlled air cavities within high-speed copper interconnects. A polymer material is introduced on the edges of interconnect lines and vias within an interconnect stack. This incorporates and controls air cavities formation, thus enhancing the signal propagation performance of the semiconductor interconnects.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: June 30, 2009
    Assignees: STMicroelectronics (Corlles 2) SAS, Koninklijke Philips Electronics N.V.
    Inventors: Joaquin Torres, Laurent-Georges Gosset
  • Publication number: 20090160015
    Abstract: In a power semiconductor device and a method of forming a power semiconductor device, a thin layer of semiconductor substrate is left below the drift region of a semiconductor device. A power semiconductor device has an active region that includes the drift region and has top and bottom surfaces formed in a layer provided on a semiconductor substrate. A portion of the semiconductor substrate below the active region is removed to leave a thin layer of semiconductor substrate below the drift region. Electrical terminals are provided directly or indirectly to the top surface of the active region to allow a voltage to be applied laterally across the drift region.
    Type: Application
    Filed: December 20, 2007
    Publication date: June 25, 2009
    Applicant: Cambridge Semiconductor Limited
    Inventors: Florin UDREA, Gehan Anil Joseph Amaratunga, Tanya Trajkovic, Vasantha Pathirana
  • Publication number: 20090152673
    Abstract: Provided is a semiconductor and a method for forming the same. The method includes forming a buried insulating layer locally in a substrate. The substrate is etched to form an opening exposing the buried insulating layer, and a silicon pattern spaced in at least one direction from the substrate is formed on the buried insulating layer. A first insulating layer is formed to enclose the silicon pattern.
    Type: Application
    Filed: May 30, 2008
    Publication date: June 18, 2009
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: O-Kyun KWON, Dong-Woo SUH, Junghyung PYO, Gyung-Ock KIM
  • Publication number: 20090137093
    Abstract: A method of forming a FINFET device includes providing a substrate with a plurality of trench devices arranged in array therein, each of the trench devices comprising a plug protruding above the substrate; forming a plurality of isolation structures along a first direction in the substrate adjacent to the trench devices so as to define an active area exposing the substrate; forming a spacer on each of the plug to define a reactive area between the active area and the spacer; and removing the isolation structures on the reactive area to form a fin structure in the active area.
    Type: Application
    Filed: April 10, 2008
    Publication date: May 28, 2009
    Applicant: NANYA TECHNOLOGY CORP.
    Inventor: Shian-Jyh LIN