Abstract: A hybrid process combines a thin-film surface micromachining process such as by sputtering, evaporation or chemical vapor deposition with a thick-film surface micromachining and release process such as dry-film lamination. Such combination results in thin film micro-structures with all the benefits of surface micromachining without the typical problems of stiction and limited range of motion.

Abstract: One aspect of the present invention relates to a method of forming an advanced low k material between metal lines on a semiconductor substrate, involving the steps of providing the semiconductor substrate having a plurality of metal lines thereon; depositing a spin-on material over the semiconductor substrate having the plurality of metal lines thereon; and at least one of heating or etching the semiconductor substrate whereby at least a portion of the spin-on material is removed, thereby forming the advanced low k material comprising at least one air void between the metal lines, the advanced low k material having a dielectric constant of about 2 or less.

Abstract: An air gap semiconductor structure and corresponding method of manufacture. The method includes forming a sacrificial polymer film over a substrate having metal lines thereon. A portion of the sacrificial polymer film is subsequently removed to form first spacers. A micro-porous structure layer is formed over the substrate and the metal lines and between the first spacers. A portion of the micro-porous structure layer is removed to form second spacers. The first spacers are removed by thermal dissociation to form air gaps. A dielectric layer is formed over the substrate and the metal lines and between the second spacers.

Abstract: A method of making a semiconductor device (10) includes filling a plurality of trenches (30, 32-34) in a substrate (11) with a first fill material (40, 42-44) and lined with a first liner material (36-39) to form an isolation structure (50) in a first trench (30). The first fill material and the first liner material are removed from a second trench (33) which is then lined with a second liner material (46) and filled with a second fill material (69) to produce a capacitance to the substrate. The first fill material and the first liner material are removed from a third trench (34), which is filled with the second fill material to form an electrical contact to the substrate. The first fill material is removed from a fourth trench (34) and dielectric material (78) is deposited on the substrate to produce a void (83) in the fourth trench.

Abstract: A process for forming air gap isolation regions between a bit line contact structure and adjacent capacitor structures, to reduce the capacitance of the space between these structures, has been developed. The process features the formation of insulator spacers on the sides of capacitor openings. After formation of capacitor structures, in the capacitor openings, top portions of the insulator spacers are exposed via a first selective etch procedure, allowing a second, selective, isotropic etch procedure to completely remove the insulator spacers creating the air gap isolation regions now located between the capacitor structure and an adjacent insulator layer. Subsequent deposition of an overlying insulator layer, comprised with poor conformality properties, allows coverage of the capacitor structures, however without filling the air gap isolation regions.

Abstract: An integrated circuit having at least one electrical interconnect for connecting at least two components and a process for forming the same are disclosed.

Abstract: A semiconductor device is fabricated first by thermocompression-bonding a silicon oxide film onto a plurality of conductive films under vacuum using a film having the silicon oxide film formed thereon and then by separating the base film from the silicon oxide film. During the separation, the base film, being composed of a fluorine-containing resin, has smaller surface energy than a silicon oxide film and thus is easy to separate, leaving the silicon oxide film on the conductive films. As a result, the silicon oxide film is adhered on the conductive films so as to cover the conductive films, and an air gap is hence provided between the conductive films. Thus, a highly reliable semiconductor device capable of high-speed-operation is provided by controlling parasitic capacitances between interconnections arranged accurately and adequately adjacent to each other so that recent needs for further miniaturization and higher integration of semiconductor elements can be met.

Abstract: A method of reworking a bump is provided. Failed bumps are chemically etched off the wafer. During etching, the etchant somewhat damages the passivation layer on the wafer. Therefore, a global metal layer is needed to cover the bonding pads and the passivation layer before a new under ball metallurgy (UBM) layer is formed. A complementary passivation layer is formed to cover the damaged passivation layer after the failed bumps are removed. Then, a new UBM layer and new bumps are formed. Alternatively, the failed bumps and UBM layer are chemically etched off without formation of a metal layer. Instead, a complementary passivation layer is formed to cover the damaged passivation layer. Finally, a new UBM layer and new bumps are formed. By chemical etching, the failed bumps can be reworked and the yield of the bump production can be increased.

Abstract: A method of fabricating an integrated circuit having active components, conductors and isolation regions on a substrate is disclosed, including patterning and etching a portion of at least one of said isolation regions to expose a first area of said substrate, depositing a mask layer over said integrated circuit including said first area, patterning an a itching said mask layer to expose a second area of said substrate within said first area, converting a portion of said substrate to a selectively etchable material, wherein said selectively etchable material lies in an area subjacent to said second area and extends only partially to the bottom surface of said substrate, selectively etching said selectively etchable material to form a void, removing said mask layer to expose said isolation region, depositing a dielectric layer over said void wherein said dielectric layer extends at least to the height of said isolation region and covers the top surface of said wafer, polishing the surface of said dielectric la

Abstract: One embodiment of the invention is directed to a method of forming a metallization level of an integrated circuit including the steps of forming metal areas of a metallization level laterally separated by a first insulating layer, removing the first insulating layer, non-conformally depositing a second insulating layer so that gaps can form between neighboring metal areas, or to obtain a porous layer. The removal of the first insulating layer is performed through a mask, to leave in place guard areas of the first insulating layer around the portions of the metal areas intended for being contacted by a via crossing the second insulating layer.

Abstract: The invention relates to a method of producing calibration structures in semiconductor substrates in the manufacture of components, specifically micro-mechanical systems with integrated semiconductor electronic systems. In the method a first layer (3) is structured on a first substrate (4, 5, 6) to produce first areas (2) which are required for the function of the components. Moreover, second areas (1) are produced in the first layer (3), which represent the calibration structures. The second areas (1) present a refractive index different from the refractive index of adjoining areas. Subsequently, the first substrate (4, 5, 6) is joined with a second substrate (12) such that the first layer (3) will be enclosed between the two substrates. Then either the first or the second substrate is thinned down to a residual thickness. The substrate layer with this residual thickness constitutes, for instance, the membrane in a pressure sensor.

Abstract: A local oxidation of silicon (LOCOS) process directed to forming differential field oxide thickness on a single wafer with minimized process steps and optimized planarity. When patterning the masking layer, at least two window widths are formed in the masking layer, exposing the underlying substrate and pad oxide. When one of the window widths is sufficiently small, oxidation of the substrate will be inhibited causing reduced growth and thus a reduced field oxide thickness in that window as compared to other larger windows formed in the same masking layer, creating differential field oxide thicknesses in one growth step. To optimize planarity, prior to oxidation variable depth trenches are formed in alignment with the windows so that the resulting field oxide regions are substantially planar with the substantial surface.

Abstract: Air gap insulation regions are formed selectively within high parasitic capacitance regions in which conductive lines are closely proximate and generates an intolerable amount of parasitic capacitance. The selective formation of air gap insulation regions improves circuit performance by reducing the parasitic capacitance and device reliability by reducing the stress fracture problem of conventional air gap insulation schemes.

Abstract: A cavity structure formed in a semiconductor substrate and under a device formation region on which a device if formed. The cavity structure has supporting pillars providing the device formation region with mechanical strength.

Abstract: Trench isolation structure includes a first conformal insulating film (preferably consisting of silicon nitride) which lines a trench etched in a silicon substrate, an insulating layer (preferably consisting of silicon dioxide) which caps the lined trench and thereby forms a cavity, and a gas (preferably consisting of carbon dioxide) within the cavity. Fabrication of the trench isolation structure is begun by depositing a first conformal insulating film onto the surface of a trench etched in a silicon substrate, thereby forming a lined trench. An amorphous carbon layer is deposited within the lined trench and the lined trench is capped by an insulating layer which encloses the amorphous carbon within a cavity. The solid amorphous carbon within the cavity is converted to carbon dioxide gas by annealing the substrate in an oxidizing ambient. Planarizing the insulating layer to the level of the substrate completes fabrication of the trench isolation structure.

Abstract: A dielectric material is provided having air gaps purposely formed within the dielectric. The dielectric is deposited, and air gaps formed, between respective interconnect lines. The geometries between interconnect lines is purposely controlled to achieve a large aspect ratio necessary to produce air gaps during CVD of the dielectric. Air gaps exist between interconnects to reduce the line-to-line capacitance, and thereby reduce the propagation delay associated with closely spaced interconnects.

Abstract: A silicon on insulator (SOI) field effect transistor (FET) structure is formed on a conventional bulk silicon wafer. The structure includes an electrical coupling between the channel region of the FET with the bulk silicon substrate to eliminate the floating body effect caused by charge accumulation in the channel regions due to historical operation of the FET. The method of forming the structure includes isolating the FET active region from other structures in the silicon substrate by forming an insulating trench about the perimeter of the FET and forming an undercut beneath the active region to reduce or eliminate junction capacitance between the source and drain regions and the silicon substrate.

Abstract: A semiconductor structure which includes a raised source and a raised drain. The structure also includes a gate located between the source and drains. The gate defines a first gap between the gate and the source and a second gap between the gate and the drain.

Abstract: A semiconductor device has an air-gap/multi-level interconnection structure. The interconnects are insulated from one another by an air gap in the same layer, and by an interlevel dielectric film between layers and from a semiconductor substrate. A high-speed semiconductor device is obtained due to a lower parasitic capacitance.

Abstract: Insulating layers between transistors that are very close together may have voids. When contacts are formed in these areas between these close transistors, the contact hole is formed at the void location. These voids may extend between the contact locations that are close together so that the deposition of the conductive material into these contact holes may extend sufficiently into the void to short two such contacts. This is prevented by placing a liner in the contact hole, which constricts the void size in the contact hole, prior to depositing the conductive material. This restricts ingress of conductive material into the void. This prevents the void from being an unwanted conduction path between two contacts that are in close proximity. The bottoms of the contact holes are etched to remove the liner prior to depositing the conductive material.

Abstract: Disclosed is a method for forming a semiconductor device; and, more particularly, to a method for forming a semiconductor device with low parasite capacitance by using an air gap and a self-aligned contact plug formed by a selective epitaxial growing method. A method for forming a semiconductor according to the present invention comprises the steps of: forming word lines over a semiconductor substrate, wherein a plurality of contact areas are formed between the word lines; forming epitaxial layers for contact plugs on the contact areas, thereby forming a resulting structure; forming air gaps on non-contact areas on which the epitaxial layers is not formed, by depositing an interlayer insulation layer on the resulting structure; and patterning the interlayer insulation layer so as to expose the epitaxial layers. Accordingly, the present invention using the air gap as a gap filling materials reduces the parasite capacitance loaded on a bit line and omits an additional gap filling process.

Abstract: A silicon on insulator (SOI) field effect transistor (FET) structure is formed on a conventional bulk silicon wafer. The structure includes an electrical coupling between the channel region of the FET with the bulk silicon substrate to eliminate the floating body effect caused by charge accumulation in the channel regions due to historical operation of the FET. The method of forming the structure includes isolating the FET active region from other structures in the silicon substrate by forming an insulating trench about the perimeter of the FET and forming an undercut beneath the active region to reduce or eliminate junction capacitance between the source and drain regions and the silicon substrate.

Abstract: A method for forming a micro cavity is disclosed. In the method for forming the cavity, a first layer is formed on a silicon layer and a trench is formed in the silicon layer by selectively etching the silicon layer. A second and a third layers are formed on the trench and on the silicon layer. Etching holes are formed through the third layer by partially etching the third layer. A cavity is formed between the silicon layer and the third layer after the second layer is removed through the etching holes. Therefore, the cavity having a large size can be easily formed and sealed in the silicon layer by utilizing the volume expansion of the silicon or the poly silicon layer. Also, a vacuum micro cavity can be formed according as a low vacuum CVD oxide layer or a nitride layer formed on the etching holes which are partially opened after the thermal oxidation process by controlling the size of the etching holes concerning the other portion of the poly silicon layer.

Abstract: A process for forming air gaps within an interlayer dielectric is provided to reduce loading capacitance between interconnections. A first dielectric layer is deposited on the spaced interconnections. This first dielectric layer is deposited more thickly at the top sides than at the bottom sides of the interconnections. A second dielectric layer is deposited on the first dielectric layer to a controlled thickness that causes formation of air gaps therewithin between the interconnections. The poor step coverage of the first dielectric layer makes it easier to form the air gaps. Air gaps between interconnections allows reduced permittivity of the overall dielectric structures and thereby reduces the interconnect line to line capacitance, and increases the possible operation speed of the semiconductor device.

Abstract: To manufacture integrated semiconductor devices comprising chemoresistive gas microsensors, a semiconductor material body is first formed, on the semiconductor material body are successively formed, reciprocally superimposed, a sacrificial region of metallic material, formed at the same time and on the same level as metallic connection regions for the sensor, a heater element, electrically and physically separated from the sacrificial region and a gas sensitive element, electrically and physically separated from the heater element; openings are formed laterally with respect to the heater element and to the gas sensitive element, which extend as far as the sacrificial region and through which the sacrificial region is removed at the end of the manufacturing process.

Abstract: An air gap semiconductor structure and corresponding method of manufacture. The method includes providing a substrate having metallic lines thereon. A high molecular weight sacrificial film is formed over the substrate. A portion of the high molecular weight sacrificial layer is removed to form spacers. A dielectric layer is formed over the substrate, the top surface of the metallic lines and the spacers. Finally, a thermal dissociation operation is conducted to remove the spacers, thereby forming an air pocket on each sidewall of the metallic lines.

Abstract: The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components.

Abstract: A void is defined between adjacent wiring lines to minimize RC coupling. The void has a low dielectric value approaching 1.0. For one approach, hollow silicon define the void. The spheres are fabricated to a known inner diameter, wall thickness and outer diameter. The spheres are ridgid enough to withstand the mechanical processes occurring during semiconductor fabrication. The spheres withstand elevated temperature up to a prescribed temperature range. At or above a desired temperature, the sphere walls disintegrate leaving the void in place. For an alternative approach, adjacent wiring lines are “T-topped” (i.e., viewed cross-sectionally). Dielectric fill deposited in the spacing between lines. As the dielectric material accumulates on the line and substrate walls, the T-tops grow toward each other. Eventually, the T-tops meet sealing off and internal void.

Abstract: A microelectronic substrate and method for manufacture. In one embodiment, the microelectronic substrate includes a body having a first surface, a second surface facing a direction opposite from the first surface, and a plurality of voids in the body between the first and second surfaces. The voids can extend from the first surface to a separation region beneath the first surface. At least one operable microelectronic device is formed at and/or proximate to the first surface of the substrate material, and then a first stratum of the microelectronic substrate above the separation region is separated from a second stratum of the microelectronic substrate below the separation region. The first stratum of the microelectronic substrate can be further separated into discrete microelectronic dies before the first stratum is separated from the second stratum. In one aspect of this embodiment, the substrate can support a film and microelectronic devices can be formed in the film and/or in the substrate.

Abstract: A reduced capacitance interconnect system. A first metal layer is formed to a predetermined level above a first dielectric layer which is formed on a semiconductor substrate. The first metal layer level forms multiple interconnect lines wherein each interconnect line is separated from each adjacent interconnect line by a trench including a trench having a highest aspect ratio. A second dielectric layer is formed on the first metal layer and in the trenches between the interconnect lines such that an enclosed void having a void tip substantially level with the top of the metal layer is formed in at least each trench having an aspect ratio above a predetermined minimum aspect ratio, wherein the enclosed void in the trench having the highest aspect ratio has a void volume which is at least 15% of the volume of the trench.

Abstract: A method of manufacturing a semiconductor device having a wiring layer with an air bridge construction includes the steps of forming a lower layer metal interconnect, depositing an interlayer insulation film, depositing a first and a second insulation film, patterning the second insulation film and of etching the first insulation film and the interlayer insulation film using the second insulation film as a mask so as to form a post opening part and a via hole to connect an upper layer metal interconnect with the lower layer metal interconnect, depositing a third insulation film over the entire surface, etching back so as to leave the third insulation film in a side wall of the post opening part and fill the via hole with the third insulation film, depositing a fourth insulation film over the entire surface of the structure, then removing the fourth insulation film until the via hole is exposed, and then removing the third insulation film inside the via hole, filling the via hole with a metal, and then flatten

Abstract: Air-bridges are formed at controlled lateral separations using the extremely high HF etch rate of a gap-fill spin-on-glass such as uncured hydrogen silsequioxane (HSQ) in combination with other dielectrics having a much slower etch rate in HF. The advantages of an air-bridge system with controlled lateral separations include providing an interconnect isolation dielectric which meets all requirements for sub-0.5 micron technologies and providing a device with reduced reliability problems.

Abstract: A method of fabricating a microstructure having an inside cavity. The method includes depositing a first layer or a first stack of layers in a substantially closed geometric configuration on a first substrate. Then, performing an indent on the first layer or on the top layer of said first stack of layers. Then, depositing a second layer or a second stack of layers substantially with said substantially closed geometric configuration on a second substrate. Then, aligning and bonding said first substrate on said second substrate such that a microstructure having a cavity is formed according to said closed geometry configuration.

Abstract: A semiconductor structure with a dielectric layer and its producing method are disclosed. The semiconductor structure includes a semiconductor substrate having thereon a plurality of metal lines and there are a plurality of concave regions formed between the metal lines. The dielectric layer is formed on the semiconductor by a method which can prevent the dielectric material from flowing into the concave regions. The method includes the steps of (a) providing a semiconductor substrate having thereon a plurality of metal lines forming therebetween a plurality of concave regions; and (b) forming the dielectric layer on the metal lines. The concave regions are only filled with air so that the capacitance of the semiconductor is lowered.

Abstract: In accordance with the present invention, a method for expanding trenches includes the steps of forming a trench in a substrate, preparing surfaces within the trench by etching the surfaces with a wet etchant to provide a hydrogen terminated silicon surface and anisotropically wet etching the trench to expand the trench.

Abstract: A multilevel interconnect structure with a low-k dielectric constant is fabricated in an integrated circuit structure by the steps of depositing a layer of photoresist on a substrate assembly, etching the photoresist to form openings, forming a metal layer on the photoresist layer to fill the openings and then removing the photoresist layer by, for example, ashing. The metal layer is supported by the metal which filled the openings formed in the photoresist.

Abstract: A fabrication method for an air-gap, in which method hard mask is used, is described. A patterned hard mask layer is formed on a semiconductor substrate. Taking advantage of the etching selectivity of the hard mask layer to the dielectric layer, an opening with a high aspect ratio is formed in the dielectric layer. A conductive plug is then formed in the opening, followed by forming a conductive layer on the hard mask layer to cover the conductive plug. The hard mask layer is further removed. A silicon oxide layer with poor step coverage is formed to cover the substrate. Using the space remaining after the removal of the hard mask layer, an air-gap is formed between the conductive layer and the dielectric layer to enhance the insulation effect.

Abstract: An isolation structure and a method of making the same are provided. In one aspect, the method includes the steps of forming a trench in a substrate and forming a first insulating sidewall in the trench and a second insulating in the trench in spaced-apart relation to the first insulating sidewall. A bridge layer is formed between the first and the second sidewalls. The bridge layer, the first and second sidewalls, and the substrate define an air gap in the trench. The isolation structure exhibits a low capacitance in a narrow structure. Scaling is enhanced and the potential for parasitic leakage current due to non-planarity is reduced.

Abstract: A process for manufacturing a semiconductor circuit. The process comprises creating a plurality of adjacent conductive lines having a solid fill between the conductive lines; creating one or more layers above the lines and the fill; creating one or more pathways to the fill through the layers; and converting the fill to a gas that escapes through the pathways, leaving an air void between adjacent lines. To protect the lines from oxidation during processing, a related process for encapsulating conductive lines in one or more adhesion-promotion barrier layers may be performed. The encapsulation process may also be practiced in conjunction with other semiconductor manufacturing processes. The processes result in a multi-layer semiconductor circuit comprising conductive lines, wherein the lines have air as a dielectric between them, are encapsulated by an adhesion-promotion barrier layer, or both.

Abstract: Disclosed is a method for making an air bridge in an electronic device. This method uses amorphous silicon carbide to protect electrical conductors in the device during formation of the bridge. The silicon carbide also provides hermetic and physical protection to the device after formation.

Abstract: A method for introducing air into the gaps between neighboring conducting structures in a microelectronics fabrication in order to reduce the capacitative coupling between them. A patterned metal layer is deposited on a substrate. The layer is lined with a CVD-oxide. A disposable gap-filling material is deposited over the lined metal layer. A two layer “air-bridge” is formed over the gap-fill by depositing a layer of TiN over a layer of CVD-oxide. This structure is rendered porous by several chemical processes. An oxygen plasma is passed through the porous air-bridge to react with and dissolve the gap-fill beneath it. The reaction products escape through the porous air-bridge resulting in air-filled gaps.

Abstract: A low dielectric constant material and a process for controllably reducing the dielectric constant of a layer of such material is provided and comprises the step of exposing the layer of dielectric material to a concentration of an oxygen plasma at a temperature and a pressure sufficient for the oxygen plasma to etch the layer of dielectric material to form voids in the layer of dielectric material. The process may also include the step of controlling the reduction of the dielectric constant by controlling the size and density of the voids. The size and density of the voids can be controlled by varying the pressure under which the reaction takes place, by varying the temperature at which the reaction takes place, by varying the concentration of the oxygen plasma used in the reaction or by varying a combination of these parameters. The process of the present invention is particularly useful in the fabrication of semiconductor devices.

Abstract: Multi-level semiconductor devices are formed with reduced parasitic capacitance without sacrificing structural integrity or electromigration performance by removing the inter-layer dielectrics and supporting the interconnection system with a metal silicide lining. Embodiments include depositing a dielectric sealing layer, e.g., silicon nitride, before forming the first metallization level, removing the inter-layer dielectrics after forming the last metallization level, electroplating or electroless plating a metal, such as cobalt or nickel, to line the interconnection system, depositing a thin layer of polycrystalline silicon on the metal, heating to form the metal silicide lining on the interconnection system, and forming dielectric protective layers, e.g. a silane derived oxide bottommost protective layer, on the uppermost metallization level.

Abstract: A method to lower the parasitic capacitance is described, in which a low dielectric constant air-gap is formed in the dielectric layers at both sides of the gate to lower the parasitic capacitance present between the gate and the source/drain region. The air-gap is formed by forming spacers at both sides of the gate, followed by forming a first dielectric layer with its height lower than the top of the spacers. Thereafter, the spacers are removed by wet etching to form a hole with its top narrower than its bottom. A second dielectric layer is further formed, by a deposition technique with a weaker step coverage capability, to encapsulate the hole and to cover the substrate, wherein the encapsulated hole is the air-gap.

Abstract: A method for fabricating an inter-metal dielectric layer. Several conducting wires are formed on a substrate, and openings lie between the adjacent conducting wires. A first dielectric layer fills the openings, and the surface of the first dielectric layer is lower than that of the conducting wires. A spacer is formed on a sidewall of each of the conducting wires. The first dielectric layer is removed to expose the bottom of the spacer. A second dielectric layer is formed to cover the conducting wires.

Abstract: A method of manufacturing an inter-metal dielectric layer. A substrate having a plurality of wires formed thereon is provided. A portion of the substrate is exposed to form an opening between the wires. The opening is filled with a flowable dielectric material, wherein a surface level of the flowable dielectric material is lower than that of the wires. A plurality of spacers is formed on the sidewall of the wires exposed by the flowable dielectric material. The flowable dielectric material is removed. An anisotropic deposition process with a poor-lateral-filling ability is performed to form a dielectric layer with a void under the spacer over the substrate.

Abstract: A semiconductor device or other suitable substrate and method with single or multi layers of buried micro pipes are disclosed. This is achieved by controlling the aspect ratio of trenches as well as controlling the deposition characteristics of the material used to fill the trenches. A buried micro pipe is formed by filling a trench that has a height which is larger than a width thereof, so that the trench filler material lines sidewalls and bottom of the trench, and covers the top of the trench to form the micro pipe within the trench. Another layer can be formed over the filler material and planarized. Alternatively, the filler material itself can be planarized. Forming trenches in the planarized layer, and repeating the above steps forms a second set of buried micro pipes in these new trenches. This forms a semiconductor device having multiple layer of buried micro pipes.

Abstract: A method of fabricating a plug etches back the first plug material layer to form a dished surface on the first plug material layer and then performs a second coverage step. A second plug material layer is formed to fill the dished surface and a hole. Thus, the slurry cannot fill the hole during chemical mechanical polishing nor can slurry react with the plug material or the first metallic layer. The reliability of the plug according to the present invention is increased. The thickness of the second plug material layer is thinner than the plug material layer of the conventional method. The thickness is decreased by about 60% when compared with the conventional method, which decreases fabrication costs.

Abstract: Air-gap technology is introduced in the damascene scheme, reducing the capacitance between interconnect metal lines on an integrated circuit substrate, and ultimately enhancing the speed of the device. Reduction of extraneous signal energy (cross-talk) from traversing from one metal line to another is also realized. The method for implementing an air-gap filled dielectric between the interconnect metal lines involves depositing a first dielectric layer on the substrate at a predetermined height. Next the first dielectric is patterned and etched to form lines. A second dielectric layer is then deposited using air-gap technology, such that the second dielectric contains air-gaps between the first dielectric lines. These air-gaps are situated below the predetermined height of the first dielectric. The substrate is then polished so that the top surface of the first dielectric is exposed. The first dielectric lines are then etched and removed.

Abstract: A process for forming controlled airgaps (22) between metal lines (16). A two-step high density plasma (HDP) chemical vapor deposition (CVD) process is used to form the silicon dioxide dielectric layer (20) with the controlled airgaps (22). The first step involves a high gas flow and low substrate bias conditions to deposit silicon dioxide with a high deposition to sputter etch ratio. The second step uses a low gas flow and high substrate bias condition to increase the sputter component of the deposition.