Abstract: A fabrication method for a dual damascene structure comprising an air-gap is provided. The method includes forming sequentially a first dielectric layer, a stop layer and a second dielectric layer on a substrate comprising a first metal layer. The first and the second dielectric layers are then defined to form a via. opening exposing the first metal layer and an opening in a predetermined position on the first and second dielectric layers. An oxide layer is then formed on the second dielectric layer covering the opening and forming a gap. The oxide layer and the second dielectric layer are then defined to form a trench, which exposes the first metal layer. A second metal layer and a via plug are then formed in the trench and the via. opening, wherein the second metal layer and the first metal layer are electrically connected through the via plug.

Abstract: An integrated circuit structure comprises a conductor film that serves as a passive element or an interconnection, and a silicon substrate. A cavity is disposed between the substrate and the conductor film and thus underneath the conductor film. The substrate is formed by forming an island of oxide film in a surface of the substrate, and then wet etching the island from the surface of the substrate thereby forming the cavity.

Abstract: A method for creating low intra-level dielectric interface between conducting lines using conventional deposition and etching processes. A layer of conducting lines is formed interspersed with dielectric material. A dummy, high-density pattern of low k dielectric material is created on top of this layer. The dielectric material between the metal lines is removed. The dummy high-density pattern is interconnected, deposited on top of this interconnected layer is a low k dielectric to form an inter layer dielectric.

Abstract: A method for forming a semiconductor device having air regions, the method comprises providing a base, forming a pattern of metal leads, depositing a layer of oxide over the metal leads, forming a layer of nitride over said layer of oxide, opening and etching a trench down to the base layer of material, and depositing and planarizing a dielectric layer. An alternate approach teaches the deposition of a layer of SOG over the layer of oxide that has been deposited over the metal leads, planarizing this layer of SOG down to the top of the metal leads, depositing a layer of PECVD oxide, patterning and etching this layer of PECVD oxide thereby creating openings that are in between the metal leads. The SOG that is between the metal leads can be removed thereby creating air gaps as the intra-level dielectric for the metal leads.

Abstract: Trench isolation structure includes a first conformal insulating film (preferably consisting of silicon nitride) which lines a trench etched in a silicon substrate, an insulating layer (preferably consisting of silicon dioxide) which caps the lines trench and thereby forms a cavity, and a gas (preferably consisting of carbon dioxide) within the cavity. Fabrication of the trench isolation structure is begun by depositing a first conformal insulating film onto the surface of a trench etched in a silicon substrate, thereby forming a lined trench. An amorphous carbon layer is deposited within the lined trench and the lined trench is capped by an insulating layer which encloses the amorphous carbon within a cavity. The solid amorphous carbon within the cavity is converted to carbon dioxide gas by annealing the substrate in an oxidizing ambient. Planarizing the insulating layer to the level of the substrate completes fabrication of the trench isolation structure.

Abstract: A method of manufacturing a semiconductor device includes the step of forming a gate electrode on a semiconductor substrate via a gate insulating film and the step of forming a first insulating film on side surfaces of the gate electrode and an upper surface of the semiconductor substrate. Also the method includes the step of forming a second insulating film on the first insulating film and the step of etching back the first and second insulating films to form side walls of the gate electrode each of which includes layers of the first and second insulating films. The method includes the step of etching the first insulating films of the side walls to remain a part of the first insulating film layers.

Abstract: The invention proposes methods for producing integrated circuits wherein the dielectric constant between closely spaced and adjacent metal lines is approaching 1. One method of the invention uses low-melting-point dielectric to form a barrier forming a void between conductive lines. Another method of the invention uses sidewall film to form a similar barrier.

Abstract: A method for fabricating a multilevel interconnect, where a first and a second conducting wires are formed respectively on a substrate, while a part of the substrate between the first and the second conducting wires is exposed. A first dielectric layer is then formed to cover the substrate as well as the first and the second conducting wires, wherein the first dielectric layer has an air gap formed between the first and the second conducting wires. An anti-etch layer is formed on the first dielectric layer above the air gap, while a second dielectric layer is then formed on the anti-etch layer and the first dielectric layer. A via opening which exposes the first conducting wire is then formed by etching, followed by forming a barrier layer which covers the profile of the via opening and the exposed surface of the first conducting layer. Consequently, a via plug is formed to fill the via opening.

Abstract: Multi-level semiconductor devices are formed with reduced parasitic capacitance without sacrificing structural integrity or electromigation performance by removing the inter-layer dielectrics and supporting the interconnection system with a rigid lining. Embodiments include depositing a dielectric sealing layer, e.g., silicon oxide, silicon nitride or composite of silicon oxide/silicon nitride, before forming the first metallization level, removing the inter-layer dielectrics after forming the last metallization level, lining the interconnection system with undoped polycrystalline silicon and forming a dielectric protective layer, e.g. a silane derived oxide, on the uppermost metallization level.

Abstract: The process of the present invention can be used for conventional processing or for the Damascene process. The key concept of the present invention is a functional "filler" material which can later be removed (decomposed) to leave an air gap between the conducting lines. The filler material can be deposited as a step during conventional metal etch processing or it can be deposited as a first step of the processing of a semiconductor wafer. Leakage currents can be reduced as part of the present invention by applying passivation layers.

Abstract: An air bridge between closely spaced interconnect lines is formed by a high density plasma chemical vapor deposition of fluorinated amorphous carbon. In one particular embodiment of the present invention, to create the air bridge, high density plasma chemical vapor deposition of fluorocarbon and hydrocarbon precursors, with little or no rf bias applied to the substrate is performed. For mechanical support of subsequently formed layers, the air bridge is capped by a hard mask layer, typically formed from an insulating material such as silicon dioxide, fluorinated silicon dioxide, or silicon nitride.

Abstract: The present invention is a semiconductor device having a plurality of wiring on a semiconductor substrate. It is provided with a first insulating film which covers the surface of all the aforesaid wiring, and a second insulating film containing air gaps which is formed between such of the aforesaid wiring as is mutually adjacent.The method of manufacturing the semiconductor device to which the present invention pertains comprises a process whereby the first insulating film is formed in such a manner as to cover the surface of the plurality of wiring formed on the semiconductor substrate, and a process whereby the second insulating film containing air gaps is formed between such of the wiring on the aforesaid substrate as is mutually adjacent. Here, the first insulating film is formed by means of the plasma CVD or spin coating methods, the second by means of the plasma CVD, spin coating, bias CVD, sputtering or similar methods.

Abstract: A semiconductor structure having a first conductive trace fabricated adjacent to a second conductive trace over an insulating layer. A dielectric material is located over and between the first and second conductive traces. A borderless contact extends through the dielectric material to contact the first conductive trace. An air gap is formed in the dielectric material between the first and second conductive traces, thereby increasing the capacitance between the first and second traces. The air gap has a first portion with a first width adjacent to the borderless contact, and a second portion with a second width away from the borderless contact. The second width is greater than the first width, and the second portion of the air gap is substantially longer than the first portion of the air gap. The first portion of the air gap is offset toward the second trace.

Abstract: A signal isolation and decoupling structure fabricated in an integrated circuit device for providing signal isolation and decoupling for signal carrying conductors of the integrated circuit device, wherein one of the conductors is embedded in dielectric material and enclosed within an isolation structure of an electrically conductive material which is formed in the integrated circuit device and extends substantially the length of the conductor, the isolation structure including top and bottom walls of electrically conductive material and first and side walls, also of an electrically conductive material, which electrically interconnect the top and bottom walls, forming an enclosure around the conductor. Also described is a method for fabricating the isolation structure in the integrated circuit device.

Abstract: A method for forming a dielectric layer within a microelectronics fabrication. There is first provided a substrate layer formed upon a substrate employed within a microelectronics fabrication. There is then formed upon the substrate layer a pair of patterned titanium nitride conductor layers upon which is formed a pair of aluminum containing conductor layers to provide a pair of patterned conductor stack layers. There is then formed over the patterned conductor stack layers a silicon oxide dielectric layer formed employing an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method employing tetra-ethyl-ortho-silicate (TEOS) as the silicon source material, where the silicon oxide dielectric layer defines at least in part a series of voids formed interposed between the patterned conductor stack layers.

Abstract: Chips having subsurface structures within or adjacent a horizontal trench in bulk single crystal semiconductor are presented. Structures include three terminal devices, such as FETs and bipolar transistors, rectifying contacts, such as pn diodes and Schottky diodes, capacitors, and contacts to and connectors between devices. FETs have low resistance connectors to diffusions while retaining low overlap capacitance. A low resistance and low capacitance contact to subsurface electrodes is achieved by using highly conductive subsurface connectors which may be isolated by low dielectric insulator. Stacks of devices are formed simultaneously within bulk single crystal semiconductor. A subsurface CMOS invertor is described. A process for forming a horizontal trench exclusively in heavily doped p+ regions is presented in which porous silicon is first formed in the p+ regions and then the porous silicon is etched.

Abstract: A MOSFET structure in which the channel region is contiguous with the semiconductor substrate while the source and drain junctions are substantially isolated from the substrate, includes a dielectric volume formed adjacent and subjacent to portions of the source and drain regions.In a further aspect of the invention, a process for forming an isolated junction in a bulk semiconductor includes forming a dielectric volume adjacent and subjacent to portions of the source and drain regions.

Abstract: A method of fabricating an air-gap spacer of a metal-oxide-semiconductor device includes the following steps. First, a substrate having a gate oxide layer and a polysilicon layer successively formed is provided. The polysilicon layer and the gate oxide layer are patterned to form a gate electrode region. A silicon nitride layer and an oxide layer are successively formed on the surface of the substrate and the surface of the gate electrode region. The oxide layer and the silicon nitride layer are anisotropically etched to form a cross-sectional L-shaped silicon nitride layer and a first spacer at the sidewall of the gate electrode region. After the first spacer is removed, an ion implantation is performed to form an extended lightly doped region below the L-shaped silicon nitride layer in the substrate and a lightly doped region in the substrate surrounding the extended lightly doped region.

Abstract: In a semiconductor device, a gate electrode is formed by sequentially forming a Schottky metal film, a barrier metal film, and a low-resistance metal film from the lower side. The Schottky metal film or barrier metal film has a gap in a lower gate vertical portion. The gap is closed at its upper and lower portions. The overlaying low-resistance metal film does not extend into the lower gate vertical portion. A method for this semiconductor device is also disclosed.

Abstract: An isolation method for a highly-integrated semiconductor device includes growing an epitaxial layer on the entire surface of a semiconductor substrate including over a trench on which an oxide layer is formed, thereby leaving the inside of the trench empty. A portion of the epitaxial layer which is located over the trench is then oxidized to form an isolation region.

Abstract: An epitaxial pinched resistor includes a semiconductor substrate of a first conductivity type having a surface on which an epitaxial layer of a second conductivity type grown. An up isolation region of the first conductivity type is diffused from the surface of the semiconductor substrate up into the epitaxial layer. A first down isolation region of the first conductivity type is diffused down into the epitaxial layer and overlapping with the up isolation region. The first down isolation region and the up isolation region isolate a portion of the epitaxial layer to be used to conduct a current. A second down isolation region of the first conductivity type is diffused down into the epitaxial layer between first and second contact surface areas of the epitaxial layer and into the portion of the epitaxial layer used to conduct the current.

Abstract: An identification document and a method of placing personalized data (variable text and color image) directly on the identification document having a data receiving page. The method comprises the steps of: printing personalized data directly onto a silicone release coat of a release sheet; positioning the release sheet with the side containing fused toner adjacent to the adhesive of an adhesive side of a security laminate; passing the release sheet and the security laminate through a laminator to transfer the personalized data to the adhesive of the security laminate; removing the release sheet leaving the personalized data on the security laminate; and passing the security laminate and the data receiving page through a laminator to seal personalized data between the security laminate and the data receiving page.

Abstract: A MOS transistor includes a void space as part of the gate oxide layer on the drain end of the transistor. The void space replaces a region of the gate oxide layer so that no oxide is present for injection of hot carriers. The presence of the void space, preferably containing a vacuum, also reduces the total gate capacitance of the device. The void space is formed by chemical etching of the gate oxide layer and void space sealing during device manufacture.

Abstract: A dielectric material is provided having air gaps which form during dielectric deposition between interconnects. The dielectric is deposited in interconnect-spaced geometries which have certain aspect ratios and which are exposed at the bottom of the geometries to a hygroscopic dielectric. During deposition, the dielectric is forced along the sidewall of the spaced interconnects as a result of moisture ougasing from the hygroscopic dielectric. Over a period of time, a keyhole occurs with pile up accumulation (or cusping) at the corners of the spaced interconnects. By decreasing the deposition temperature in a subsequent step, outgasing is minimized, and deposition over the keyhole and upon the hygroscopic dielectric takes place. Keyhole coverage results in an air gap which is surrounded on all sides by the fill dielectric. Air gap between interconnects helps reduce permittivity of the overall dielectric structure, resulting in a lessening of the interconnect line-to-line capacitance.

Abstract: An improved structure and a process for forming an interlevel dielectric layer having a low capacitance between closely spaced metallurgy lines is provided. The method begins with a substrate surface having closely spaced metallurgy lines. A silicon oxide dielectric layer having a closed void between adjacent metallurgy lines is formed using electro cyclotron resonance techniques. The voids in the silicon dioxide dielectric layer are formed by controlling the ECR process parameters to achieve a proper etch to deposition ratio. The etch to deposition ratio of the silicon oxide layer is adjusted to the particular height and spacing between the metallurgy lines. Next, a spin-on-glass layer is formed over the silicon oxide dielectric layer. Portions of the SOG layer are etched back or chemically mechanically polished. The void (air) has a lower capacitance than the ECR silicon oxide layer.

Abstract: A new method of trench isolation incorporating thermal stress releasing voids is described. Two sets of narrow trenches are etched into the silicon substrate not covered by a photoresist mask wherein the second set of trenches alternate with the first set of trenches. The first set of trenches is filled with an insulating layer. A second insulating layer is deposited over the surface of the substrate and within the second set of trenches wherein said insulating layer has step coverage such that voids are formed and are completely enclosed within the second set of trenches completing the thermal stress releasing device isolation of the integrated circuit. The method of forming thermal stress released polysilicon gate spacers in an integrated circuit is described. Polysilicon gate electrodes are formed on the surface of the semiconductor substrate. Sucessive sidewalls are formed on the gate electrodes of thin silicon dioxide, silicon nitride, and silicon dioxide.

Abstract: A new method of trench isolation incorporating thermal stress releasing voids is described. Two sets of narrow trenches are etched into the silicon substrate not covered by a photoresist mask wherein the second set of trenches alternate with the first set of trenches. The first set of trenches is filled with an insulating layer. A second insulating layer is deposited over the surface of the substrate and within the second set of trenches wherein said insulating layer has step coverage such that voids are formed and are completely enclosed within the second set of trenches completing the thermal stress releasing device isolation of the integrated circuit. The method of forming thermal stress released polysilicon gate spacers in an integrated circuit is described. Polysilicon gate electrodes are formed on the surface of the semiconductor substrate. Sucessive sidewalls are formed on the gate electrodes of thin silicon dioxide, silicon nitride, and silicon dioxide.