Abstract: Provided is a method of implanting dopant ions to an integrated circuit. The method includes forming a first pixel and a second pixel in a substrate, forming an etch stop layer over the substrate, forming a hard mask layer over the etch stop layer, patterning the hard mask layer to include an opening between the first pixel and the second pixel, and implanting a plurality of dopants through the opening to form an isolation feature.

Abstract: A method of fabricating a semiconductor structure. The method includes forming a first feature of a first active device and a second feature of a second active device, introducing a first amount of nitrogen into the first feature of the first active device, and introducing a second amount of nitrogen into the second feature of the second active device, the second amount of nitrogen being different from the first amount of nitrogen.

Abstract: In a GaAs substrate as a semi-insulating substrate, a heterojunction bipolar transistor (HBT) is formed in an element formation region, while an isolation region is formed in an insulating region. The isolation region formed in the insulating region is formed by introducing helium into the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT. In an outer peripheral region, a conductive layer is formed to be exposed from protective films and coupled to a back surface electrode. Because a GND potential is supplied to the back surface electrode, the conductive layer is fixed to the GND potential. The conductive layer is formed of the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT.

Abstract: A method and structure for reducing dark current in an image sensor includes preventing unwanted electrons from being collected in the photosensitive region of the image sensor. In one embodiment, dark current is reduced by providing a deep n-type region having an n-type peripheral sidewall formed in a p-type substrate region underlying a pixel array region to separate the pixel array region from a peripheral circuitry region of the image sensor. The method and structure also provide improved protection from blooming.

Abstract: An integrated circuit includes a bipolar transistor comprising a substrate and a collector formed in the substrate. The collector includes a highly doped lateral zone, a very lightly doped central zone and a lightly doped intermediate zone located between the central zone and the lateral zone 4a of the collector. The substrate includes a lightly doped lateral zone and a highly doped central zone. The dopant species in the zone of the substrate are electrically inactive.

Abstract: An integrated circuit is manufactured from a semiconductor substrate having trenches with first and second sidewalls facing each other and a conductive line arranged in a bottom region of the trenches. At least the bottom region of the trenches is lined with an insulative material between the conductive line and the substrate. A first sacrificial layer is formed above the conductive line adjacent the first and second sidewalls. The trenches are filled with one or more additional sacrificial layers having a different etch selectivity than the first sacrificial layer. A portion of the one or more additional sacrificial layers and a portion of the insulative material are selectively removed to the first sacrificial layer so that the substrate is exposed below the first sacrificial layer along the first trench sidewalls and covered by the insulative material along the second trench sidewalls.

Abstract: The present invention is directed to a method for fabricating a thermal management substrate having a Silicon (Si) layer on a polycrystalline diamond film, or on a diamond-like-carbon (DLC) film. The method comprises acts of fabricating a separation by implantation of oxygen (SIMOX) wafer; depositing a polycrystalline diamond film onto the SIMOX wafer; and removing various layers of the SIMOX wafer to leave a Si overlay layer that is epitaxially fused with the polycrystalline diamond film. In the case of the DLC film, the method comprises acts of ion-implanting a Si wafer; depositing an amorphous DLC film onto the Si wafer; and removing various layers of the Si wafer to leave a Si overlay structure epitaxially fused with the DLC film.

Abstract: A semiconductor substrate is a semiconductor substrate used when an SOI substrate having an SOI structure is manufactured, in which a silicon oxide film and a silicon single crystal layer are formed on the surface of a silicon substrate. A region containing no nitrogen, which is made of a silicon single crystal layer with a thickness of 10 ?m or less, is formed in the vicinity of the surface, and the nitrogen concentration of a portion excluding the region, that is, the region containing nitrogen, is in a range of 1×1013 to 5×1015 atoms/cm3.

Abstract: The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.

Abstract: A method for producing a high-resistance SIMOX wafer wherein oxygen diffused inside of a wafer by the heat treatment at a high temperature in an oxidizing atmosphere can be reduced to suppress the occurrence of thermal donor. In one embodiment, a heating-rapid cooling treatment is conducted after the heat treatment at a high temperature in an oxidizing atmosphere to implant vacancies from a surface of a wafer into an interior thereof to thereby easily precipitate oxygen diffused inside the wafer during the heat treatment.

Abstract: Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises a shaped-modified isolation region that is formed in a trench generally between two doped wells of the substrate in which the bulk CMOS devices are fabricated. The shaped-modified isolation region may comprise a widened dielectric-filled portion of the trench, which may optionally include a nearby damage region, or a narrowed dielectric-filled portion of the trench that partitions a damage region between the two doped wells. Latch-up may also be suppressed by providing a lattice-mismatched layer between the trench base and the dielectric filler in the trench.

Abstract: A method for fabricating a semiconductor device comprises providing a silicon-containing substrate with first, second, and third regions. First, second, and third gate stacks respectively overlie a portion of the silicon-containing substrate in the first, second, and third regions. A spacer is formed on opposing sidewalls of each of the first, second, and third gate stacks, the spacer overlying a portion of the silicon-containing substrate in the first, second, and third regions, respectively. A source/drain region is formed in a portion of the silicon-containing substrate in the first, second, and third regions, with the source/drain region adjacent to the first, second, and third gate stacks, respectively. The first, second, and third gate stacks have first, second, and third gate dielectric layers of various thicknesses and at least one thereof with a relatively thin thickness is treated by NH3-plasma, having a nitrogen-concentration of about 1013˜1021 atoms/cm2 therein.

Abstract: A process for manufacturing a silicon-on-insulator substrate comprising a single-crystal silicon substrate in which an oxide layer has been locally buried includes forming a step on the silicon substrate so that a region corresponding to the oxide layer has a greater surface height than other regions; then implanting oxygen ions in the silicon substrate so as to form the oxide layer.

Abstract: A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain regions are typically located. The inventive multilayer stressor includes a first conformal epi semiconductor layer that is undoped or lightly doped and a second epi semiconductor layer that is highly dopant relative to the first epi semiconductor layer. The first and second epi semiconductor layers each have the same lattice constant, which is different from that of the substrate they are embedded in. The structure including the inventive multilayer embedded stressor achieves a good balance between stress proximity and short channel effects, and even eliminates or substantially reduces any possible defects that are typically generated during formation of the deep source/drain regions.

Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region. The method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting.

Abstract: The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.

Abstract: The invention provides methods for reducing trap densities at interfaces in a multilayer semiconductor wafer, specifically trap densities between an active layer and an insulating layer under the active layer. The methods comprise exposing wafers to high temperatures in a generally neutral atmosphere that also comprises one or more species that can, or whose ions can, migrate into the wafer down to the interface where reduction of the trap density is desired.

Abstract: A method of fabricating a semiconductor device, including: forming a first well of a second conduction type and a second well of a first conduction type on a semiconductor substrate of the first conduction type, forming a gate oxide corresponding to each element on a surface of the semiconductor substrate, forming trenches by etching at forming locations of first and second trench isolating regions respectively at a first depth larger than a depth of a diffusion layer formed in a memory-cell forming region within the second well and smaller than a depth of a diffusion layer of a transistor of a peripheral circuit region, executing additional etching at a forming location of the second trench isolating region so that a second depth larger than the first depth is obtained and doping the trenches at the forming locations of the first and second trench isolating regions respectively, with a doping agent, thereby executing a planarization process.

Abstract: To easily and accurately flush a substrate surface serving an SOI area with a substrate surface serving as a bulk area, make a buried oxide film, and prevent an oxide film from being exposed on substrate surface. After partially forming a mask oxide film 23 on the surface of a substrate 12 constituted of single crystal silicon, oxygen ions 16 are implanted into the surface of the substrate through the mask oxide film, and the substrate is annealed to form an buried oxide film 13 inside the substrate. Further included is a step of forming a predetermined-depth concave portion 12c deeper than substrate surface 12b serving as a bulk area on which the mask oxide film is formed on the substrate surface 12a serving as an SOI area by forming a thermally grown oxide film 21 on the substrate surface 12a serving as an SOI area on which the mask oxide film is not formed between the step of forming the mask oxide film and the step of implanting oxygen ions.

Abstract: A method of filling a trench in a substrate ensures that a void or seam is not left in the material occupying the trench. First, a preliminary insulating layer is formed so as to extend contiguously along the bottom and sides of the trench and along an upper surface of the substrate. Impurities are then implanted into a portion of the preliminary insulating layer adjacent the top of the first trench to form a first insulating layer having a doped region and an undoped region. The doped region is removed to form a first insulating layer pattern at the bottom and sides of the first trench, and which first insulating layer pattern defines a second trench. The second trench is then filled with insulating material.

Abstract: In an aspect, a method is provided for forming a silicon-on-insulator (SOI) layer. The method includes the steps of (1) providing a silicon substrate; (2) selectively implanting the silicon substrate with oxygen using a low implant energy to form an ultra-thin patterned seed layer; and (3) employing the ultra-thin patterned seed layer to form a patterned SOI layer on the silicon substrate. Numerous other aspects are provided.

Abstract: Embodiments of the present invention relate to the fabrication of a buried bi-layer insulator of silicon oxide and silicon nitride in a microelectronic substrate, and to the buried silicon oxide/silicon nitride bi-layer insulator itself. The buried silicon oxide/silicon nitride bi-layer insulator may be formed by implanting oxygen ions and nitrogen ions into the silicon-containing microelectronic substrate and then annealing the silicon-containing microelectronic substrate to form silicon oxide and silicon nitride layers therein.

Abstract: One aspect of the present subject matter relates to a memory cell, or more specifically, to a one-transistor SOI non-volatile memory cell. In various embodiments, the memory cell includes a substrate, a buried insulator layer formed on the substrate, and a transistor formed on the buried insulator layer. The transistor includes a floating body region that includes a charge trapping material. A memory state of the memory cell is determined by trapped charges or neutralized charges in the charge trapping material. The transistor further includes a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region. The transistor further includes a gate insulator layer formed over the channel region, and a gate formed over the gate insulator layer. Other aspects are provided herein.

Abstract: A semiconductor device in one embodiment has a first connection region, a second connection region and a semiconductor volume arranged between the first and second connection regions. Provision is made, within the semiconductor volume, in the vicinity of the second connection region, of a field stop zone for spatially delimiting a space charge zone that can be formed in the semiconductor volume, and of an anode region adjoining the first connection region. The dopant concentration profile within the semiconductor volume is configured such that the integral of the ionized dopant charge over the semiconductor volume, proceeding from an interface of the anode region which faces the second connection region, in the direction of the second connection region, reaches a quantity of charge corresponding to the breakdown charge of the semiconductor device only near the interface of the field stop zone which faces the second connection region.

Abstract: A SIMOX wafer is produced by implanting an oxygen ions into a surface of a Si substrate and then conducting a high-temperature annealing, in which an atmosphere in at least an end stage of the high-temperature annealing treatment is an Ar or N2 atmosphere containing an oxygen of more than 3 volume % but not more than 10 volume %.

Abstract: A method for forming a device isolation layer in a semiconductor substrate by destroying a lattice structure of the semiconductor substrate through a high-energy ion implantation process.

Abstract: To easily and accurately flush a substrate surface serving an SOI area with a substrate surface serving as a bulk area, make a buried oxide film, and prevent an oxide film from being exposed on substrate surface. After partially forming a mask oxide film 23 on the surface of a substrate 12 constituted of single crystal silicon, oxygen ions 16 are implanted into the surface of the substrate through the mask oxide film, and the substrate is annealed to form a buried oxide film 13 inside the substrate. Further included is a step of forming a predetermined-depth concave portion 12c deeper than substrate surface 12b serving as a bulk area on which the mask oxide film is formed on the substrate surface 12a serving as an SOI area by forming a thermally grown oxide film 21 on the substrate surface 12a serving as an SOI area on which the mask oxide film is not formed between the step of forming the mask oxide film and the step of implanting oxygen ions.

Abstract: This method for manufacturing a SIMOX wafer, includes: implanting oxygen ions in a silicon wafer; cleaning said silicon wafer into which said oxygen ions are implanted; and forming a buried oxide film within an interior of said silicon wafer by subjecting said cleaned silicon wafer to a heat treatment, wherein said method further includes immersing said silicon wafer in an aqueous solution of hydrofluoric acid and etching a SiO2 film formed on a surface of said silicon wafer, which is conducted after said implanting of oxygen ions in said silicon wafer, but prior to said cleaning of said silicon wafer, and an etching rate for said SiO2 film by said aqueous solution of hydrofluoric acid during said etching treatment is within a range from 150 to 3,000 (?/minute).

Abstract: A semiconductor device includes: a SOI substrate including a support layer, a first insulation film and a SOI layer; a first circuit; a second circuit; and a trench separation element. The SOI substrate further includes a first region and a second region. The first region has the support layer, the first insulation film and the SOI layer, which are stacked in this order, and the second region has only the support layer. The trench separation element penetrates the support layer, the first insulation film and the SOI layer. The trench separation element separates the first region and the second region. The first circuit is disposed in the SOI layer of the first region. The second circuit is disposed in the support layer of the second region.

Abstract: The present invention provides a semiconductor device includes: an element isolation region configured to be formed in a semiconductor substrate; a P-type field effect transistor configured to be formed in a first element formation region of the semiconductor substrate for which isolation by the element isolation region is carried out; an N-type substrate region configured to be formed in the semiconductor substrate for which isolation by the element isolation region is carried out, arsenic being ion-implanted into the N-type substrate region; a nickel silicide layer configured to be formed on the N-type substrate region; a first insulating film configured to cover the P-type field effect transistor and have compressive stress; and a second insulating film configured to cover the N-type substrate region and have tensile stress or compressive stress lower than the compressive stress of the first insulating film.

Abstract: This method for manufacturing a SIMOX wafer includes: heating a silicon wafer to 300° C. or more and implanting oxygen ions so as to form a high oxygen concentration layer within the silicon wafer; subjecting the silicon wafer to a cooling to less than 300° C. and an implanting of oxygen ions so as to form an amorphous layer; and subjecting the silicon wafer to a heat-treating in a mixed gas atmosphere containing oxygen so as to form a buried oxide layer. In the forming of the buried oxide layer, a starting temperature is less than 1350° C. and a maximum temperature is 1350° C. or more. This SIMOX wafer is manufactured by the above method and includes a BOX layer and a SOI layer on the BOX layer. The BOX layer has a thickness of 1300 ? or more and a breakdown voltage of 7 MV/cm or more, and the surface of the SOI layer and the interface between the SOI layer and the BOX layer have a roughness over a 10-?m square area of 4 ? rms or less.

Abstract: There is provided a method of producing a semiconductor device. The method includes the steps of: forming a first hard mask having an opening above a substrate; forming a sacrificial film above a side surface of the opening of the first hard mask; forming a second hard mask in the opening having the sacrificial film above the side surface; removing the sacrificial film after the second hard mask is formed; ion implanting a first conductivity-type impurity through the first hard mask; and ion implanting a second conductivity-type impurity through the first and second hard masks.

Abstract: A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.

Abstract: The present invention provides a method of forming a thin channel MOSFET having low external resistance. The method comprises forming a dummy gate region atop a substrate; implanting oxide forming dopant through said dummy gate to create a localized oxide region in a portion of the substrate aligned to the dummy gate region that thins a channel region; forming source/drain extension regions abutting said channel region; and replacing the dummy gate with a gate conductor.

Abstract: A semiconductor structure including a trench formed in a substrate and a buried isolation collar that extends about sidewalls of the trench. The buried isolation collar is constituted by an insulator formed from a buried porous region of substrate material. The porous region is formed from a buried doped region defined using masking and ion implantation or by masking the trench sidewalls and using dopant diffusion. Advantageously, the porous region is transformed to an oxide insulator by an oxidation process. The semiconductor structure may be a storage capacitor of a memory cell further having a buried plate about the trench and a capacitor node inside the trench that is separated from the buried plate by a node dielectric formed on the trench sidewalls.

Abstract: Methods of forming buried bit lines in a non-volatile memory device can include forming impurity regions in a substrate of a non-volatile memory device to provide immediately neighboring buried bit lines for the device and then forming a shallow trench isolation region in the substrate between the immediately neighboring buried bit lines to substantially equalize lengths of the immediately neighboring buried bit lines.

Abstract: In a MOSFET, after an element region is formed, a wiring layer is formed subsequently to a barrier metal layer, and hydrogen annealing is performed. However, in the case of an n-channel MOSFET, a threshold voltage is lowered due to an occlusion characteristic of the barrier metal layer. Thus, an increased impurity concentration in a channel layer causes a problem that reduction in an on-resistance is inhibited. According to the present invention, after a barrier metal layer is formed, an opening is provided in the barrier metal layer on an interlayer insulating film, and hydrogen annealing treatment is performed after a wiring layer is formed. Thus, an amount of hydrogen which reaches a substrate is further increased, and lowering of a threshold voltage is suppressed. Moreover, since an impurity concentration in a channel layer can be lowered, an on-resistance is reduced.

Abstract: The disclosure provides a method for manufacturing a semiconductor device. The method, in one embodiment, includes forming semiconductor features (405, 410, 415, 420, 425, 430, 435, 440, 445) over a substrate (310), and then forming a layer of material (510) over the semiconductor features (405, 410, 415, 420, 425, 430, 435, 440, 445). This method further includes selectively etching portions of the layer of material (510) based upon a density or size of the semiconductor features (405, 410, 415, 420, 425, 430, 435, 440, 445) located thereunder, and then polishing remaining portions of the layer of material (510).

Abstract: A sidewall oxidation process for use during the formation of a transistor such as a flash memory cell allows for improved control of a gate oxide profile. The method comprises doping transistor source and drain regions to different doping levels, then performing a transistor sidewall oxidation using a particular process to modify the gate oxide thickness. The oxide forms at a faster rate along the source sidewall than along the drain sidewall. By using ranges within the oxidation environment described, a source side gate oxide having a variable and selectable thickness may be formed, while forming a drain-side oxide which has a single thickness where a thinner layer is desirable. This leads to improved optimization of key competing requirements of a flash memory cell, such as program and erase performance, while maintaining sufficient long-term data retention. The process may allow improved cell scalability, shortened design time, and decreased manufacturing costs.

Abstract: A method for forming isolation structure for MOS transistor is disclosed, which includes forming a first photoresist layer over a sacrificed oxide layer of a semiconductor substrate, patterning the first photoresist layer to define a PMOS active region and a PMOS isolation region; implanting nitrogen ions into the PMOS isolation region through the sacrificed oxide layer by using the first photoresist layer as a mask; removing the first photoresist layer; forming a second photoresist layer over the sacrificed oxide layer, patterning the second photoresist layer to define a NMOS active region and a NMOS isolation region; implanting oxygen ions into the NMOS isolation region through the sacrificed oxide layer by using the second photoresist layer as a mask; removing the second photoresist layer and the sacrificed oxide layer; and annealing the semiconductor substrate to form isolation structures of PMOS and NMOS, respectively.

Abstract: Methods of fabricating a gate-insulating layer of a dual-gate semiconductor device are disclosed. A disclosed method comprises sequentially forming a buffer oxide layer and a nitride layer on a semiconductor substrate having at least one high voltage device area and at least one low voltage device area; forming at least one trench by selectively removing at least one portion of the buffer oxide layer, the nitride layer and the semiconductor substrate; forming at least one device isolation layer by depositing an oxide layer in the trench and planarizing the oxide layer; removing the nitride layer and the buffer oxide layer remaining on the high voltage device area; forming a first gate-insulating layer on the high voltage device area; removing the nitride layer and the buffer oxide layer remaining on the low voltage device area; and forming a second gate-insulating layer on the low voltage device area.

Abstract: The construction of Shallow Trench Isolation, STI, regions is integrated in to a SIMOX fabrication process for a Silicon On Insulator, SOI, wafer. Prior to the beginning of the SOI process, a preferred nitrogen (N2) implant is applied to the silicon wafer in areas designated as active regions. The nitrogen modifies the oxidation rate of later implanted oxygen. Regions where the N2 is implanted result in thinner oxide layers. The SIMOX process can begin following the implantation of nitrogen. This results in buried regions of thick and thin oxide layers at fixed depths in the Si substrate. Excess Si on top of the buried thick and thin oxide regions can be polished down to the thick oxide regions to form the active device regions over the thin oxide regions. Thus, the SOI wafer exhibits an STI structure upon completion of the SOI process without a need for additional STI manufacturing steps.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor and an integrated circuit including the same. The semiconductor device 100, among other things, may include a substrate 110 having a lattice structure and having an implanted precipitate region 120 located within the lattice structure. Additionally, the semiconductor device 100 may include a dynamic defect 125 located within the lattice structure and proximate the implanted precipitate region 120, such that the implanted precipitate region 120 affects a position of the dynamic defect 125 within the lattice structure. Located over the substrate 110 in the aforementioned semiconductor device 100 is a gate structure 160.

Abstract: A method for fabricating a transistor of a semiconductor device is provided. The method includes: forming device isolation layers in a substrate including a bottom structure, thereby defining an active region; etching the active region to a predetermined depth to form a plurality of recess structures each of which has a flat bottom portion with a critical dimension (CD) larger than that of a top portion; and sequentially forming a gate oxide layer and a metal layer on the recess structures; and patterning the gate oxide layer and the metal layer to form a plurality of gate structures.

Abstract: A self-aligned element isolation film structure in a flash memory cell and a forming method thereof are disclosed. An example method of forming a self-aligned element isolation film structure in a flash memory cell forms an insulating layer on a semiconductor substrate and forms a floating gate pattern on the insulating layer. The example method selectively implants ions in a portion of the insulating layer exposed by the floating gate pattern and forms a self-aligned element isolation film on the floating gate pattern by oxidizing and growing the portion of the insulating layer to which the ion implantation is performed.

Abstract: A method is provided for fabricating thin membrane structures in localized surface regions of a single crystal substrate. In the method, ion implantation masks are patterned on the surface of the single crystal substrate with openings that define the localized surface regions. Foreign ions are implanted through the openings into the single crystal substrate to modify the chemical and/or structural properties of subsurface layers at predetermined depths underneath super layers of material. These subsurface layers are removed by selective etching. The removal of the subsurface layers leaves the super layers of material intact as membrane structures on top of openings or channels corresponding to the space of the removed subsurface layers. At least one portion or end of a membrane structure remains attached to the single crystal substrate.

Abstract: Methods of fabricating a semiconductor device include forming a mask pattern on a semiconductor substrate and which exposes defined regions of the semiconductor substrate. Oxygen ions are implanted into the defined regions of the semiconductor substrate using the mask pattern as an ion implantation mask. The oxygen ion implanted regions of the semiconductor substrate are annealed at one or more temperatures in a range that is sufficiently high to form silicon oxide substantially throughout the oxygen ion implanted regions by reacting the implanted oxygen ions with silicon in the oxygen ion implanted regions, and that is sufficiently low to substantially prevent oxidation of the semiconductor substrate adjacent to the oxygen ion implanted regions.

Abstract: In general, the present invention discloses at least one trench isolation region formed in a semiconductor substrate to electrically and/or optically isolate at least one active region from another active region. The at least one trench isolation region comprises a bottom portion and first and second trench sidewalls. At least one trench sidewall is adjacent a doped region. The at least one sidewall adjacent a doped region has a higher impurity dopant concentration than impurity doped regions surrounding the at least one trench isolation region.

Abstract: Methods of forming a device isolation structure in a semiconductor device are disclosed. A disclosed method comprises forming a p-type well and an n-type well in a semiconductor substrate; sequentially depositing a gate insulating layer and a gate electrode material layer; depositing a protective layer on the gate electrode material layer; removing a portion of the protective layer, a portion of the gate electrode material layer, and a portion of the gate insulating layer to expose a surface area of the semiconductor substrate; performing ion implantation and heat treatment processes to form a device isolation structure; forming a gate electrode by removing a portion of the gate electrode material layer; forming an LDD region by implanting low concentration impurity ions in the semiconductor substrate; forming a spacers on a sidewall of the gate electrode; and forming a source/drain region by implanting high concentration impurity ions.

Abstract: A semiconductor having an optimized insulation structure which is simple and inexpensive to produce and can be made smaller than LOCOS insulation structures is disclosed. An implantation mask on a surface of a semiconductor substrate is used to implant elements into the semiconductor substrate, which elements, on thermal activation, form an insulation region together with the further elements of the semiconductor substrate. The thermal activation is effected by means of laser irradiation, during which the semiconductor substrate is briefly melted and then recrystallizes during the subsequent cooling, so that the implanted elements form the insulation region together with the further elements of the semiconductor substrate.