Abstract: A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage Vbd.

Abstract: A method for forming shallow junctions in a substrate. The substrate is masked with a first mask to selectively cover first portions of the substrate and selectively expose second portions of the substrate. A first dopant is implanted substantially within a first depth zone through the second portions of the substrate. The first depth zone extends from a first depth to a second depth, and the first depth is shallower than the second depth. The substrate is annealed for a first time to form a noncontiguous buried insulating layer substantially within the first depth zone in the second portions of the substrate. The substrate is masked with a second mask to selectively cover third portions of the substrate and selectively expose fourth portions of the substrate. The fourth portions of the substrate at least partially overlap the second portions of the substrate. A second dopant is implanted substantially within a second depth zone through the fourth portions of the substrate.

Abstract: According to the present invention, a semiconductor device to use a SOI substrate performing insulation by a LOCOS method in which an oxide resistivety film provided on a silicon layer is used, includes steps of: implanting impurity in a LOCOS edge which is a silicon layer under bird's beak of the field oxide film with the oxide resistant film as a mask after a field oxide film is formed and forming a high density impurity area having impurity density higher than impurity density of an impurity diffusion layer formed on the silicon layer, and removing a pad oxide film after a heat treatment is performed for the field oxide film after the high density impurity area is formed. Therefore, a method of manufacturing the semiconductor device at a lower cost to suppress occurrence of hump and to prevent a MOSFET characteristic from deteriorating can be provided.

Abstract: An isolation structure for high frequency integrated circuits is a conductive material disposed over a region of active gallium arsenide substrate. The conductive material over the active region creates a lossy RF path to reduce undesired coupling between adjacent conductors. In one case, two RF signal lines (1,2) terminated at the same via pad (3) have weaker coupling than in prior art via structures due to the lossy RF structure disposed on isolating fractional portions (10,11) of the via pad (3). The isolating fractional portion (10,11) are intermediate terminating fractional portions (8,9) of the via pad (3) to which the signal lines (1,2) are connected. In another case, two parallel bias lines (12,13) are disposed over an active layer region (6) increasing the RF loss between them and advantageously reducing the RF coupling. The reduced RF coupling improves RF isolation and permits increased miniaturization.

Abstract: An SOI FET comprising a silicon substrate having silicon layer on top of a buried oxide layer having doped regions and an undoped region is disclosed. The doped region has a dielectric constant different from the dielectric constant of the doped regions. A body also in the silicon layer separates the source/drains in the silicon layer. The source/drains are aligned over the doped regions and the body is aligned over the undoped region. A gate dielectric is on top of the body and a gate conductor is on top of the gate dielectric.

Abstract: A silicon-on-insulator substrate having improved thickness uniformity as well as a method of fabricating the same is provided. Specifically, improved thickness uniformity of a SOI substrate is obtained in the present invention by subjecting a bonded or SIMOX (separation by ion implantation of oxygen) SOI substrate to a high-temperature oxidation process that is capable of improving the thickness uniformity of said SOI substrate. During this high-temperature oxidation process surface oxidation of the superficial Si-containing (i.e., the Si-containing layer present atop the buried oxide (BOX) region) occurs; and (ii) internal thermal oxidation (ITOX), i.e., diffusion of oxygen via the superficial Si-containing layer into the interface that exists between the BOX and the superficial Si-containing layer also occurs.

Abstract: A microelectronic structure includes at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type. In a further aspect of the invention, a process for forming a microelectronic structure, such as a MOSFET, having at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type includes forming a recess having a surface, forming a dielectric material over a portion of the surface of the recess, and back-filling the recess to from a source/drain terminal.

Abstract: Disclosed is a semiconductor device having a reduced size, increased accuracy, and flattened element isolation regions with an decreased size. A plurality of MOSFETs having gate oxide films with different thicknesses and element isolation regions are formed by a manufacturing method employing oxygen implantation. An oxygen-ion implantation process and an annealing process are applied to a method of manufacturing the semiconductor device.

Abstract: A method of fabricating a silicon-on-insulator (SOI) substrate including at least one patterned buried oxide region having well defined edges is provided. The method includes a step of implanting first ions into a surface of a Si-containing substrate so as to form an implant region of the first ions in the Si-containing substrate. Following the first implant step, a selective implant process is employed wherein second ions that are insoluble in SiO2 are incorporated into portions of the Si-containing substrate. The second ions employed in the selective implant step are capable of preventing the implant region of first ions from forming an oxide region during a subsequent annealing step. An annealing step is then performed which causes formation of a buried oxide region in the implant region of first ions that does not include the second ions.

Abstract: Methods of producing buried insulating layers in semiconductor substrates are disclosed whereby a dose of selected ions is implanted into a substrate to form a buried precursor layer below an upper layer of the substrate, followed by oxidation of the substrate in an atmosphere having a selected oxygen concentration to form an oxide surface layer. The oxidation is performed at a temperature and for a time duration such that the formation of the oxide layer causes the injection of a controlled number of atoms of the substrate from a region proximate to an interface between the newly formed oxide layer and the substrate into the upper regions of the substrate to reduce strain. A high temperature annealing step is then performed to produce the insulating layer within the precursor layer.

Abstract: Methods and semiconductor structures are provided for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices. A bulk silicon substrate layer is provided that defines one power distribution rail. A high energy deep oxygen implant is performed to create a deep buried oxide layer and a first intermediate silicon layer. The deep buried oxide layer is disposed between the bulk silicon substrate layer and the first intermediate silicon layer. The first intermediate silicon layer defines another power distribution rail. A lower energy oxygen implant is performed to create a shallow buried oxide layer and a second intermediate silicon layer The shallow buried oxide layer is disposed between the first intermediate silicon layer and the second intermediate silicon layer. A connection to the bulk silicon substrate layer is formed without making electrical connection to the intermediate silicon layers.

Abstract: The present invention provides methods and system for forming a buried oxide layer (BOX) region in a semiconductor substrate, such as, a silicon wafer. In one aspect, in a method of the invention, an initial dose of oxygen ions is implanted in the substrate while maintaining the substrate temperature in a range of about 300° C. to 600° C. Subsequently, a second dose of oxygen ions is implanted in the substrate while actively cooling the substrate to maintain the substrate temperature in range of about 50° C. to 150° C. These ion implantation steps are followed by an annealing step in an oxygen containing atmosphere to form a continuous BOX region in the substrate. In one preferred embodiment, the initial ion implantation step is performed in a chamber that includes a device for heating the substrate while the second ion implantation step is performed in a separate chamber that is equipped with a device for actively cooling the substrate.

Abstract: A method is provided for making ultra-shallow diffused junctions using an elemental dopant. A semiconductor wafer is cleaned for providing a clean reaction surface. The cleaned wafer in loaded onto a stage located in a doping system. A quantity of elemental dopant atoms are placed in a partially enclosed elemental dopant source which is within a secondary vacuum enclosure. A quantity of the elemental dopant atoms having thermal velocities are deposited onto a surface of the wafer, and the wafer is heated for diffusing the elemental dopant into the wafer. In one embodiment, the heating is conducted by heating the wafer in ultra-high vacuum for diffusing the portion of the doping atoms into the wafer, and the deposition and heating occur simultaneously. In another embodiment, the surface of the wafer is hydrogen terminated, the wafer is removed from the UHV system, and the heating of the wafer is conducted outside of the UHV system by heating the wafer in a furnace.

Abstract: Methods of forming merged logic DRAM devices on silicon-on-insulator (SOI) wafers having a relatively thick buried oxide region, where deep trenches are etched into the SOI substrate without etching through the buried oxide layer are provided. The methods of the present invention provide high performance SOI merged logic DRAM devices.

Abstract: A semiconductor-on-insulator (SOI) chip. The SOI chip having a substrate; a buried oxide (BOX) layer disposed on the substrate; and an active layer disposed on the BOX layer, the active layer divided into a first tile and a second tile, the first tile having a first thickness and the second tile having a second thickness, the second thickness being smaller than the first thickness; wherein the BOX layer is formed under the active layer in an area of the first tile by implanting oxygen ions with a first energy level and a first dosage and the BOX layer is formed under the active layer in an area of the second tile by implanting oxygen ions with a second energy level and a second dosage.

Abstract: An integrated circuit and a process for making the same are provided. The circuit has a nitrogen implanted emitter window, wherein the nitrogen has been implanted into the emitter window after the emitter window etch, but prior to the emitter conductor deposition. Nitrogen implantation is expected to minimize oxide growth variation.

Abstract: A method for forming an isolation region in a semiconductor device, in which nitrogen ions are injected into a region of an isolation oxide film to form an oxynitride film, thereby preventing formation of a recess at a top edge of the isolation oxide film, which improves the device isolation characteristic. The method includes depositing a pad oxide film and a pad nitride film over a substrate. The pad oxide film, the pad nitride film, and the substrate are selectively removed to form a trench, which is then filled with an isolation oxide film. Nitrogen ions are injected into an entire surface of the pad nitride film, inclusive of the isolation oxide film, to form an oxynitride film in a region of the isolation oxide film. The pad nitride film and the pad oxide film are removed, and a gate oxide film and a polysilicon layer are deposited.

Abstract: A novel method for forming substrate contact regions on a SOI substrate without requiring additional space, and in order to provide lower diffusion capacitance. The method utilizes known semiconductor processing techniques. This method for selectively modifying the BOX region of a SOI substrate involves first providing a silicon substrate. Then, ion implanting the base using SIMOX techniques (e.g. O2 implant) is accomplished. Next, the substrate is photopatterned to protect the modified BOX region. Then, further ion implanting using a “touch-up” O2 implant is accomplished, thereby resulting in a good quality BOX as typically practiced. The final step is annealing the substrate. The area of the substrate, which had a mask present, would not receive the “touch-up” O2 implant (second ion implant), which in turn would result in a leaky BOX.

Abstract: A semiconductor device having an SOI structure capable of effectively preventing diffusion of an impurity from a source/drain region on an endmost portion of a silicon layer under a gate electrode is disclosed. In this semiconductor device, nitrogen is introduced into at least either a source/drain region or an end portion of a semiconductor layer located under a gate electrode, and the concentration profile of the nitrogen has a first concentration peak at least in either one of an endmost portion of the source/drain region in the direction where the gate electrode extends and an endmost portion of the semiconductor layer located under the gate electrode. Due to this concentration profile of nitrogen, point defects or the like serving as mediation for diffusion of an impurity are trapped, whereby diffusion of the impurity from the source/drain region is inhibited as a result. Thus, generation of an abnormal leakage current or the like is prevented.

Abstract: A method for forming a silicon on insulator substrate includes the step of dissociating a plasma of molecules including at least any one of oxygen and nitrogen to obtain ions. The ions are accelerated by passage through gaps between acceleration electrodes at a predetermined acceleration energy for irradiation of the accelerated ions onto a silicon substrate which is heated to form an insulation film within the silicon substrate.

Abstract: A method of fabricating a defect induced buried oxide (DIBOX) region in a semiconductor substrate utilizing an oxygen ion implantation step to create a stable defect region; a low energy implantation step to create an amorphous layer adjacent to the stable defect region, wherein the low energy implantation steps uses at least one ion other than oxygen; oxidation and, optionally, annealing, is provided. Silicon-on-insulator (SOI) materials comprising a semiconductor substrate having a DIBOX region in patterned or unpatterned forms is also provided herein.

Abstract: The present invention is directed to a process for producing a silicon on insulator (SOI) structure having intrinsic gettering, wherein a silicon substrate is subjected to an ideal precipitating wafer heat treatment which enables the substrate, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process to form an ideal, non-uniform depth distribution of oxygen precipitates, and wherein a dielectric layer is formed beneath the surface of the wafer by implanting oxygen or nitrogen ions, or molecular oxygen, beneath the surface and annealing the wafer. Additionally, the silicon wafer may initially include an epitaxial layer, or an epitaxial layer may be deposited on the substrate during the process of the present invention.

Abstract: A method for forming isolating structures in a silicon carbide layer includes depositing a masking layer on first and second portions of the silicon carbide layer, and forming openings through the masking layer to expose the first portions of the silicon carbide layer. Ions are implanted into the first portions of the silicon carbide layer. The silicon carbide layer is heated to form an oxide layer thereon having first portions on the first portions of the silicon carbide layer, and having second portions on the second portions of the silicon carbide layer. The first portions of the oxide layer are etched to form isolating regions in the silicon carbide layer.

Abstract: A semiconductor device and a method of forming thereof include a dummy active region positioned adjacent the device active region. The dummy active region is formed to include an oxide layer of a thickness that is less than the oxide layer of the active region such that excess charge accumulated during etching in the active region is conducted through the dummy active region into the substrate. In this manner, the dummy active region operates as a charge sink during formation of the active region to prevent premature deterioration of the gate oxide layer of the active region.

Abstract: A method for forming a silicon on insulator substrate includes the step of dissociating a plasma of molecules including at least any one of oxygen and nitrogen to obtain ions. The ions are accelerated by passage through gaps between acceleration electrodes at a predetermined acceleration energy for irradiation of the accelerated ions onto a silicon substrate which is heated to form an insulation film within the silicon substrate.

Abstract: Within a method for forming a series of gate dielectric layers having a plurality of thicknesses upon a semiconductor substrate, there is sequentially selectively stripped only a series of sacrificial gate dielectric layers only in locations where new gate dielectric layers are desired to be formed, rather masking a only a portion of a partially sacrificial gate dielectric layer which is desired to be retained and stripping a sacrificial remainder of the gate dielectric layer. By employing the sequential selective stripping method, a semiconductor integrated circuit microelectronic fabrication is formed with enhanced reliability insofar as there is attenuated over etching into isolation regions which separate active regions of a semiconductor substrate.

Abstract: Beam implantation is combined with plasma implantation of oxygen, and possibly also internal thermal oxidation, to form a high quality buried oxide layer.

Abstract: A method of substantially reducing charge build-up in a SOI device is provided. The method includes depositing a dielectric material on a surface of a semiconductor structure which includes at least silicon-on-insulator (SOI) devices therein. Next, a first conductive material is deposited on the dielectric material and then holes are drilled through the conductive material and the dielectric insulating material. Each hole is filled with a second conductive material, and thereafter selective portions of the first conductive material are removed to form contact pads for further probing. The method is especially useful in focused ion beam (FIB) drilling.

Abstract: Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as to form an inhibiting region in said structure; and (c) growing a dielectric layer on the structure in said opening, wherein the inhibiting region partially inhibits growth of the dielectric layer is capable of forming a semiconductor structure, e.g., MOSFET or anti-fuse, including a dual thickness dielectric layer. Alternatively, the dual thickness dielectric can be formed by replacing the inhibiting species mentioned above with a dielectric growth enhancement species which forms an enhancing region in the structure which aids in the growth of the dielectric layer.

Abstract: A patterned buried insulator is formed beneath the source and drain by forming a mask over the body area and implanting a dose of n or p type ions in the areas where the source and drains will be formed, then etching the STI and etching out the implanted area. A light oxidation is followed by a conformal oxide deposition in the STI and also in the etched area, thereby forming the buried oxide only where desired.

Abstract: A method and semiconductor structure are provided for implementing body contacts for semiconductor-on-insulator transistors. A bulk semiconductor substrate is provided. A mask is applied to the bulk semiconductor substrate to block an insulating implant layer in selected regions. The selected regions provide for body contact for transistors. Holes are formed extending into the bulk semiconductor substrate. The holes are filled with an electrically conductive material to create stud contacts to the bulk semiconductor substrate. In the preferred embodiment, the semiconductor-on-insulator is silicon on an oxide insulating layer and the invention provides a body contact for SOI transistors.

Abstract: A semiconductor device is provided in which a lowering in the breakdown voltage of a gate insulating film (nitrided silicon oxide film) in a boundary region between the upper-end corner portion of the side wall of an element isolating groove and a silicon substrate in the end portion of an element forming region which is formed in contact therewith can be suppressed without causing an increase in the number of steps (time for effecting the steps).

Abstract: A method of fabricating a trench isolation structure in a high-density semiconductor device that provides an isolation characteristic that is independent of the properties of adjacent MOS transistor devices, wherein a first trench in a first isolation area and a second trench implanted are formed on a semiconductor substrate, a nitrogen (N)-rich silicon layer is formed on the sidewall in a second isolation area, a subsequent oxidation process may be employed to fabricate oxide layers, each having a different thickness, on the sidewall surfaces of the first and second trenches. When the first and second oxide-layered trenches are filled with a stress relief liner and a dielectric material, the different thicknesses of the oxides prevent leakage currents from flowing to an adjacent semiconductor device, regardless of the doping properties of each device.

Abstract: A semiconductor-on-insulator (SOI) device includes a buried insulator layer and an overlying semiconductor layer. At least parts of the buried insulator layer include a nitrided semiconductor oxide. The nitrided semiconductor oxide may be formed by means of a nitride implant with sufficient energy to pass through a surface semiconductor layer and penetrate into a buried oxide layer. Following the nitride implant the device may be annealed to remove damage to the surface semiconductor layer, as well as to form a high quality nitrided oxide in the buried insulator layer. The nitrided semiconductor oxide material may reduce or prevent depletion of dopant material from portions of the surface semiconductor layer, such as from channel portions of NMOS transistors.

Abstract: A relatively thick gate oxide film and a relatively thin gate oxide film are formed on a surface of silicon substrate. In a region exactly under the relatively thick gate oxide film, a halogen is added only within a depth range of no more than 2 nm from the main surface of silicon substrate. Thus, a semiconductor device having a dual gate oxide and a method of manufacturing the same can be obtained capable of reducing damage to the substrate through a simplified process.

Abstract: Semiconductor devices and processes for forming the same. The semiconductor device includes field isolation regions within trenches lying within a semiconductor device substrate. The trenches include a first trench and a second trench. The device includes a first component region and a second component region. The first component region lies near the first trench, and the second component region lies near the second trench. The semiconductor device includes a feature selected from a group consisting of: (a) a first liner within the first trench, and a second liner within the second trench, wherein the first liner is significantly thicker than the second liner; and (b) the first component region has a first edge with a first radius of curvature near the first trench, and the second component has a second edge with a second radius of curvature near the second trench, wherein the first radius of curvature is significantly greater than the second radius of curvature.

Abstract: A patterned buried insulator is formed beneath the source and drain by forming a mask over the body area and implanting a dose of n or p type ions in the areas where the source and drains will be formed, then etching the STI and etching out the implanted area. A light oxidation is followed by a conformal oxide deposition in the STI and also in the etched area, thereby forming the buried oxide only where desired.

Abstract: A method for forming shallow trench isolation is disclosed. A pad oxide layer and a mask layer are sequentially formed on a substrate. Afterwards, an opening is formed through the mask layer and the pad oxide layer such that regions of the substrate are exposed. Thereafter, the exposed regions are etched to form trenches inside said substrate. Next, nitrogen ions are implanted into the sidewall of the trenches to form a silicon nitride layer, and then a siliconoxynitride layer is formed inside the sidewall of the trenches. Subsequently, a silicon oxide layer is formed on the siliconoxynitride layer and on the mask layer. The excess portion of the silicon oxide layer over said mask layer is removed to expose the mask layer, and then the mask layer is removed away. Finally, the pad oxide layer is removed by using hydrofluoric acid (HF).

Abstract: A semiconductor device having a SGI structure produced by selecting D, T and R values for satisfying the formula: D<0.4(−100R+7)−1(−230 T+14.5), wherein D is a width of an element formation region, T is a thermal oxidation amount of a groove in terms of microns, and R is a curvature radius at an end bottom portion of the groove, has excellent properties such as reduced in stress generated at bottom portions of grooves in a silicon substrate and not generating abnormal junction leakage current.

Abstract: An ion implantation system for producing silicon wafers having relatively low defect densities, e.g., below about 1×106/cm2, includes a fluid port in the ion implantation chamber for introducing a background gas into the chamber during the ion implantation process. The introduced gas, such as water vapor, reduces the defect density of the top silicon layer that is separated from the buried silicon dioxide layer.

Abstract: The present invention provides a method for forming a dielectric 1; 7, 8 on a semiconductor substrate 2 having the following steps: implantation of ions into a surface layer of the semiconductor substrate 2, the ions forming a first dielectric layer 7; and performance of a thermal oxidation process for forming a second dielectric layer 8 on the first dielectric layer 7. Consequently, e.g. by the implantation of nitrogen ions into a surface layer of a silicon substrate, the imperfection density of the dielectric formed can be reduced approximately by a factor of 10.

Abstract: A circuit isolation technique that uses implanted ions in embedded portions of a wafer substrate to lower the resistance of the substrate under circuits formed on the wafer or portions of circuits formed on the wafer to prevent the flow of injected currents across the substrate. The embedded ions provide low resistance regions that allow injected currents from a circuit to flow directly to a ground potential in the same circuit rather than flowing across the substrate to other circuits. High energy implantation processes on the order of 1 MeV to 3 MeVs can be used to implant the ions in embedded regions. Multiple energy levels can be used to provide thick embedded layers either prior to or after application of an epitaxial layer. Various masking materials can be used to mask the isolation regions during the implantation process, including hard masking materials such as silicon dioxide or silicon nitride, poly-silicon or an amorphous silicon layer, and a photoresist layer.

Abstract: This invention discloses a method for fabricating SOI material, incorporating an amorphous process introduced by ion implantation in the conventional SIMOX methods, which enhances diffusion of various atoms in the amorphous region in annealing process. It realizes under a lower temperature annealing to eliminate threading dislocations and other crystal defects in the top silicon layer and silicon islands, pinholes and other silicon segregation products in the buried oxide layer and fabricate high quality of SOI material. Another method for forming SOI material is also described, incorporating an amorphous process introduced by ion implantation in the SIMNI or SIMON methods. It forms amorphous buried nitride or oxynitride layer, a top single crystal silicon layer and a sharp interface between the top layer and the buried layer.

Abstract: The method of the present invention applies to any semiconductor structure provided with polysilicon filled deep trenches formed in a silicon substrate coated by a Si3N4 pad layer both in the “array” and “kerf” areas. First, a photoresist mask is formed onto the structure and patterned to expose the deep trenches only in the “array” areas. Deep trenches are then anisotropically dry etched to create recesses having a determined depth. Next, the photoresist mask is removed only in the “array” areas. A step of anisotropic dry etching is now performed to extend said recesses down to the desired depth to create the shallow isolation trenches. The photoresist mask is totally removed. A layer of oxide (STI oxide) is conformally deposited by LPCVD onto the structure to fill said shallow isolation trenches in excess. The structure is planarized to create the STI oxide regions and expose deep trenches in the “kerf” areas.

Abstract: A single-crystal silicon substrate having a surface layer which has been heat-treated in a reducing atmosphere containing hydrogen is prepared. An ion-implantation layer is formed by implanting oxygen ions. Subsequently, a buried oxide film (BOX) layer is formed by a desired heat-treatment utilizing the ion-implantation layer. An SOI substrate having a single-crystal silicon layer (SOI layer) which is formed on the BOX layer and has a remarkably reduced number of defects such as COPs is obtained.

Abstract: A method of forming a patterned buried oxide film, includes performing an implantation into a substrate, forming a mask on at least portions of the substrate for controlling the implantation diffusion, and annealing the substrate to form a buried oxide. The mask may be selectively patterned. A region that is covered by the mask has a thinner buried oxide than an area which is exposed directly to the annealing ambient.

Abstract: A method and semiconductor structure are provided for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors. A bulk silicon substrate is provided. A deep ion implant layer is implanted to reside below an oxide insulator. An oxygen implant layer is implanted while applying a mask to block the oxygen implant layer in selected regions. The selected regions provide for body contact for the SOI transistors. Holes are formed extending into the deep ion implant layer and the bulk silicon substrate. The holes are filled with an electrically conductive material to create stud contacts to the deep ion implant layer and the bulk silicon substrate.

Abstract: A conventional initial deep trench structure consists of a patterned Si3N4 pad layer coated silicon substrate with deep trenches formed therein. The trenches are partially filled with doped polysilicon (POLY1). A dielectric film is interposed between said polysilicon fill and the substrate to create the storage capacitor. A TEOS SiO2 collar layer conformally coats the upper portion of the structure. Now, the TEOS SiO2 is dry etched in a two-step process performed in the same RIE reactor. In the first step, the TEOS SiO2 is etched at least 6 times faster than the Si3N4 (stopping on the Si3N4 pad layer). In the second step, the operating conditions ensure a partially isotropic dry etch, preferably with twice the power and 1.25 times the pressure, thus providing a vertical etch rate 6× the horizontal rate. As a result of this step, the upper part of the silicon substrate in the trench is exposed without damages.

Abstract: A process for fabricating a tapered trench on a silicon substrate. The process comprises the steps of forming an initial trench in the substrate and implanting nitrogen ions on the initial trench side walls. More nitrogen ions are implanted adjacent the exposed surface of the substrate than adjacent the trench bottom. Finally, the initial trench side walls are oxidized to create the tapered shape.

Abstract: The invention provides a method for fabricating a shallow trench isolation which is not susceptable to buried contact trench formation. The invention also provides immunity from the STI “kink effect,” as well as benefits associated with nitridation. The process begins by forming a pad oxide layer on a semiconductor substrate. A nitride layer is formed on the pad oxide layer. The nitride layer, the pad oxide layer, and the semiconductor substrate are patterned to form trenches. Next, a fill oxide layer is formed over the nitride layer, the pad oxide layer, and the semiconductor substrate. The fill oxide layer is chemical-mechanical polished, stopping on the nitride layer to form fill oxide regions. N2 ions are implanted into the fill oxide regions. An anneal is performed to form a buried oxynitride layer. The buried oxynitride layer is partially above the level of the top surface of the semiconductor substrate and partially below the level of the top surface of the semiconductor substrate.