Abstract: A method for fabricating a semiconductor device of the present invention comprises steps of forming a first oxide layer on a semiconductor substrate comprising a memory cell unit and an input/output circuit unit, removing selectively the first oxide layer on the memory cell unit, forming a photoresist layer on the first oxide layer on the input/output circuit unit and the semiconductor substrate of the memory cell unit, forming openings on regions where gate electrodes will be formed by patterning the photoresist layer, forming oxygen containing layers by implanting the oxygen ion in the semiconductor substrate on the memory cell unit and the first oxide layer of the input/out circuit unit through the openings, removing the photoresist layer, forming a trench inside of the semiconductor substrate on the memory cell unit by removing the oxygen containing layer formed in the semiconductor substrate, etching the first oxide layer as a certain thickness, forming the gate electrodes on the upper surface of the fir

Abstract: A method of forming a semiconductor component having a conductive line (24) that crosses a trench (72) may include forming the trench (72) in a semiconductor substrate (52). A dopant may be implanted at a first energy level into the semiconductor substrate (52) to form a first conductive region (92). The dopant may be implanted at a second energy level into the semiconductor substrate (52) to form a second conductive region (94). The first energy level may be greater than the second energy level. The first conductive region (92) and the second conductive region (94) may form the conductive line (24).

Abstract: A process for creating a substrate including bulk silicon regions and semiconductor-on-insulator regions. Regions of a surface of a bulk silicon substrate are recessed above regions where it is desired to create buried oxide regions in the substrate. Implant mask regions are formed on the surface of the substrate over regions where it is not desired to create buried oxide regions. Buried oxide regions are formed in the substrate under the recessed regions in the substrate. The implant mask regions are removed, leaving bulk silicon regions between the buried oxide regions.

Abstract: In a method of manufacturing a TFT using a crystalline silicon film in which defects are compensated by a thermal oxidation step, the roughness of a thermal oxidation film formed by thermal oxidation is made small. In the method, first, an amorphous silicon film to which an impurity for suppressing crystallization, such as nitrogen, oxygen, or carbon, is formed on a crystalline silicon film used as an active layer. Since crystallization of this amorphous silicon film is suppressed, it can be thermally oxidized in the state of an amorphous or microcrystalline, and the thermal oxidation film with small roughness can be obtained. By using this thermal oxidation step, it is possible to suppresses generation of a gate leak, to suppresses fluctuation of TFT characteristics in the same substrate to the minimum, and to manufacture a semiconductor device capable of operating at high speed.

Abstract: The invention relates to a method of producing a thin layer of semiconductor material including:

Abstract: Implanted regions, formed in a semiconductor substrate by ion implanting oxygen or nitrogen ions, are converted to dielectric isolation regions by high temperature annealing. In some embodiments, oxygen and/or nitrogen ions are implanted at multiple predetermined depths to provide a graded implant profile in the implanted regions. In some embodiments, oxygen and/or nitrogen ions are implanted to have a peak concentration at a predetermined depth in the implanted regions. High temperature annealing is performed in an inert atmosphere or in an atmosphere having trace amounts of oxygen present for some or all of the anneal time.

Abstract: A fabrication method of a device isolation structure. A patterned mask layer is formed on a silicon substrate. A dopant is doped into an exposed substrate to prevent a bird's beak silicon region from being oxidized in a first doping step. A spacer is formed on the sidewall of the mask layer. Portions of the silicon substrate are removed to form a trench by using the mask layer and the spacer as a mask. A second dopant is doped into the exposed silicon substrate on the bottom of the trench to benefit the oxidation of a desired field oxide region in a second doping step. A field oxide layer is formed to fill the trench in a field oxide process.

Abstract: An ion implantation system for producing silicon wafers having relatively low defect densities, e.g., below about 1×106/cm2, includes a fluid port in the ion implantation chamber for introducing a background gas into the chamber during the ion implantation process. The introduced gas, such as water vapor, reduces the defect density of the top silicon layer that is separated from the buried silicon dioxide layer.

Abstract: A buried wiring line. The structure of the buried wiring line at least comprises a conductive doped region in a provided substrate and a silicon nitride region formed around the conductive doped region in the substrate. The silicon nitride region, which comprises a first silicon nitride below the doped region and a second silicon nitride layer beside the doped region, isolates the buried wiring line from the substrate.

Abstract: A method of fabricating a shallow trench isolation includes formation of a polishing stop layer. The polishing stop layer is formed in a fill material by performing ion implantation to implant atoms in the fill material. The depth of the polishing stop layer can be controlled by the energy of the implanted atoms. The polishing stop layer prevents the fill material from being dished by chemical-mechanical polishing. The polishing stop layer also prevents scratches from forming in the surface of the fill material, which is used to form isolation regions.

Abstract: A method for making an SOI semiconductor device including a silicon substrate includes implanting oxide and Nitrogen into the substrate and then annealing to drive Oxygen and Nitrogen through and below the buried oxide layer. The implanted species interact with the Silicon matrix of the substrate to establish field isolation areas that extend deeper than the buried oxide layer of the SOI device, to ensure adequate component isolation.

Abstract: An object is to provide a semiconductor substrate processing method and a semiconductor substrate that prevent formation of particles from the edge part of the substrate. Silicon ions are implanted into the edge part of an SOI substrate (10) in the direction of radiuses of the SOI substrate (10) to bring a buried oxide film (2) in the edge part of the SOI substrate (10) into a silicon-rich state. Thus an SOI substrate (100) is provided, where the buried oxide film (2) has substantially been eliminated in the edge part.

Abstract: A method for fabricating a first memory cell and a second memory cell electrically isolated from each other. The method including forming a first polysilicon (poly I) layer on an oxide coated substrate and masking the poly I layer to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator such that the insulator electrically isolates the poly I layer (e.g., floating gate) of the first memory cell from the poly I layer (e.g., floating gate) of the second memory cell.

Abstract: Method for forming quantum dots using agglomeration of a conductive layer and a semiconductor device resulting therefrom are disclosed. The method includes the steps of forming a first insulating layer on a substrate, forming a conductive layer on the first insulating layer, forming a second insulating layer on the conductive layer, and annealing the conductive layer between the first, and second insulating layers to agglomerate the conductive layer.

Abstract: A semiconductor device isolation structure includes a semiconductor substrate including an active region and a field region, an insulation layer buried in the active region of the substrate, and an isolation layer formed in the field region of the substrate deeper than the buried insulation layer. A method for isolating a semiconductor device includes the steps of preparing a semiconductor substrate, defining an active region and a field region in the substrate, forming an insulation layer buried in the active region of the substrate, and forming an isolation layer in the field region of the substrate to be deeper than the buried insulation layer. The invention applies to an SOI (Silicon On Insulator) provided with a SIMOX (Separation by Implanted Oxygen) type, for effectively overcoming interfacial defects between a buried oxide film and a semiconductor substrate, and improves a reliability of the semiconductor device by planarizing the same.

Abstract: Oxygen implantation can be used to form a buried oxide layer in a substrate. A dielectric masking material is used to shape the buried oxide layer by changing the depth at which ions can implant based on the shape of the dielectric masking layer.

Abstract: The present invention relates to the electrical isolation of components within an integrated opto-electronic device where two or more active regions are optically coupled, for example by a waveguide. The device includes a distributed feed-back laser diode and an electro-absorption modulator fabricated on the same substrate. The laser diode and modulator are: separated by an electrical isolation region; linked optically across the isolation region by a waveguide; and capped by a ternary cap layer through which ohmic contacts are made to operate the components. The cap layer extends to the isolation region from which a grounding contact is made to ground the cap layer in the isolation region and so to electrically isolate the laser diode and modulator from each other.

Abstract: A semiconductor device structure with differential field oxide thicknesses. A single field oxidation step produces a nitrided field oxide region (322) that is thinner than a non-nitrided field oxide region (324). The bird's beak (326) of the nitrided field oxide (322) encroaches less into the active cell region than the bird's beak (328) of the thicker non-nitrided field oxide (324). The differential field oxide thicknesses allow isolation of multi-voltage integrated circuit devices, such as flash memory devices, while increasing available active cell area for a given design rule.

Abstract: Ions are implanted into a silicon nitride film at a dose of not more than 1.times.10.sup.15 cm.sup.-2 so that the projected range of the ions is 20 to 60% of the thickness of the silicon nitride film. This enables the stress of the nitride film to be reduced while enjoying good productivity without introduction of defects into a silicon substrate.

Abstract: The formation of a fully-depleted, ESD protected CMOS device is described. The device is formed on an SOI or SIMOX substrate, over which an oxide pad is grown to a thickness of between 10 and 30 nm. Appropriate ions are implanted into the oxide to adjust the threshold voltage of an ESD transistor. A portion of the top silicon film is thinned to a thickness no greater than 50 nm. The fully depleted CMOS devices are fabricated onto the thinned top silicon film, while the ESD devices are fabricated onto the top silicon film having the original thickness.

Abstract: A semiconductor fabrication process uses a buried, oxygen-rich layer as a stop etch in a trench isolation area, with minimal masking. According to one embodiment, the process involves applying a mask to protect selected portions of a silicon-based substrate, and then using the mask to implant an oxygen-based substance into unmasked portions of the substrate, thereby forming a buried oxygen layer at a selected depth within the substrate. The same mask is then used in an etching process to form the desired trench structure. The depth of the trench is defined as a result of terminating the etch process upon reaching the buried oxygen layer.

Abstract: First, oxygen ions of a high concentration are implanted into a silicon substrate 1, by which a high-concentration oxygen implanted layer 3 is formed. Subsequently, a heat treatment for about 4 hours at 1350.degree. C. is carried out in an atmosphere of Ar with a 0.5% concentration oxygen for the formation of a buried oxide layer 5. Next, pulse laser annealing is performed for melting and recrystallization of the surface silicon layer. Pulsed laser beam is radiated at an energy density of 1200 mJ/cm.sup.2 or more. The pulsed laser beam is able to melt the semiconductor surface in several 10's nsec by virtue of its extremely large power density in irradiation of 10.sup.7 W/cm.sup.2. By iterating this pulse laser annealing, the surface silicon layer iterates to melt and recrystallize, activating the activities of crystal defects, by which damage recovery based on crystal seeds is accomplished.

Abstract: A transistor and a method of making the same are provided. The transistor includes a substrate that has an upper surface and a gate dielectric layer positioned on the substrate that has a first quantity of nitrogen therein. A gate electrode is positioned on the gate dielectric layer. First and second source/drain regions are positioned in the substrate and laterally separated to define a channel region beneath the gate dielectric layer. The gate dielectric layer may be composed of a high K material with a thin equivalent thickness of oxide, such as TiO.sub.2, Ta.sub.2 O.sub.5, CrO.sub.2 or SrO.sub.2. The nitrogen suppresses later oxide formation which may otherwise increase the equivalent thickness of oxide of the gate dielectric layer. Nitrogen may also be incorporated into the substrate and the gate electrode.

Abstract: Disclosed are an isolation film of a semiconductor device and a method for fabricating the same, which prevent the isolation film from being damaged due to misalignment when forming a contact hole in a region adjacent to the isolation film, to ensure stable effective isolation distance. The isolation film of a semiconductor device includes a semiconductor substrate, a lower isolation film formed in the semiconductor substrate, and an upper isolation film formed on the lower isolation film, with a material having etching selectivity different from the lower isolation film.

Abstract: A layer of silicon oxide is first formed on the silicon substrate. A mask is then formed on the oxide layer to define at least one surface region of the oxide that is not covered by the mask and a continuous strip of mask material that extends continuously around the unmasked oxide surface region. The mask is then used to etch the oxide surface region to expose an underlying substrate surface region and, thereby creating a continuous wall of oxide around the substrate surface region. The mask is then removed and oxygen ions are implanted into the silicon substrate to define a horizontal layer of oxide ions within the substrate. The wall of oxide surrounding the substrate surface region impairs the implant of oxygen ions beneath the wall such that a continuous substantially vertical wall of oxygen ions is formed in the substrate extending from the perimeter of the horizontal oxygen ion layer to the surface of the substrate.

Abstract: The radiation hardness of a microelectronic device is improved by implant dopant ions, such as Si, into an oxide layer. This implantation creates electron traps/recombination centers in the oxide layer. A subsequent anneal remove defects in the active silicon layer.

Abstract: Semiconductor devices are formed in a semiconductor substrate having an essentially planar upper surface. In some embodiments, implanted regions are formed in the substrate at a first predetermined depth by implantation of oxygen and/or nitrogen ions. In some embodiments buried implanted are formed in the substrate at a second predetermined depth, deeper than the first depth by implantation of oxygen and/or nitrogen ions. These implanted regions are converted to dielectric isolation regions and buried dielectric regions, respectively, by a high temperature anneal after formation of a gate structure.

Abstract: A semiconductor apparatus and fabrication method for forming oxide isolation regions in a semiconductor substrate for use in forming self-aligned, floating gate MOS structures or other semiconductor devices. The method includes providing a semiconductor substrate member prefabricated having a barrier oxide layer, a polysilicon layer and a plurality of spaced apart silicon nitride layer portions fabricated on the polysilicon layer. The nitride layer portions delineate regions for forming the self-aligned floating gate MOS structures, as well as delineating portions of the silicon dioxide layer and portions of said polysilicon layer that are unprotected by the plurality of silicon nitride layer portions. The method further includes the step of implanting oxygen O.sub.2 ions into regions of the substrate, including those unprotected portions of the silicon dioxide layer and portions of the polysilicon layer to form the oxide isolation regions.

Abstract: An STI fabrication method for a semiconductor device is disclosed, which includes the steps of forming a trench on a semiconductor substrate, forming a conductive film on the trench, ion-implanting a germanium into the conductive film, and oxidizing the conductive film.

Abstract: The present invention solves the problem of how to form local regions of semi-insulating material within a single crystal substrate. It does this by irradiating the semiconductor with a high energy beam capable of producing radiation damage along its path. As a consequence of such radiation damage the resistivity of the semiconductor in the irradiated area is increased by several orders of magnitude, causing it to become semi-insulating. Semi-insulating regions of this type are effective as electrically isolating regions and can be used, for example, to decouple analog from digital circuits or to maintain high Q in integrated inductors after these devices have been made. The radiation used could be electromagnetic (such as X-rays or gamma rays) or it could comprise energetic particles such as protons, deuterons, etc. Confinement of the beam to local regions within the semiconductor is accomplished by means of suitable masks.

Abstract: A method for forming field isolation regions in multilayer semiconductor devices comprises the steps of masking active regions of the substrate, forming porous silicon in the exposed field isolation regions, removing the mask and oxidizing the substrate. A light ion impurity implant is used to create pores in the substrate. Substrate oxidation proceeds by rapid thermal annealing because the increased surface area of the pores and the high reactivity of unsaturated bonds on these surfaces provides for enhanced oxidation.

Abstract: A monolthically integrated VCSEL and photodetector, and a method of manufacturing same, are disclosed for applications where the VCSEL and photodetector require separate operation such as duplex serial data communications applications. A first embodiment integrates a VCSEL with an MSM photodetector on a semi-insulating substrate. A second embodiment builds the layers of a p-i-n photodiode on top of layers forming a VCSEL using a standard VCSEL process. The p-i-n layers are etched away in areas where VCSELs are to be formed and left where the photodetectors are to be formed. The VCSELs underlying the photodetectors are inoperable, and serve to recirculate photons back into the photodetector not initially absorbed. The transmit and receive pairs are packaged in a single package for interface to multifiber ferrules. The distance between the devices is precisely defined photolithographically, thereby making alignment easier.

Abstract: A modified LOCOS isolation process for semiconductor devices is disclosed. First, a shielding layer is formed overlying a semiconductor substrate. The shielding layer is then patterned to form an opening that exposes a portion of the semiconductor substrate for forming a device isolation region. Next, oxygen ions are implanted with a tilt angle into the semiconductor substrate to form a doped region extending to the area under the margin of the shielding layer. A thermal oxidation process is then performed to form a field oxide layer on the semiconductor substrate. Since the oxidation rate of the area under the margin of the shielding layer is increased by the implanted oxygen ions, the bird's beak effect shown in conventional LOCOS process can be eliminated. After that, the shielding layer is removed to complete the fabricating process of this invention.

Abstract: The method of the present invention is a method of including forming an oxide layer on the substrate. A nitride layer is subsequently formed on the oxide layer. A photoresist layer is formed on the nitride layer to define isolation regions that uncovered by the photoresist layer. A liquid phase deposition oxide is deposited on the isolation regions. Then the photoresist layer is removed. After removing the photoresist layer, an oxygen ion implantation is performed through the oxide layer and the nitride layer into the substrate by using the liquid phase deposition oxide layer as implant mask to form relative high oxygen ion contained regions in the substrate. After the ion implantation is done, the liquid phase deposition oxide layer is removed. An annealing process is carried out to form isolation regions in the substrate and recover implant-induced damage.

Abstract: An epitaxial layer with a doping of approximately 10.sup.12 atoms per cm.sup.2 is used in accordance with the resurf condition for the high-voltage circuit element in high-voltage integrated circuits of the resurf type. If the circuit comprises a zone which is provided in the epitaxial layer, which is of the same conductivity type as the substrate, and to which a high voltage is applied, the doping between this zone and the substrate must in addition be sufficiently high for preventing punch-through between the zone and the substrate. A known method of complying with these two requirements is to make the epitaxial layer very thick. It is found in practice, however, that this method is often not very well reproducible. According to the invention, the epitaxial layer is provided in the form of a high-ohmic layer which is doped from the upper side (3a) and from a buried layer (3b).

Abstract: A method for fabricating a periodic table group III-IV HEMT/pHEMT field-effect transistor device. The disclosed fabrication arrangement uses a single metalization for ohmic and Schottky barrier contacts, employs selective etching with a permanent etch stop layer, employs a non-alloyed ohmic contact semiconductor layer and includes a permanent non-photosensitive secondary mask element. The invention includes provisions for both an all optical lithographic process and a combined optical and electron beam lithographic process These concepts are combined to provide a field-effect transistor device of reduced fabrication cost, increased dimensional accuracy and state of the art electrical performance.

Abstract: A structure for a complementary field effect transistor includes a semiconductor body having a first body region of a first conductivity type and an adjoining second body region of an opposite second conductivity type. A buried dielectric region is located in the semiconductor body beneath the upper semiconductor surface and extends into the first and second body regions. A first drain region of the second conductivity type is located in the semiconductor body and adjoins the first body region, the dielectric region and the upper semiconductor surface. A second drain region of the first conductivity type is located in the semiconductor body and adjoins the second body region, the dielectric region and the upper semiconductor surface. The two drain regions are adjacent to one another.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, an active layer in the substrate and a silicon carbide buried layer which provides a conduction barrier between the substrate and at least a portion of the active layer. The buried layer is preferably formed by implanting second conductivity type dopants into the substrate so that a P-N junction barrier is provided between the active layer and the substrate. The buried layer may also be formed by implanting electrically inactive ions into the substrate so that a relatively high resistance barrier is provided between the active layer and the substrate. The electrically inactive ions are preferably selected from the group consisting of argon, neon, carbon and silicon, although other ions which are electrically inactive in silicon carbide may be used.

Abstract: In a method manufacturing a semiconductor device, a semiconductor layer having a device forming region is formed on substrate. Next, a region except for the device forming region is changed into an insulator. In this case, a conducting path is left across the semiconductor device to electrically connect the semiconductor device with an adjacent semiconductor device. Subsequently, the device forming region is etched on the condition that the conducting path is left. Finally, the conducting path is disrupted after the etching process. Thus, the semiconductor device and the adjacent semiconductor device are left in an electrical contact via the conducting path during the etching process. Consequently, the uniformity of the etching between the semiconductor devices is largely improved.

Abstract: Generally, the present invention relates to a semiconductor device having a dual thickness gate dielectric along the channel and a process of fabricating such a device. By providing a dual thickness gate dielectric, the gate dielectric can, for example, be optimized to the transistor and device performance can be enhanced.

Abstract: A method of producing an SOI substrate having a single-crystal silicon layer on a buried oxide layer in an electrically insulating state from the substrate by implanting oxygen ions into a single crystal silicon substrate and practicing an anneal processing in an inert gas atmosphere at high temperatures to form the buried oxide layer. After the anneal processing in which the thickness of the buried oxide layer becomes a theoretical value in conformity with the thickness of the buried oxide layer formed by the implanted oxygen, the oxidation processing of the substrate is carried out in a high temperature oxygen atmosphere.

Abstract: An interlevel dielectric and a method for making same wherein boron is introduced into the dielectric though an implantation process. During the implantation process, either the boron-10 or the boron-11 boron isotope may be selected and introduced into the dielectric. Boron is introduced to make the dielectric flow at lower temperatures. Selectively implanting boron-10 or boron-11 during implantation, as opposed to buying boron comprising a specific boron isotope from a supplier and introducing boron during CVD, lowers the production costs. Furthermore, by introducing boron into the dielectric during the implantation process as opposed to during deposition of the dielectric during a CVD process, the dielectric layer is free of boron bumps. Boron-bearing dielectrics can be made to made to flow at lower temperatures than dielectrics which do not contain boron.

Abstract: A process for fabricating a bipolar transistor on a silicon-on-insulator substrate which includes etching a bipolar transistor area into the substrate, wherein the bipolar transistor area has substantially vertical sidewalls and a bottom, and forming a buried collector in bottom of the bipolar transistor area. Polysilicon sidewalls are formed adjacent to the vertical sidewalls in the bipolar transistor area, wherein the polysilicon sidewalls are connected to the buried collector. The polysilicon sidewalls are oxidized to form a layer of oxidized polysilicon. Oxide sidewalls are formed on the oxidized polysilicon sidewalls, and epitaxial silicon is formed to fill the bipolar transistor area. A base and an emitter are formed for the bipolar transistor, within the epitaxial barrier.

Abstract: A method for producing an electrically conductive element is provided in which an oxidation barrier is formed through modification of one or more layers which initially were receptive to oxidation.

Abstract: A method of forming a field oxide isolation region is described, in which a masking layer is formed over a silicon substrate. The masking layer is patterned to form an opening for the field oxide isolation region, whereby the remainder of the masking layer forms an implant mask. A conductivity-imparting dopant is implanted through the opening into the silicon substrate. Oxygen is implanted through the opening into the silicon substrate in multiple implantation steps. The implant mask is removed. The field oxide isolation region is formed in and on the silicon substrate, by annealing in a non-oxygen ambient. Alternately, the field oxide isolation region is formed by annealing in oxygen, simultaneously forming a gate oxide in the region between the field oxide isolation regions.

Abstract: Oxygen ion is implanted into a silicon substrate to remain a silicon layer on a surface of the silicon substrate. In this state, a silicon oxide layer is formed under the silicon layer. Silicon oxide particles are formed and remained in the residual silicon layer. While maintaining this state, the silicon substrate is heated to a predetermined temperature not less than 1300.degree. C. Alternatively, the silicon substrate is heated at a high temperature-rise rate to 900-1100.degree. C., and thereafter is heated at a low temperature-rise rate to the temperature not less than 1300.degree. C. The silicon substrate is held at the predetermined temperature not less than 1300.degree. C. for a predetermined time, whereby crystallinity of the residual silicon layer is restored.

Abstract: An isolation method in which an isolation ring is formed to isolate a semiconductor device from other semiconductor devices on a common substrate. The method is suitable for isolating bipolar devices from CMOS or other devices formed on the same substrate and for preventing base current from being injected into the substrate. The method starts with a substrate having a buried sub-collector and a first isolation region that surrounds the portion of the surface to contain the semiconductor device. The first isolation region extends only part of the distance from the surface towards the buried sub-collector. Layers of polysilicon and dual-tone resist are applied, and a first mask is used with an opaque area aligned over the portion of the surface to contain the semiconductor device. The edge of the opaque region terminates above the first isolation region. After exposure, the properties of the dual-tone resist allow a narrow sub-minimum width trench to be removed from the resist to define an isolation ring.

Abstract: The present invention discloses a method for manufacturing 3-D transistors with high electrostatic discharge (ESD) reliability. Pad oxide layers are on a silicon substrate and a thick field oxide is on the silicon substrate between the pad oxide layer. An oxygen amorphized region is formed in the substrate by using an ion implantation having oxygen ions as dopants and the field oxide as a hard mask. A high-temperature thermal annealing is implemented to convert the oxygen amorphized region into an oxygen implant-induced oxide regions. Then, the pad oxide layers and the field oxide are removed to form a field oxide region on the substrate and silicon islands on the oxygen implant-induced oxide regions. A thin gate oxide is deposited on the surface of the substrate and the silicon islands to seal the silicon islands. Finally, PMOSFETs are formed on the silicon islands and bulk NMOSFET buffers are formed on the field oxide region of the substrate.

Abstract: A method for forming field isolation regions in multilayer semiconductor devices comprises the steps of masking active regions of the substrate, forming porous silicon in the exposed field isolation regions, removing the mask and oxidizing the substrate. A light ion impurity implant is used to create pores in the substrate. Substrate oxidation proceeds by rapid thermal annealing because the increased surface area of the pores and the high reactivity of unsaturated bonds on these surfaces provides for enhanced oxidation.

Abstract: In a method of forming a II-VI compound semiconductor thin film on an InP substrate, a layer of III-V compound semiconductor mixed crystal is first formed on the InP substrate. The desorption rate of a group V element constituting the III-V compound semiconductor mixed crystal at a decomposition temperature of a native oxide layer formed on a surface of the III-V compound semiconductor mixed crystal layer is lower than a desorption rate of P of the InP substrate at a decomposition temperature of a native oxide layer formed on a surface of the InP substrate. A II-VI compound semiconductor thin film layer is formed on the first III-V compound semiconductor mixed crystal layer.