Abstract: According to one embodiment, a structure comprises a substrate and a field oxide region, where the field oxide region has a top surface, and where the top surface of the field oxide region comprises substantially no cavities caused by lateral etching. The structure further comprises a trench situated in the substrate, where the trench has a first sidewall and a second sidewall in the substrate, and where the trench is situated directly underneath the field oxide region. According to this embodiment, the trench is used as a deep trench isolation region in the substrate and is typically filled with polysilicon. A thermally grown oxide liner is situated on the first and the second sidewalls of the trench, where the oxide liner is formed after removal of a hard mask. The hard mask may be densified TEOS oxide or HDP oxide and may be removed in an anisotropic dry etch process.

Abstract: In accordance with an aspect of the invention, a method of forming a trench isolation region includes forming a trench within a substrate. A silanol layer is formed to partially fill the trench and then converted, at least some of the silanol, to a compound including at least one of SiOn and RSiOn, where R includes an organic group. An electrically insulative material is formed over the converted silanol to fill the trench. In another aspect of the invention, a method of forming a trench isolation region includes forming a trench within a substrate. A first layer of at least one of Si(OH)x and (CH3)ySi(OH)4?y is formed to partially fill the trench. At least some of the Si(OH)x if present is converted to SiO2 and at least some of (CH3)ySi(OH)4?y if present is converted to (CH3)xSiO2?x. Next, a layer of an electrically insulative material is formed to fill the trench.

Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.

Abstract: A method for forming a device isolation film of a semiconductor device, wherein an annealing process is performed on the oxide film using NH3 prior to the deposition of a liner nitride film and after the deposition of a thermal oxide film on a sidewall of a trench to nitridate the oxide film is disclosed.

Abstract: A metal film containing a metal is formed on a silicon layer, and then a surface portion of the silicon layer and the metal film are oxidized so as to form a silicon oxide film containing the metal in a surface portion of the silicon layer.

Abstract: Disclosed is a shallow trench isolation (STI) structure and methods of manufacturing the same. The methods eliminate the requirement for design size adjustments (DSA) in manufacturing the STI structure. Further disclosed is an STI trench liner and methods for the formation thereof by growing a thin oxide layer on shallow isolation trench surfaces while preventing oxide formation on adjacent nitride surfaces, followed by the deposition of, and oxide growth upon, a polysilicon layer.

Abstract: Provided is a method of semiconductor device fabrication capable of rounding the sharp edge portions of trenches so as to form device isolation regions having high electrical reliability. A semiconductor substrate comprising a lattice-strain relaxed silicon germanium layer, a silicon germanium layer, and a lattice strained silicon layer formed in this order of mention onto a silicon substrate is used, while trenches are formed in the portions for device isolation regions of the semiconductor substrate by etching. Then, a silicon film is deposited on the entirety of the exposed surface, and the deposited silicon film is dry-oxidized so as to form a silicon dioxide film. As a result, the edge portions of the trenches are rounded.

Abstract: A process gas consisting of one of N2, N2O or a mixture thereof is converted to a plasma and then a surface of a copper wiring layer is exposed to the plasma of the process gas, whereby a surface portion of the copper wiring layer is reformed and made into a copper diffusion preventing barrier. According to this method, a noble semiconductor device can be provided having increased operational speed and less copper diffusion.

Abstract: In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally spaced from the diffusion region. The conductive line is preferably formed relative to and within isolation oxide which separates substrate active areas. The conductive line is subsequently interconnected with the diffusion region. According to another preferred implementation, an oxide isolation grid is formed within semiconductive material. Conductive material is formed within the oxide isolation grid to form a conductive grid therein. Selected portions of the conductive grid are then removed to define interconnect lines within the oxide isolation grid. According to another preferred implementation, a plurality of oxide isolation regions are formed over a semiconductive substrate.

Abstract: A method and device are provided for shallow trench isolation for a silicon wafer containing silicon-germanium. In one example, the method comprises forming a trench region in a silicon-germanium layer of a semiconductor substrate containing a single crystal silicon-germanium layer on the surface; forming a first single crystal silicon layer in the trench region and an active region; oxidizing the first single crystal silicon layer; forming a first thermal oxide layer on the surface of the first single crystal silicon layer; forming a device isolation region; embedding an insulator in the trench region; and forming a device in an active region over the single crystal silicon-germanium layer separated by the device isolation region, wherein the step of forming the device in the active region further includes forming a doped region of a depth to reach within the single crystal silicon-germanium layer below the first single crystal silicon layer.

Abstract: A method of controlling the top width of a deep trench. A conductive layer is formed on the trench over a substrate of polysilicon with a recessed structure. An additional layer of amorphous silicon (?-Si) is deposited onto the polysilicon. After subsequent oxidation, the amorphous silicon is converted to SiO2. According to the invention, the top width of a deep trench is controlled, protecting bit lines from sub-threshold leakage.

Abstract: In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally spaced from the diffusion region. The conductive line is preferably formed relative to and within isolation oxide which separates substrate active areas. The conductive line is subsequently interconnected with the diffusion region. According to another preferred implementation, an oxide isolation grid is formed within semiconductive material. Conductive material is formed within the oxide isolation grid to form a conductive grid therein. Selected portions of the conductive grid are then removed to define interconnect lines within the oxide isolation grid. According to another preferred implementation, a plurality of oxide isolation regions are formed over a semiconductive substrate.

Abstract: A mask (4) for forming active regions is formed on a surface portion of a Si layer (2) serving as a semiconductor region with a thermal oxide film (3) interposed therebetween. Dummy sidewalls (8) are formed over the side surfaces of the mask (4) for forming active regions. Then, etching is performed by using the mask (4) for forming active regions and the dummy sidewalls (8) as a mask to form trenches (9) each defining the side surfaces of the Si layer (2). Thereafter, each of the trenches (9) is filled with a plasma CVD oxide film (11), which is polished till the dummy sidewalls (8) are exposed at the surface. By removing the dummy sidewalls (8), oxidation is performed with the upper-surface edge portions of the Si layer (2) being exposed. This allows the upper-surface edge portions of the Si layer (2) to be oxidized without involving the oxidation of the lower-surface edge portions of the Si layer (2).

Abstract: A trench isolation in a semiconductor device, and a method for fabricating the same, includes: forming a trench having inner sidewalls for device isolation in a silicon substrate; forming an oxide layer on a surface of the silicon substrate that forms the inner sidewalls of the trench; supplying healing elements to the silicon substrate to remove dangling bonds; and filling the trench with a device isolation layer, thereby forming the trench isolation without dangling bonds causing electrical charge traps.

Abstract: In one aspect, the invention encompasses a method of forming a polished material. A substrate is provided and an elevational step is provided relative to the substrate. The elevational step has an uppermost surface. A material is formed beside the elevational step. The material extends to above the elevational step uppermost surface and has lower and upper layers. The lower layer polishes at slower rate than the upper layer under common polishing conditions. The lower layer joins the upper layer at an interface. The material is polished down to about the elevational level of the elevational step uppermost surface utilizing the common polishing conditions. In another aspect, the invention encompasses a method of forming an isolation region. A substrate is provided. The substrate has an opening extending therein and a surface proximate the opening. A material is formed within the opening. The material extends to above the substrate surface, and comprises a lower layer and an upper layer.

Abstract: A method of producing semiconductor devices is provided, which makes it possible to bury a silicon oxide without shape deterioration in device isolation trenches. The method comprises the steps of: forming an etching resistive mask over a semiconductor substrate; etching the semiconductor substrate through an opening in the etching resistive mask to form a device isolation trench; forming a coat of a silazane perhydride polymer solution over the semiconductor substrate having the device isolation trench formed therein; vaporizing a solvent from the coat and then subjecting the coat to chemical reaction to form a film of silicon oxide; removing said film of the silicon oxide leaving a residue inside said device isolation trench; and heating said silicon oxide left in said device isolation trench for densification.

Abstract: A method of making a semiconductor structure includes sealing a gate layer by wet oxidation. The gate layer is on a substrate containing isolation regions. Semiconductor devices prepared from the semiconductor structure exhibits reduced inverse narrow width effects.

Abstract: The filling of sub-0.25 &mgr;m trenches with dielectric material may lead to the formation of a void. Typically, the void may be closed by oxidation. When the trench includes non-oxidizable sidewall portions, insufficient closure may result. Therefore, an oxidizable spacer layer is conformally deposited prior to depositing the bulk dielectric, so that the sidewalls of the trench may be oxidized along the entire depth of the trench, thereby allowing the complete closure of the void.

Abstract: The present invention is related to an integrated circuit having an SiC etch stop layer fabricated using a method for removal of silicon carbide layers and in particular amorphous SiC of a substrate comprising the steps of: converting at least partly said exposed part of said carbide-silicon layer into an oxide-silicon layer by exposing said carbide-silicon layer to an oxygen containing plasma; and removing said oxide-silicon layer from said substrate.

Abstract: A method and structure to form shallow trench isolation regions without trench oxide grooving is provided. In particular, a method includes a two-step oxide process in which an oxide liner lines the inside surface of a trench and the trench is filled with a bulk oxide layer, preferably using a high density plasma chemical vapor deposition (HDP-CVD) process. The oxide liner and the bulk oxide layer are formed to have similar etch rates. Thus, when etching the oxide liner and the bulk oxide layer between stack structures, a common dielectric top surface is formed that is substantially planar and without grooves.

Abstract: A flash memory having a charge-storage dielectric layer and a method for forming the same are provided. According to one embodiment, charge-storage dielectric layers are formed over the first and second active regions. The charge-storage layer over the first active region is not connected to the charge-storage layer over the second active region. A gate line overlies the charge-storage layer and extends across the first and second active regions and the isolation region. The charge-storage layer can be formed only where a gate line intersects an active region of a semiconductor substrate, not on an isolation region. Thus, undesirable influence or disturbance from adjacent memory cells can be avoided.

Abstract: A semiconductor device and a method for releasing stress exerted while fabricating the semiconductor device. The method for releasing the stress, includes forming a stack layer deposited on a semiconductor sequentially with a gate oxide layer, a poly-silicon layer, a tungsten layer, and a hard mask; selectively oxidizing, wherein only the poly-silicon layer of the stack layer is oxidized; heat treating for releasing stress exerted during the selective oxidation process; and forming a gate sealing nitride layer on the stack layer heat-treated.

Abstract: A super-self-aligned (SSA) structure and manufacturing process uses a single photomasking layer to define critical features and dimensions of a trench-gated vertical power DMOSFET. The single critical mask determines the trench surface dimension, the silicon source-body mesa width between trenches, and the dimensions and location of the silicon mesa contact. The contact is self-aligned to the trench, eliminating the limitation imposed by contact-to-trench mask alignment in conventional trench DMOS devices needed to avoid process-induced gate-to-source shorts. Oxide step height above the silicon surface is also reduced avoiding metal step coverage problems. Poly gate bus step height is also reduced. Other features described include polysilicon diode formation, controlling the location of drain-body diode breakdown, reducing gate-to-drain overlap capacitance, and utilizing low-thermal budget processing techniques.

Abstract: A semiconductor device having a trench isolation structure which has a high insulating characteristic, is suitable for miniaturizing a semiconductor device, and prevents a leakage current, as well as a method of manufacturing the semiconductor device. A small-density polysilicon film is formed between a semiconductor substrate and a CVD silicon oxide film in the area within a trench where a trench isolation structure is to be formed. Mechanical stress that develops between the semiconductor substrate and the CVD silicon oxide film during heat treatment is mitigated by changing the crystalline structure of the polysilicon film.

Abstract: Provided is a method of semiconductor device fabrication capable of rounding the sharp edge portions of trenches so as to form device isolation regions having high electrical reliability. A semiconductor substrate comprising a lattice-strain relaxed silicon germanium layer, a silicon germanium layer, and a lattice strained silicon layer formed in this order of mention onto a silicon substrate is used, while trenches are formed in the portions for device isolation regions of the semiconductor substrate by etching. Then, a silicon film is deposited on the entirety of the exposed surface, and the deposited silicon film is dry-oxidized so as to form a silicon dioxide film. As a result, the edge portions of the trenches are rounded.

Abstract: In fabricating a shallow trench isolation (STI), a silicon oxide layer, a silicon nitride layer and a moat pattern is sequentially deposited on a silicon substrate. Next, the silicon nitride layer and the silicon oxide layer is etched using the moat pattern as a mask to thereby partially expose the silicon substrate and then the moat pattern is removed. Ion implanting process is performed into the silicon substrate using the silicon nitride layer as a mask, adjusting a dose of an implanted ion and an implant energy, to thereby form an isolation region. And then, the isolation region to form a porous silicon and to form an air gap in the porous silicon is anodized, wherein a porosity of the porous silicon is determined by the dose of the implanted ion. Next, the porous silicon is oxidized through an oxidation process. Finally, the silicon nitride layer is removed.

Abstract: A magnetic random access memory module includes a magnetic memory array. A permeable metal layer extends over a first side of the magnetic memory array. An electrically insulating layer is disposed between the permeable metal layer and the magnetic memory array.

Abstract: In a method of producing a trench insulation in a silicon substrate a first silicon-oxide layer is deposited on a front surface of a sequence of layers including the silicon substrate. Then the first silicon-oxide layer is structured so as to define a mask for a subsequent production of a trench. A trench is etched with a predetermined depth in the silicon substrate making use of the mask and filled with a silicon oxide. Then a first polysilicon layer is conformally deposited on the first silicon-oxide layer and on the oxide-filled trench. The first polysilicon layer is removed in such a way that a polysilicon cover remains on the oxide-filled trench, and the first silicon-oxide layer is removed.

Abstract: In accordance with an aspect of the invention, a method of forming a trench isolation region includes forming a trench within a substrate. A silanol layer is formed to partially fill the trench and then converted, at least some of the silanol, to a compound including at least one of SiOn and RSiOn, where R includes an organic group. An electrically insulative material is formed over the converted silanol to fill the trench. In another aspect of the invention, a method of forming a trench isolation region includes forming a trench within a substrate. A first layer of at least one of Si(OH)x and (CH3)ySi(OH)4-y is formed to partially fill the trench. At least some of the Si(OH)x if present is converted to SiO2 and at least some of (CH3)ySi(OH)4-y if present is converted to (CH3)xSiO2-x. Next, a layer of an electrically insulative material is formed to fill the trench.

Abstract: A method of providing a thick thermal oxide in trench isolation is disclosed, wherein an additional polysilicon layer, blanket deposited in a chemical vapor deposition process, is employed. The polysilicon layer is subsequently, in a thermal oxidation process, transformed into a thick thermal liner oxide. Advantageously, forming the thick liner oxide by oxidation of the additional polysilicon layer reduces the formation of a “bird's beak” and, thus, reduces the introduction of mechanical stress into the semiconductor device. Due to the employment of a thick thermal liner oxide, the formation of divots is also minimized. Thus, the device stability and reliability is improved.

Abstract: A semiconductor device is provided having at least two neighboring transistors and an STI region therebetween. The STI region is provided with a voltage bias to minimize subthreshold leakage current between the neighboring transistors. A method of fabricating such a semiconductor device is also provided.

Abstract: The filling of sub-0.25 &mgr;m trenches with dielectric material may lead to the formation of a void. Typically, the void may be closed by oxidation. When the trench includes non-oxidizable sidewall portions, insufficient closure may result. Therefore, an oxidizable spacer layer is conformally deposited prior to depositing the bulk dielectric, so that the sidewalls of the trench may be oxidized along the entire depth of the trench, thereby allowing the complete closure of the void.

Abstract: A method of making a semiconductor structure includes sealing a gate layer by wet oxidation. The gate layer is on a substrate containing isolation regions. Semiconductor devices prepared from the semiconductor structure exhibits reduced inverse narrow width effects.

Abstract: Disclosed is a submount integrated photodiode package with an improved metal layer configuration and laser diode package using the same. In particular, a unitary laser diode of the invention provides a light receiving area overlying a semiconductor substrate to correspond to a radiation area of light emitted from a laser diode so as to reduce chip size in respect to a conventional one while maintaining a monitoring current identical to the conventional one as well as improve heat-radiating features. The invention provides a unitary laser diode package which comprises a light receiving area overlying a semiconductor substrate and having the same configuration as a radiation area of emission light from the laser diode and a metal layer adjacent to the light receiving area.

Abstract: The present disclosure relates to a method for forming a device isolation layer of a semiconductor device by a shallow trench isolation (STI). In the disclosed methods, after a nitride layer is removed from the silicon substrate, an amorphous silicon layer is deposited thereon and is oxidized to form an amorphous spacer at a side wall of the device isolation layer by etching the amorphous silicon layer.

Abstract: After a trench is formed into a substrate, a polysilicon layer is formed on sidewalls and a bottom of the trench. A thermal oxidation is performed on the polysilicon layer such that a polysilicon oxide layer is formed thereon. Then, a portion of the polysilicon oxide layer is removed such that the polysilicon layer is exposed on the bottom of the trench while the sidewalls of the trench are still covered by the polysilicon oxide layer. A TEOS-ozone oxide layer is deposited on the substrate to fill the trench. Since the bottom of the trench has a better condition for the deposition of TEOS-ozone oxide layer than that of the sidewalls, a gap fill quality can be enhanced.

Abstract: A method for estimating molecular nitrogen implantation dosage. The semiconductor wafers are first implanted with various concentration of molecular nitrogen. After implantation, the implanted wafers and a non-implanted wafer are subjected to thermal process to grow oxide layer. The thickness of oxide layer on the wafers with various implantation dosage is measured. Because implanted nitrogen on the wafers suppresses the growth of oxide layer, a suppression ratio is computed from the difference in thickness of the oxide layer between the implanted and non-implanted semiconductor wafers to stand for the thickness variation. Then, a relation between the suppression ratio and the dosages of molecular nitrogen is built. A molecular nitrogen dosage needed to grow a predetermined thickness of oxide layer on a process wafer is computed by inputting the predetermined thickness into the relation.

Abstract: In one aspect, the invention encompasses a method of forming a polished material. A substrate is provided and an elevational step is provided relative to the substrate. The elevational step has an uppermost surface. A material is formed beside the elevational step. The material extends to above the elevational step uppermost surface and has lower and upper layers. The lower layer polishes at slower rate than the upper layer under common polishing conditions. The lower layer joins the upper layer at an interface. The material is polished down to about the elevational level of the elevational step uppermost surface utilizing the common polishing conditions. In another aspect, the invention encompasses a method of forming an isolation region. A substrate is provided. The substrate has an opening extending therein and a surface proximate the opening. A material is formed within the opening. The material extends to above the substrate surface, and comprises a lower layer and an upper layer.

Abstract: First, a trench of a semiconductor substrate is filled with a polysilicon film deposited on the surface of the semiconductor substrate. A selective thin film having etching selectivity with respect to the polysilicon film is formed on the polysilicon film. Then, the selective thin film is etched (etched back) so that a part of the selective thin film remains in a depression of the polysilicon film, as a self-aligning mask. The polysilicon film is further etched with the self-aligning mask, thereby forming a polysilicon embedded layer in the trench with a flat surface.

Abstract: A method of forming a dielectric structure for a flash memory cell includes forming a first layer of silicon dioxide, forming a layer of silicon nitride on the first layer of silicon dioxide, and pretreating the silicon nitride layer. Pretreatment of the silicon nitride layer includes nitridation. The method further includes depositing a second layer of silicon dioxide on the pretreated silicon nitride layer. Nitridation of the silicon nitride can occur in a batch process or in a single wafer tool, such as a single wafer rapid thermal anneal (RTA) tool. The nitriding pretreatment of the nitride layer improves the integrity of the ONO structure and enables the second layer of silicon dioxide to be deposited rather than thermally grown. Because the nitride layer undergoes less change after deposition of the second layer of silicon dioxide, the present method improves the overall reliability of the ONO structure.

Abstract: A high-dielectric capacitor is formed by using a Ru lower electrode having a (002)-oriented principal surface, by depositing thereon a Ta2O5 film such that the Ta2O5 film has a (100)-principal surface.

Abstract: A method for forming an isolation trench in a silicon or silicon-on-insulator substrate is described in which a trench is formed in the semiconductor structure (containing a multiple layer structure of Si, SiO2, and SiN layers) and an undoped polysilicon layer is deposited on the bottom and sidewalls of the trench and on the surface of the region adjacent to the trench. A substantial portion of the trench is left unfilled by the undoped polysilicon layer deposited. The polysilicon layer is thermally oxidized to form a thermal oxide that fills the trench and thereby avoids forming a birds-beak formation of the thermal oxide above the sidewalls of the trench. The isolation structure may be planarized by either removing the polysilicon layer from the region adjacent to the trench before oxidation or later removing the oxide from the SiN layer and adjusting height of the oxide in the trench.

Abstract: The present invention is related to an integrated circuit having an SiC etch stop layer fabricated using a method for removal of silicon carbide layers and in particular amorphous SiC of a substrate comprising the steps of: converting at least partly said exposed part of said carbide-silicon layer into an oxide-silicon layer by exposing said carbide-silicon layer to an oxygen containing plasma; and removing said oxide-silicon layer from said substrate.

Abstract: The present invention is related to a method for removal of silicon carbide layers and in particular amorphous SiC of a substrate. Initially, the exposed part of a carbide-silicon layer is at least partly converted into an oxide-silicon layer by exposing the carbide-silicon layer to an oxygen containing plasma. The oxide-silicon layer is then removed from the substrate.

Abstract: In order to close or cover micropipes, which generally are formed in SiC bulk material, one sputters or deposits or grows a layer of silicon on the backside of a micromachined silicon carbide diaphragm. This is followed by an oxidation process. In this approach, the deposition of silicon reduces or completely plugs the micropipes. After the silicon deposition, the wafer is oxidized which completely closes the otherwise reduced micropipes. Since the oxidation process is significantly faster than silicon and SiC, it is significantly easier to close even the largest of micropipes. The thickness of the silicon, the processing for depositing or growing silicon, and the process of oxidation can be adjusted to close micropipes in different SiC materials.

Abstract: In accordance with an aspect of the invention, a method of forming a trench isolation region includes forming a trench within a substrate. A silanol layer is formed to partially fill the trench and then converted, at least some of the silanol, to a compound including at least one of SiOn and RSiOn, where R includes an organic group. An electrically insulative material is formed over the converted silanol to fill the trench. In another aspect of the invention, a method of forming a trench isolation region includes forming a trench within a substrate. A first layer of at least one of Si(OH)x and (CH3)ySi(OH)4−y is formed to partially fill the trench. At least some of the Si(OH)x if present is converted to SiO2 and at least some of (CH3)ySi(OH)4−y if present is converted to (CH3)xSiO2−x. Next, a layer of an electrically insulative material is formed to fill the trench.

Abstract: A dual depth trench isolation structure formed between active devices and conductive well regions of same conductivity type which comprises a first inter-well isolation structure having a first isolation trench depth, a second inter-well isolation structure having a second isolation trench depth which combine to form a dual depth trench containing the dual depth trench isolation structure comprising the first inter-well isolation structure and the second inter-well isolation structure, with the dual depth trench isolation interposed at the boundary of an n-well conductive region and a p-well conductive region, a first intra-well isolation structure having a first isolation trench depth, the first intra-well isolation structure interposed between a pair of p-channel transistors residing in the n-well region, and a second intra-well isolation structure having a second isolation trench depth, the second intra-well isolation structure interposed between a pair of n-channel transistors residing in the p-well regio

Abstract: A metal film containing a metal is formed on a silicon layer, and then a surface portion of the silicon layer and the metal film are oxidized so as to form a silicon oxide film containing the metal in a surface portion of the silicon layer.

Abstract: A process for fabricating an integrated circuit sensor/actuator is described. High aspect ratio deep silicon beams are formed by a process of deep trench etch and silicon undercut release etch by using oxide spacers to protect the silicon beam sidewalls during release etch. An oxide layer is then formed, followed by deposition of a controlled thickness of polysilicon which is then thermally oxidized. The polysilicon layer inside the trenches gets fully oxidized resulting in void-free trench isolation. This process creates a silicon island or beam on three sides leaving the third side for interfacing with the sensor/actuator beams. The sensor/actuator is formed by a similar process of deep trench etch and release etch process on the same substrate. These suspended beams of the sensors and actuators are bridged with the silicon islands from the fourth side. The above process finally results in suspended silicon beams connected to electrically isolated silicon islands.

Abstract: After a trench is formed into a substrate, a polysilicon layer is formed on sidewalls and a bottom of the trench. A thermal oxidation is performed on the polysilicon layer such that a polysilicon oxide layer is formed thereon. Then, a portion of the polysilicon oxide layer is removed such that the polysilicon layer is exposed on the bottom of the trench while the sidewalls of the trench are still covered by the polysilicon oxide layer. A TEOS-ozone oxide layer is deposited on the substrate to fill the trench. Since the bottom of the trench has a better condition for the deposition of TEOS-ozone oxide layer than that of the sidewalls, a gap fill quality can be enhanced.