Conformal Insulator Formation Patents (Class 438/437)
  • Patent number: 11274369
    Abstract: A thin film deposition method with respect to a substrate including a pattern structure includes supplying RF power through a component disposed below a substrate, forming a potential on an exposed surface of the substrate exposed to a reaction space, moving the active species to the exposed surface in the reaction space using the potential, and forming a thin film including active species component on the exposed surface of the substrate.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: March 15, 2022
    Assignee: ASM IP Holding B.V.
    Inventors: KiChul Um, JeungHoon Han, DooHan Kim, YongGyu Han, TaeHee Yoo, WanGyu Lim, DongHyun Ko
  • Patent number: 10896846
    Abstract: Methods for forming conductive regions of a metallization network with reduced leakage current and capacitance are described. Aspects of the invention include forming a trench in a dielectric material on the substrate, forming a first liner layer in a first portion of the trench, forming a second liner layer in a second portion of the trench, and forming a conductive material over the second liner layer in the trench.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: January 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Raghuveer Patlolla, Cornelius Brown Peethala, Chih-Chao Yang
  • Patent number: 10707085
    Abstract: A method of manufacturing a semiconductor device includes: forming an isolation region comprising a dielectric material on a substrate; forming a recess in the isolation region, wherein a thickness of the isolation region is reduced but greater than zero in the recess; forming a fill layer or layer stack including at least one of a semiconductor or metal on the isolation region and which conforms to the recess; forming a dishing prevention layer or layer stack on the fill layer or layer stack and which conforms to the recess; planarizing the dishing prevention layer or layer stack and the fill layer or layer stack to confine the dishing prevention layer or layer stack and the fill layer or layer stack to the recess, wherein the planarizing stops on the isolation region outside the recess; and forming one or more electrical contacts to the fill layer or layer stack confined to the recess.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: July 7, 2020
    Assignee: Infineon Technologies Austria AG
    Inventor: Alim Karmous
  • Patent number: 10373806
    Abstract: Provided are apparatuses and methods for performing deposition and etch processes in an integrated tool. An apparatus may include a plasma processing chamber that is a capacitively-coupled plasma reactor, and the plasma processing chamber can include a showerhead that includes a top electrode and a pedestal that includes a bottom electrode. The apparatus may be configured with an RF hardware configuration so that an RF generator may power the top electrode in a deposition mode and power the bottom electrode in an etch mode. In some implementations, the apparatus can include one or more switches so that at least an HFRF generator is electrically connected to the showerhead in a deposition mode, and the HFRF generator and an LFRF generator is electrically connected to the pedestal and the showerhead is grounded in the etch mode.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: August 6, 2019
    Assignee: Lam Research Corporation
    Inventors: Akhil Singhal, Patrick A. Van Cleemput, Martin E. Freeborn, Bart J. van Schravendijk
  • Patent number: 10204982
    Abstract: A method for forming a semiconductor device includes forming a mask layer on a stressed semiconductor layer of a stressed, semiconductor-on-insulator wafer. An isolation trench bounding the stressed semiconductor layer is formed. The isolation trench extends through the mask layer and into the SOI wafer past an oxide layer thereof. A dielectric body is formed in the isolation trench. A relaxation reduction liner is formed on the dielectric body and on an adjacent sidewall of the stressed semiconductor layer. The mask layer on the stressed semiconductor layer is removed.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: February 12, 2019
    Assignee: STMicroelectronics, Inc.
    Inventors: Pierre Morin, Qing Liu, Nicolas Loubet
  • Patent number: 9960033
    Abstract: A method of filling recesses or grooves on a patterned surface with a layer of film, by combining depositing a film by PEALD/PPECVD on the patterned surface and etching the film, wherein the deposition and the etching are separately controlled, and wherein the conditions for deposition can be controlled by controlling RF power.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: May 1, 2018
    Assignee: ASM IP HOLDING B.V.
    Inventor: Toshihisa Nozawa
  • Patent number: 9847247
    Abstract: A method for filling gaps of semiconductor device and a semiconductor device with insulation gaps formed by the same are provided. First, a silicon substrate with plural protruding portions is provided, and the protruding portions are spaced apart from each other by gaps with predetermined depths. A nitride-containing layer is formed above the silicon substrate for covering the protruding portions and surfaces of the gaps as a liner nitride. Then, an amorphous silicon layer is formed on the nitride-containing layer. An insulating layer is formed on the amorphous silicon layer, and the gaps are filled up with the insulating layer.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: December 19, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ping-Wei Huang, Keng-Jen Lin, Yi-Hui Lin, Yu-Ren Wang
  • Patent number: 9543162
    Abstract: A substrate processing method includes a phosphoric acid processing step of supplying a phosphoric acid aqueous solution, which contains silicon and has a silicon concentration lower than a saturation concentration, to a front surface of a substrate, a liquid volume reducing step of reducing a volume of the phosphoric acid aqueous solution on the substrate, after the phosphoric acid processing step, and a rinse replacing step of supplying a rinse liquid having a temperature lower than that of the phosphoric acid aqueous solution supplied to the front surface of the substrate in the phosphoric acid processing step to the front surface of the substrate covered with the phosphoric acid aqueous solution at least partially, after the liquid volume reducing step.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: January 10, 2017
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Taiki Hinode, Takashi Ota, Kazuhide Saito
  • Patent number: 9335276
    Abstract: A method is disclosed evaluating a silicon layer crystallized by irradiation with pulses form an excimer-laser. The crystallization produces periodic features on the crystallized layer dependent on the number of and energy density ED in the pulses to which the layer has been exposed. An area of the layer is illuminated with light. A microscope image of the illuminated area is made from light diffracted from the illuminated are by the periodic features. The microscope image includes corresponding periodic features. The ED is determined from a measure of the contrast of the periodic features in the microscope image.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: May 10, 2016
    Assignee: Coherent LaserSystems GmbH & Co. KG
    Inventor: Paul Van Der Wilt
  • Patent number: 9287374
    Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes an active region, a device isolation film, a first liner nitride film disposed over a lower portion of a sidewall of the active region, and a second liner nitride film disposed over an upper portion of the sidewall of the active region and having a higher density of nitrogen than a density of nitrogen in the first liner nitride film.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: March 15, 2016
    Assignee: SK HYNIX INC.
    Inventors: Yu Jun Lee, Kyoung Chul Jang
  • Patent number: 9287159
    Abstract: A device isolation layer of the memory device includes a first insulation layer in a lower portion of a device isolation trench, a second insulation layer in an upper portion of the device isolation trench and a separation layer between the first insulation layer and the second insulation layer. First and second conductive fillers are in the first and second insulation layers and are separated by the separation layer.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: March 15, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Chul Kim, Jae-Seok Kim, Chan-Hong Park
  • Patent number: 9276003
    Abstract: A semiconductor device includes a substrate with an active pattern, the active pattern having a first extension portion extending in a first direction substantially parallel to a top surface of the substrate, a second extension portion extending from a first end of the first extension portion in a third direction oriented obliquely to the first direction, a third extension portion extending from a second end of the first extension portion in a direction opposed to the third direction, a first projection portion protruding from the second extension portion in a direction opposed to the first direction, the first projection portion being spaced apart from the first extension portion, and a second projection portion protruding from the third extension portion in the first direction, the second projection portion being spaced apart from the first extension portion.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: March 1, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jea-Hyun Kim, Kyong-Seok Song, Sung-Hee Han
  • Patent number: 9196762
    Abstract: Certain embodiments provide a method for manufacturing a solid-state imaging device, including thinning a semiconductor substrate, forming a plurality of masking patterns, and forming a groove having inclined surfaces that are inclined relative to a front surface of the semiconductor substrate at a back surface of the semiconductor substrate. A plurality of light receiving sections are provided in a lattice pattern at the front surface of the semiconductor substrate to be thinned. A wiring layer including metal wirings is provided on the front surface of the semiconductor substrate to be thinned. The plurality of masking patterns are arranged in a lattice pattern on the back surface of the thinned semiconductor substrate. The groove is formed by etching the semiconductor substrate between the masking patterns using an etchant having an anisotropic etching property.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: November 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Jun Saito
  • Patent number: 9190494
    Abstract: Disclosed are methods, systems and devices, including a system, having a memory device. In some embodiments, the memory device includes a plurality of fin field-effect transistors disposed in rows, a plurality of insulating fins each disposed between the rows, and a plurality of memory elements each coupled to a terminal of a fin field-effect transistor among the plurality of fin field-effect transistors.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: November 17, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 9136270
    Abstract: A device isolation layer of the memory device includes a first insulation layer in a lower portion of a device isolation trench, a second insulation layer in an upper portion of the device isolation trench and a separation layer between the first insulation layer and the second insulation layer. First and second conductive fillers are in the first and second insulation layers and are separated by the separation layer.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: September 15, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Chul Kim, Jae-Seok Kim, Chan-Hong Park
  • Patent number: 9112008
    Abstract: A MEMS device and a forming method thereof are provided. The MEMS device includes a semiconductor substrate with a well region formed therein. A source region, a drain region and a channel region are formed in the well region. The source region and the drain region are covered by an isolating layer, and the channel region is covered by a gate dielectric layer. The device further includes a gate electrode layer which is disposed above the gate dielectric layer, with a gap disposed therebetween. The width of the gap corresponds to the width of the channel region. The MEMS can work well at high voltages with less leakage current.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: August 18, 2015
    Assignee: LEXVU OPTO MICROELECTRONICS TECHNOLOGY (SHANGHAI) LTD.
    Inventors: Jianhong Mao, Fengqin Han
  • Patent number: 9059243
    Abstract: Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Kangguo Cheng, Balasubramanian S. Haran, Ali Khakifirooz, Pranita Kulkarni, Arvind Kumar, Shom Ponoth
  • Patent number: 9040337
    Abstract: Provided are a stretchable electronic device and a method of manufacturing the same. The manufacturing method includes forming coil interconnection on a first substrate, forming a first stretchable insulating layer that covers the coil interconnection, forming a second substrate on the first stretchable insulating layer, separating the first substrate from the coiling interconnection and the first stretchable insulating layer, and forming a transistor on the coil interconnection.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 26, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Chan Woo Park, Jae Bon Koo, Sang Chul Lim, Ji-Young Oh, Soon-Won Jung
  • Patent number: 9034725
    Abstract: A method of forming a transistor is provided. An upper portion of a substrate is partially removed forming a trench. An isolation layer partially fills the trench, forming active patterns of the substrate. The isolation layer has a void therein. A photoresist pattern is formed on the active patterns and the isolation layer. The active patterns and the isolation layer are partially removed using the photoresist pattern as an etching mask, thus forming a recess. A plasma treatment process is performed, removing the photoresist pattern and filling the void. A gate insulation layer and a gate electrode fill the recess.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: May 19, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo-Whan Choi, Jung-Bong Yun, Chang-Won Choi
  • Patent number: 9034726
    Abstract: A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: May 19, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Chien Liu, Chia-Lung Chang, Jei-Ming Chen, Jui-Min Lee, Yuh-Min Lin
  • Publication number: 20150123239
    Abstract: One or more methods of forming shallow trench isolation (STI) and resulting semiconductor arraignments are provided. A method of forming STI includes forming a nitride liner in a first opening and second opening and recessing the nitride liner in the first opening and second opening while forming an oxide structure in the first opening and second opening, thus forming a first STI region in the first opening and a second STI region in the second opening. A semiconductor arraignment includes a first STI region in an active area and a second STI region in an isolation area, where a first recessed nitride layer height in the first STI region is different than a second recessed nitride layer height in the second STI region.
    Type: Application
    Filed: November 4, 2013
    Publication date: May 7, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ming-Hui Chen, Chuan-Ping Hou, Chih-Ho Tai
  • Publication number: 20150123240
    Abstract: A semiconductor device has a substrate including a semiconductor material of a first conductivity type. A first layer including a semiconductor material of a second conductivity type is formed in the substrate with a boundary between the first layer and the semiconductor material of the first conductivity type as a p-n junction. A vertical trench is formed through the first layer by anisotropic etch and extends at least to the boundary. The vertical trench has a rounded or polygonal shape with a depth less than 40 micrometers. An insulating material is deposited in the vertical trench. An insulating layer is formed over a sidewall of the vertical trench. The shallow vertical trench filled with insulating material increases breakdown voltage and reduces manufacturing time and complexity. The semiconductor device can be a discrete diode, transistor, rectifier, transient voltage suppressor, silicon controlled rectifier, and triode.
    Type: Application
    Filed: November 7, 2013
    Publication date: May 7, 2015
    Inventor: Addison R. Crockett
  • Publication number: 20150115397
    Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes an epitaxial layer and a dielectric material. The epitaxial layer is in a trench of the semiconductor and is peripherally enclosed thereby, in which the epitaxial layer is formed by performing etch and epitaxy processes. The etch and epitaxy process includes etching out a portion of a sidewall of the trench and a portion of a bottom surface of the trench and forming the epitaxial layer conformal to the remaining portion of the sidewall and the remaining portion of the bottom surface. The dielectric material is peripherally enclosed by the epitaxial layer.
    Type: Application
    Filed: October 24, 2013
    Publication date: April 30, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Hung CHENG, Cheng-Ta WU, Yeur-Luen TU, Chia-Shiung TSAI, Ru-Liang LEE, Tung-I LIN, Wei-Li CHEN
  • Patent number: 9012293
    Abstract: A method is provided for forming sandwich damascene resistors in MOL processes and the resulting devices. Embodiments include forming on a substrate a film stack including an interlayer dielectric (ILD), a first dielectric layer, and a sacrifice layer (SL); removing a portion of the SL and the first dielectric layer, forming a first cavity; conformally forming a layer of resistive material in the first cavity and over the SL; depositing a second dielectric layer over the layer of resistive material and filling the first cavity; and removing the second dielectric layer, the layer of resistive material not in the first cavity, and at least a partial depth of the SL.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: April 21, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Chang Yong Xiao, Roderick Miller, Jie Chen
  • Patent number: 9006080
    Abstract: An integrated circuit device incorporating a plurality of isolation trench structures configured for disparate applications and a method of forming the integrated circuit are disclosed. In an exemplary embodiment, a substrate having a first region and a second region is received. A first isolation trench is formed in the first region, and a second isolation trench is formed in the second region. A first liner layer is formed in the first isolation trench, and a second liner layer is formed in the second isolation trench. The second liner layer has a physical characteristic that is different from a corresponding physical characteristic of the first liner layer. An implantation procedure is performed on the second isolation trench and the second liner layer formed therein. The physical characteristic of the second liner layer may be selected to enhance an implantation depth or an implantation uniformity compared to the first liner layer.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Chou, Min-Feng Kao, Feng-Chi Hung, Shih Pei Chou, Jiech-Fun Lu, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 8980715
    Abstract: Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alfred Grill, Seth L. Knupp, Son V. Nguyen, Vamsi K. Paruchuri, Deepika Priyadarshini, Hosadurga K. Shobha
  • Patent number: 8981466
    Abstract: Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alfred Grill, Seth L. Knupp, Son V. Nguyen, Vamsi K. Paruchuri, Deepika Priyadarshini, Hosadurga K. Shobha
  • Publication number: 20150069571
    Abstract: According to a structure herein, a silicon substrate has an active device in the silicon substrate. A dielectric film is on the active device. An isolation trench is in the dielectric film surrounding the active device. The trench extends through the dielectric film and at least partially into the silicon substrate. A core is in the isolation trench. The core comprises material having thermal conductivity greater than silicon dioxide and electrical conductivity approximately equal to silicon dioxide.
    Type: Application
    Filed: September 11, 2013
    Publication date: March 12, 2015
    Applicant: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Qizhi Liu, Zhenzhen Ye, Yan Zhang
  • Patent number: 8975154
    Abstract: A method for producing at least one deep trench isolation in a semiconductor substrate including silicon and having a front side may include forming at least one cavity in the semiconductor substrate from the front side. The method may include conformally depositing dopant atoms on walls of the cavity, and forming, in the vicinity of the walls of the cavity, a silicon region doped with the dopant atoms. The method may further include filling the cavity with a filler material to form the at least one deep trench isolation.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: March 10, 2015
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Didier Dutartre, Zahra Aitfqirali-Guerry, Yves Campidelli, Denis Pellissier-Tanon
  • Patent number: 8969172
    Abstract: [Problem] To provide a method for forming an isolation structure having a low shrinkage percentage and a low tensile stress. [Means for Solving] A first polysilazane composition containing a porogen is cast on the surface of a substrate to form a coat, and then the coat is fired to form a porous siliceous film having a refractive index of 1.3 or less. Thereafter, the surface of the porous siliceous film is soaked with a second polysilazane composition, and then fired to form an isolation structure of a siliceous film having a refractive index of 1.4 or more.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: March 3, 2015
    Assignee: AZ Electronic Materials USA Corp.
    Inventors: Naoko Nakamoto, Katsuchika Suzuki, Shinji Sugahara, Tatsuro Nagahara
  • Patent number: 8962430
    Abstract: On a substrate formed of a first semiconductor layer, an insulating layer and a second semiconductor layer, a silicon oxide pad layer and a silicon nitride pad layer are deposited and patterned to define a mask. The mask is used to open a trench through the first semiconductor layer and insulating layer and into the second semiconductor layer. A dual liner of silicon dioxide and silicon nitride is conformally deposited within the trench. The trench is filled with silicon dioxide. A hydrofluoric acid etch removes the silicon nitride pad layer along with a portion of the conformal silicon nitride liner. A hot phosphoric acid etch removes the silicon oxide pad layer, a portion of the silicon oxide filling the trench and a portion of the conformal silicon nitride liner. The dual liner protects against substrate etch through at an edge of the trench between the first and second semiconductor layers.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: February 24, 2015
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: Qing Liu, Nicolas Loubet, Bruce Doris
  • Publication number: 20150048477
    Abstract: A semiconductor structure includes a surface having a plurality of portions and a dielectric material over the surface. The dielectric material includes an aspect ratio substantially equal to or greater than a predetermined value.
    Type: Application
    Filed: August 16, 2013
    Publication date: February 19, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: JIA-YOU TSAI, KUNG-WEI LEE
  • Patent number: 8941210
    Abstract: Semiconductor devices including a trench isolation layer are provided. The semiconductor device includes a substrate having a trench therein, a liner insulation layer that covers a bottom surface and sidewalls of the trench and includes micro trenches located at bottom inner corners of the liner insulation layer, a first isolating insulation layer filling the micro trenches and a lower region of the trench that are surrounded by the liner insulation layer, and a second isolating insulation layer filling the trench on the first isolating insulation layer. The liner insulation layer on sidewalls of an upper region of the trench having a thickness that gradually increases toward a bottom surface of the trench, and the liner insulation layer on sidewalls of the lower region of the trench having a thickness that is uniform. Related methods are also provided.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: January 27, 2015
    Assignee: SK Hynix Inc.
    Inventor: Tai Ho Kim
  • Patent number: 8940615
    Abstract: The present invention provides a method of forming an isolation structure. A substrate is provided, and a trench is formed in the substrate. Next, a semiconductor layer is formed on a surface of the trench. A nitridation is carried out to form a nitridation layer in the semiconductor layer. Lastly, an insulation layer is filled into the trench.
    Type: Grant
    Filed: September 9, 2012
    Date of Patent: January 27, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Te-Lin Sun, Chien-Liang Lin, Yu-Ren Wang
  • Publication number: 20150021702
    Abstract: A semiconductor structure with an improved shallow trench isolation (STI) region and method of fabrication is disclosed. The STI region comprises a lower portion filled with oxide and an upper portion comprising a high Young's modulus (HYM) liner disposed on the lower portion and trench sidewalls and filled with oxide. The HYM liner is disposed adjacent to source-drain regions, and serves to reduce stress relaxation within the shallow trench isolation (STI) oxide, which has a relatively low Young's modulus and is soft. Hence, the HYM liner serves to increase the desired stress imparted by the embedded stressor source-drain regions, which enhances carrier mobility, thus increasing semiconductor performance.
    Type: Application
    Filed: July 22, 2013
    Publication date: January 22, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Yanxiang Liu, Johannes M. van Meer, Xiaodong Yang, Manfred J. Eller
  • Publication number: 20150001669
    Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes a bottom portion and a top portion. The bottom portion has a lining oxide layer, a negatively-charged liner and a first silicon oxide. The lining oxide layer is peripherally enclosed by the semiconductor substrate, the negatively-charged liner is peripherally enclosed by the lining oxide layer, and the first silicon oxide is peripherally enclosed by the negatively-charged liner. The top portion adjoins the bottom portion, and has a second silicon oxide peripherally enclosed by and contacting the semiconductor substrate.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Cheng-Hsien Chou, Hung-Ling Shih, Tsun-Kai Tsao, Ming-Huei Shen, Kuo-Hwa Tzeng, Yeur-Luen Tu
  • Patent number: 8916433
    Abstract: When forming high-k metal gate electrode structures in an early manufacturing stage, integrity of an encapsulation and, thus, integrity of sensitive gate materials may be improved by reducing the surface topography of the isolation regions. To this end, a dielectric cap layer of superior etch resistivity is provided in combination with the conventional silicon dioxide material.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: December 23, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Peter Baars, Sven Beyer
  • Patent number: 8912074
    Abstract: A method of forming shallow trench isolation structures including the steps of forming a trench in a substrate, filling a first insulating layer in the lower portion of the trench and defining a recess at the upper portion of the trench, forming a buffer layer on the sidewall of the recess, filling a second insulating layer in the recess, and performing a steam annealing process to transform the substrate surrounding the first insulating layer into an oxide layer.
    Type: Grant
    Filed: July 13, 2014
    Date of Patent: December 16, 2014
    Assignee: United Microelectronics Corp.
    Inventors: En-Chiuan Liou, Po-Chao Tsao, Chia-Jui Liang, Jia-Rong Wu
  • Patent number: 8907444
    Abstract: Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a stress-inducing material disposed in a top portion of the trench over the insulating material.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: December 9, 2014
    Assignee: Infineon Technologies AG
    Inventors: Alois Gutmann, Roland Hampp, Scott Jansen
  • Publication number: 20140357039
    Abstract: On a substrate formed of a first semiconductor layer, an insulating layer and a second semiconductor layer, a silicon oxide pad layer and a silicon nitride pad layer are deposited and patterned to define a mask. The mask is used to open a trench through the first semiconductor layer and insulating layer and into the second semiconductor layer. A dual liner of silicon dioxide and silicon nitride is conformally deposited within the trench. The trench is filled with silicon dioxide. A hydrofluoric acid etch removes the silicon nitride pad layer along with a portion of the conformal silicon nitride liner. A hot phosphoric acid etch removes the silicon oxide pad layer, a portion of the silicon oxide filling the trench and a portion of the conformal silicon nitride liner. The dual liner protects against substrate etch through at an edge of the trench between the first and second semiconductor layers.
    Type: Application
    Filed: May 31, 2013
    Publication date: December 4, 2014
    Inventors: Qing Liu, Nicolas Loubet, Bruce Doris
  • Patent number: 8900968
    Abstract: A semiconductor device may include, but is not limited to, a semiconductor substrate having a device isolation groove defining first to fourth device formation portions. The second device formation portion is separated from the first device formation portion. The third device formation portion extends from the first device formation portion. The third device formation portion is separated from the second device formation portion. The fourth device formation portion extends from the second device formation portion. The fourth device formation portion is separated from the first and third device formation portions. The third and fourth device formation portions are positioned between the first and second device formation portions.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: December 2, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Takeshi Kishida
  • Patent number: 8895405
    Abstract: A method of manufacturing a semiconductor device includes forming a silicon nitride film having an opening portion on a semiconductor substrate, forming a silicon oxide film on the silicon nitride film and on a side face of the opening portion, performing an etching treatment to the silicon oxide film so that a sidewall is formed on the side face of the opening portion, forming a trench on the semiconductor substrate with use of the sidewall and the silicon nitride film as a mask, and forming an insulating layer in the trench. The step of forming the silicon oxide film includes oxidizing the silicon nitride film with a plasma oxidation method or a radical oxidation method.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: November 25, 2014
    Assignee: Spansion LLC
    Inventors: Fumihiko Inoue, Yukio Hayakawa
  • Publication number: 20140302663
    Abstract: A semiconductor device with an isolation layer buried in a trench includes an interface layer formed on the surface of the trench, a buffer layer formed in the interface layer at a bottom corner of the trench, a liner layer formed over the interface layer, and a gap-fill layer gap-filling the trench over the liner layer. The trench includes a micro-trench formed at the bottom corner thereof, and the buffer layer fills the micro-trench.
    Type: Application
    Filed: June 18, 2014
    Publication date: October 9, 2014
    Inventors: Hyung-Hwan KIM, Bong-Ho CHOI, Jin-Yul LEE, Seung-Seok PYO
  • Publication number: 20140264720
    Abstract: An isolation feature with a nitrogen-doped fill dielectric and a method of forming the isolation feature are disclosed. In an exemplary embodiment, the method of forming the isolation feature comprises receiving a substrate having a top surface. A recess is etched in the substrate, the recess extending from the top surface into the substrate. A dielectric is deposited within the recess such that the depositing of the dielectric includes introducing nitrogen during a chemical vapor deposition process. Accordingly, the deposited dielectric includes a nitrogen-doped dielectric. The deposited dielectric may include a nitrogen-doped silicon oxide. In some embodiments, the depositing of the dielectric disposes the nitrogen-doped dielectric in contact with a surface of the recess. In further embodiments, a liner material is deposited within the recess prior to the depositing of the dielectric within the recess.
    Type: Application
    Filed: September 9, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shing Long Lee, Yi-Chieh Wang, Chung-Han Lin, Kuang-Jung Peng, Yun Chang, Shou-Wen Kuo
  • Patent number: 8835280
    Abstract: A method for manufacturing a semiconductor device includes forming a device isolation film defining an active region, forming a recess configured to expose a seam contained in the device isolation film by etching the active region and the device isolation film, forming a sacrificial film to fill the exposed seam, and forming a gate at a lower part of the recess.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: September 16, 2014
    Assignee: SK Hynix Inc.
    Inventor: Seong Wan Ryu
  • Patent number: 8829642
    Abstract: The present invention discloses a semiconductor device, which comprises: a substrate, and a shallow trench isolation in the substrate, characterized in that, the semiconductor device further comprises a stress release layer between the substrate and the shallow trench isolation. In the semiconductor device and the method for manufacturing the same according to the present invention, the stresses accumulated during the formation of the STI can be released by interposing the stress release layer made of a softer material between the substrate and the STI, thereby reducing the leakage current of the substrate of the device and improving the device reliability.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: September 9, 2014
    Assignee: The Institute of Microelectronics, Chinese Academy of Science
    Inventors: Haizhou Yin, Wei Jiang
  • Patent number: 8823045
    Abstract: A light emitting diode includes a graphene layer, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode and a second electrode. The first semiconductor layer, the active layer, and the second semiconductor layer are stacked with each other in sequence. The first electrode is located on and electrically connected with the second semiconductor layer. The second electrode is located on and electrically connected with the first semiconductor layer. The graphene layer is located on at least one of the first semiconductor layer and the second semiconductor layer.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: September 2, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yang Wei, Shou-Shan Fan
  • Patent number: 8815700
    Abstract: In a SOI process, a high lateral voltage isolation structure is formed by providing at least two concentric dielectric filled trenches, removing the semiconductor material between the dielectric filled trenches and filling the resultant gap with dielectric material to define a single wide dielectric filled trench.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: August 26, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Peter J. Hopper, William French, Kyuwoon Hwang
  • Publication number: 20140227858
    Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.
    Type: Application
    Filed: February 13, 2013
    Publication date: August 14, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Hongliang Shen, Kyutae Na, Sandeep Gaan, Hsin-Neng Tai, Weihua Tong, Sang Cheol Han, Tae Hoon Kim, Ja Hyung Han, Haigou Huang, Changyong Xiao, Huang Liu, Seung Yeon Kim
  • Patent number: 8778751
    Abstract: A semiconductor component includes a semiconductor body having a surface and a cutout in the semiconductor body. The cutout extends from the surface of the semiconductor body into the semiconductor body in a direction perpendicular to the surface. The cutout has a base and at least one sidewall. The component further includes a layer on the surface of the semiconductor body and in the cutout. The layer forms a well above the cutout. The well has a well base, a well edge and at least one well sidewall. The at least one well sidewall forms an angle ? in the range of 20° to 80° with respect to the surface of the semiconductor body. The layer has at least one edge which, proceeding from the well edge, extends in the direction of the surface of the semiconductor body.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: July 15, 2014
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Poelzl