Abstract: A method is for the formation of at least one filled isolation trench having a protective cap in a semiconductor layer, and a semiconductor device with at least one filled isolation trench having a protective cap. The method allows obtaining, in an easy way, filled isolation trenches exhibiting excellent functional and morphological properties. The method therefore allows the obtainment of effective filled isolation trenches which help provide elevated, reliable and stable isolation properties.

Abstract: A semiconductor structure has a substrate having a trench, an isolation dielectric in the trench, and a stress buffer layer, between the substrate and the dielectric. Semiconductor devices containing the semiconductor structure may have higher reliability, and may have a reduced manufacturing costs per device.

Abstract: A semiconductor process and apparatus provides an encapsulated shallow trench isolation region by forming a silicon nitride layer (96) to cover a shallow trench isolation region (95), depositing a protective dielectric layer (97, 98) over the silicon nitride layer (96), and polishing and densifying the protective dielectric layer (97, 98) to thereby form a densified silicon nitride encapsulation layer (99) over the shallow trench isolation region (95).

Abstract: An element isolation film is formed by filling an oxide in a trench formed in an element isolation region of a semiconductor substrate to thereby form an insulation film for element isolation. A method of forming the element isolation film includes a first step of depositing a material in a plasma state including oxygen and silicon on an inner surface of the trench while applying no bias voltage (or a relatively low voltage), and a second step of filling the material in a plasma state including oxygen and silicon in the trench while applying a bias voltage (or a relatively high voltage).

Abstract: Provided are methods and composition for forming a multi-layer isolation structure on an integrated circuit substrate. A process can include selecting a lower dielectric material for the lower dielectric layer and selecting an upper dielectric material for the upper dielectric layer. A range of effective dielectric constants that correspond to the thicknesses the lower and upper dielectric materials are selected. A range of thicknesses for each of the lower and upper dielectric layers are determined from a range of acceptable dielectric constants using information indicating an effective dielectric constant corresponding to thicknesses of the materials for both the lower upper dielectric layers, enabling the formation of the multi-layer isolation structure.

Abstract: In a method of manufacturing a semiconductor device, a mask pattern is formed on an active region of a substrate. An exposed portion of the substrate is removed to form a trench in the substrate. A preliminary first insulation layer is formed on a bottom and sidewalls of the trench and the mask pattern. A plasma treatment is performed on the preliminary first insulation layer using fluorine-containing plasma to form a first insulation layer including fluorine. A second insulation layer is formed on the first insulation layer to fill the trench. A thickness of a gate insulation layer adjacent to an upper edge of the trench may be selectively increased, and generation of leakage current may be reduced.

Abstract: A method of forming an isolation structure includes the steps of: (a) forming an opening within a substrate; (b) forming a substantially conformal layer comprising tetraethoxysilane (TEOS) layer along the opening; and (c) forming a dielectric layer over the TEOS layer, the dielectric layer substantially filling the opening.

Abstract: A semiconductor device fabrication method deposits a dielectric stress-canceling film on oxide films formed on the surfaces of a semiconductor substrate and its isolation trenches, and partly etches the dielectric stress-canceling film to leave a dielectric base film inside each trench and a dielectric top film outside each trench. The trenches are then filled with a dielectric layer that covers the dielectric top and base films, the upper part of this dielectric layer is removed to expose the dielectric top films, and the dielectric top films are selectively etched, using the trench-filling dielectric layer as an etching mask. In the resulting trench isolation structure, the trenches are completely filled with dielectric material, and stress exerted by the oxide films in the trenches during heat treatment is canceled by opposing stress exerted by the dielectric base films.

Abstract: An integrated circuit and method including an isolation arrangement. One embodiment provides a substrate having trenches and mesa regions and also auxiliary structures on the mesa regions. A first isolation structure covers side walls and a bottom region of the trenches and at least partially side walls of the auxiliary structure. A liner on the first isolation structure fills the trenches and gaps between the auxiliary structures with a second isolation structure; and the second isolation structure is pulled back, wherein upper sections of the liner are uncovered.

Abstract: A method for forming an isolation layer in a semiconductor device includes forming a trench in a semiconductor substrate. A flowable insulation layer is formed to fill the trench. The flowable insulation layer is recessed. A buried insulation layer is deposited on the flowable insulation layer while keeping a deposition sputtering rate (DSR) below about 22 so as to fill the trench with the buried insulation layer while restraining the buried insulation layer from growing on a lateral portion of the trench.

Abstract: A p-type body region and an n-type buffer region are formed on an n? drift region. An n++ emitter region and a p++ contact region are formed on the p-type body region in contact with each other. A p++ collector region is formed on the n-type buffer region. An insulating film is formed on the n? drift region, and a gate insulating film is formed on the n++ emitter region, the p-type body region, and the n drift region. A gate electrode is formed on the insulating film and the gate insulating film. A p+ low-resistivity region is formed in the p-type body region and surrounding the interface between the n++ emitter region and between the p-type body region and the p++ contact region. The p-type body region has two local maxima of an impurity concentration profile at the interface between the body region and the gate insulating film.

Abstract: A semiconductor device includes a substrate having a dielectric layer and a device layer on the substrate. The device layer has an opening. First and second sublayers are disposed on the device layer and line the opening. The second sublayer serves as a stop layer for planarization to provide a substantially planarized top surface for the semiconductor device.

Abstract: A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material using an electrochemical etch to form a first cavity, a second cavity, wherein the first cavity is isolated from the second cavity, a first protrusion is between the first cavity and the second cavity, and the semiconductor material comprises silicon. The method further includes performing a thermal oxidation to convert a portion of the silicon of the semiconductor material to silicon dioxide and forming a first dielectric material over the first cavity, over the second cavity, over at least a portion of the semiconductor material, and over at least a portion of the first protrusion. Other embodiments are described and claimed.

Abstract: A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A semiconductor substrate is prepared. The semiconductor substrate has a first region and a second region other than the first region. A first mask is formed over the first region. The first mask has a first line-and-space pattern extending in a first direction. A first removing process is performed. The first removing process selectively removes the first region with the first mask to form a first groove extending in the first direction. The first removing process removes an upper part of the second region while a remaining part of the second region having a first surface facing upward. The bottom level of the first groove is higher than the level of the first surface.

Abstract: Insulating trenches isolate regions of a semiconductor layer and include hermetically sealed voids. After forming a trench, a first fill of SiO2 is formed by a CVD process with the oxide layers having increasing thickness toward the upper trench edges forming first bottlenecks. The first fill oxide layers are then RIE etched to initially remove the oxide layer from the wafer surface with continued etching to remove the oxide layers in upper trench portions to define later sealing portions of the voids or to displace the first bottlenecks downward to define further bottlenecks. A second SiO2 deposition is then performed using a low pressure CVD process to deposit oxide near steps formed previously and/or at the displaced bottlenecks to seal the voids. The deposition process is stopped when the sealed portions of the oxide layer above the voids are grown above the semiconductor wafer surface.

Abstract: Some embodiments include methods of forming isolation regions in which spin-on material (for example, polysilazane) is converted to a silicon dioxide-containing composition. The conversion may utilize one or more oxygen-containing species (such as ozone) and a temperature of less than or equal to 300° C. In some embodiments, the spin-on material is formed within an opening in a semiconductor material to form a trenched isolation region. Other dielectric materials may be formed within the opening in addition to the silicon dioxide-containing composition formed from the spin-on material. Such other dielectric materials may include silicon dioxide formed by chemical vapor deposition and/or silicon dioxide formed by high-density plasma chemical vapor deposition.

Abstract: A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. Sidewalls and a bottom surface of each of the first trenches are oxidized by a radical oxidization process to form a first oxide layer. An oxidization-prevention spacer is formed on the sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches, wherein each second trench is narrower and deeper than the corresponding first trench. The second trenches are filled with a second oxide layer. The first trenches are filled with an insulating layer.

Abstract: Manufacturing a semiconductor device includes defining bulb-type trenches having spherical portions in a silicon substrate. Oxide layers are formed in surfaces of spherical portions of the bulb-type trenches by conducting an oxidation process for the silicon substrate having the bulb-type trenches defined therein. An insulation layer is formed on the entire surface of the silicon substrate including the surfaces of the bulb-type trenches, which have the oxide layers formed in the surfaces of the spherical portions thereof. Isolation trenches are defined by etching the insulation layer, whereby SOI structures having the oxide layers interposed between portions of the silicon substrate are formed.

Abstract: Methods and apparatus are provided. An isolation region is formed by lining a trench formed in a substrate with a first dielectric layer by forming the first dielectric layer adjoining exposed substrate surfaces within the trench using a high-density plasma process, forming a layer of spin-on dielectric material on the first dielectric layer so as to fill a remaining portion of the trench, and densifying the layer of spin-on dielectric material.

Abstract: A method of forming shallow trench isolation on a substrate using a gas cluster ion beam (GCIB) is described. The method comprises generating a GCIB, and irradiating the substrate with the GCIB to form a shallow trench isolation structure by growing a dielectric layer in at least one region on the substrate.

Abstract: An isolation trench structure includes both a deep trench isolation (DTI) trench and a shallow trench isolation (STI) trench. The DTI trench can be formed by etching a deeper, narrower trench in a substrate and filling the deeper trench with one or more materials (such as an oxide). The STI trench can be formed by etching a shallower, wider trench in the substrate and filling the shallower trench with one or more materials (such as an oxide). The STI trench surrounds a portion of the DTI trench, such as by completely encircling an upper portion of the DTI trench. The DTI and STI trenches are filled during different operations, and the DTI and STI trenches can be filled with the same material(s) or with different material(s).

Abstract: A method of forming a semiconductor device includes the following processes. A first groove is formed in a semiconductor substrate. An insulating film is formed in the first groove. An interlayer insulating film is formed over the semiconductor substrate. A removing process is performed to remove a part of the interlayer insulating film and a part of the insulating film to form an alignment mark in the first groove.

Abstract: A reliable gap-filling process is performed in the manufacturing of a semiconductor device. An apparatus for performing the gap-filling process includes a chamber in which a wafer chuck is disposed, a plasma generator for generating plasma used to etch the wafer, an end-point detection unit for detecting the point at which the etching of the wafer is to be terminated, and a controller connected to the end-point detection unit. The end-point detection unit monitors the structure being etched at a region outside the opening that is to be filled, and generates in real time data representative of the layer that is being etched. As soon as an underlying layer is exposed and begins to be etched, an end-point detection signal is generated and the etching process is terminated. In the case in which the layer being etched is an oxide layer, a uniform etching is achieved despite any irregularity that exists in the thickness to which the oxide layer is formed.

Abstract: A trench is formed in a surface layer of a semiconductor substrate, the trench surrounding an active region. A lower insulating film made of insulating material is deposited over the semiconductor device, the lower insulating film filling a lower region of the trench and leaving an empty space in an upper region. An upper insulating film made of insulating material having therein a tensile stress is deposited on the lower insulating film, the upper insulating film filling the empty space left in the upper space. The upper insulating film and the lower insulating film deposited over the semiconductor substrate other than in the trench are removed.

Abstract: A method of manufacturing a semiconductor device includes a process of forming a STI trench in a substrate, a process of forming a thermal oxide film on a sidewall and a bottom surface of the STI trench, a process of performing a plasma treatment on a surface of the thermal oxide film that is located at a bottom portion of the STI trench, and a process of forming an insulating film in the STI trench using a CVD method.

Abstract: The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access device trenches, and source/drain regions are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench is formed between the adjacent recessed access devices and filled with electrically insulative material to form a trenched isolation region.

Abstract: A method for forming a semiconductor structure includes forming a plurality of features across a surface of a substrate, with at least one space being between two adjacent features. A first dielectric layer is formed on the features and within the at least one space. A portion of the first dielectric layer interacts with a reactant derived from a first precursor and a second precursor to form a first solid product. The first solid product is decomposed to substantially remove the portion of the first dielectric layer. A second dielectric layer is formed to substantially fill the at least one space.

Abstract: A masking apparatus for preventing irradiation of an outer region of a substrate during lithography is disclosed. The masking apparatus includes a mask that includes a plurality of discrete segments arranged to form a continuous ring shaped mask positioned between an outer region of a substrate and an illumination system.

Abstract: A method for manufacturing a semiconductor memory device, includes: forming a stacked unit above a semiconductor substrate; making a hole in the stacked unit to pass through electrode layers and insulating layers of the stacked unit; forming an insulating film on a side wall of the hole, the insulating film including a charge storage layer; forming a semiconductor layer in an interior of the hole to align in a stacking direction of the electrode layers and the insulating layers to form a memory string; making a trench in a portion of the stacked unit proximal to the memory string to pass through the electrode layers and the insulating layers; forming a metal film on a side wall of the trench; forming a cap film to cover the metal film and fill into the trench; performing heat treatment to form a compound on the side wall of the trench.

Abstract: The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transistor region comprises a PFET; and, the second transistor region comprises an NFET. Further, STI regions are provided in the substrate adjacent sides of and positioned between the first transistor region and the second transistor region, wherein the STI regions each comprise a compressive region, a compressive liner, a tensile region, and a tensile liner.

Abstract: A semiconductor device includes a semiconductor substrate having a trench defining an active region. A wall oxide is formed on side walls of the active region extending in the longitudinal direction, and an element isolation layer is formed in the trenches. A method of manufacturing a semiconductor device includes forming line-shape first trenches on a semiconductor substrate so as to define an active region; forming a wall oxide on surfaces of the first trenches; forming a second trench which separates the active region into a plurality of active regions; and filling the trenches with an element isolation layer.

Abstract: An isolation structure in a memory device and a method for fabricating the isolation structure. In the method, a first trench is formed in a cell region of a semiconductor substrate and a second trench in a peripheral region of the semiconductor substrate. A liner layer comprising a silicon nitride layer is formed on the first and second trenches. A spin on dielectric (SOD) layer comprising polysilazane is formed on the liner layer so as to fill the first and second trenches. A portion of the SOD layer filling the second trench is removed. A portion of the silicon nitride layer, which is disposed on the second trench and is exposed after the removing of the portion of the SOD layer, is oxidized using oxygen plasma and heat generated from the plasma. A high density plasma (HDP) oxide layer is formed to fill the second trench.

Abstract: Embodiments of a method for fabricating a semiconductor device having a reduced gate-drain capacitance are provided. In one embodiment, the method includes the steps of etching a trench in a semiconductor substrate utilizing an etch mask, widening the trench to define overhanging regions of the etch mask extending partially over the trench, and depositing a gate electrode material into the trench and onto the overhanging regions. The gate electrode material merges between the overhanging regions prior to the filling of the trench to create an empty fissure within the trench. A portion of the semiconductor substrate is removed through the empty fissure to form a void cavity proximate the trench.

Abstract: A trench isolation having a sidewall and bottom implanted region located within a substrate of a first conductivity type is disclosed. The sidewall and bottom implanted region is formed by an angled implant, a 90 degree implant, or a combination of an angled implant and a 90 degree implant, of dopants of the first conductivity type. The sidewall and bottom implanted region located adjacent the trench isolation reduces surface leakage and dark current.

Abstract: In a method of manufacturing a non-volatile memory device, a conductive structure is formed on a substrate. The conductive structure includes a tunnel oxide pattern, a first conductive pattern, a pad oxide pattern and a hard mask pattern. A trench is formed on the substrate using the conductive structure as an etching mask. An inner oxide layer is formed on an inner wall of the trench and sidewalls of the tunnel oxide pattern and the first conductive pattern. The inner oxide layer is cured, thereby forming a silicon nitride layer on the inner oxide layer. A device isolation pattern is formed in the trench, and the hard mask pattern and the pad oxide pattern are removed from the substrate. A dielectric layer and a second conductive pattern are formed on the substrate. Accordingly, the silicon nitride layer prevents hydrogen (H) atoms from leaking into the device isolation pattern.

Abstract: A method for fabricating an isolation structure in a memory device includes forming a first trench in a cell region of a semiconductor substrate and a second trench in a peripheral region of the semiconductor substrate. The method also includes oxidating the surface of the first and second trenches to form a sidewall oxide layer; depositing a tetraethylorthosilicate(TEOS) layer on the sidewall oxide layer; forming a silicon nitride layer and a silicon oxide layer on the TEOS layer; selectively removing portions of the silicon nitride and silicon oxide layers on the second trench to expose a portion of the underlying TEOS layer; coating a flowable insulation layer that fills the first and second trenches; and curing the flowable insulation layer.

Abstract: The present invention relates to a semiconductor device with a device isolation structure and a method for fabricating the same. The semiconductor device includes: a substrate provided with a trench formed in the substrate; and at least one device isolation structure including an oxide layer formed on the trench, a nitride layer formed on the oxide layer disposed on sidewalls of the trench and a high density plasma oxide layer formed on the nitride layer to fill the trench.

Abstract: A method of fabricating a semiconductor device includes forming trench-like recesses in a semiconductor substrate, the recesses including one or more recesses each of which has an opening width of not more than a predetermined value, forming a first insulating film above the substrate after the recesses have been formed, so that one or a plurality of voids are formed in the one or more recesses whose opening widths are not more than the predetermined value, removing part of the first insulating film so that a beam is left which spans the openings so that the beam passes over upper surfaces of the one or more recesses and so that at least the voids are exposed in a portion of the substrate except the beam, and filling the voids in the recesses with a material with fluidity, thereby forming second insulating films in the recesses.

Abstract: A method for forming an isolation layer of a semiconductor device includes forming a trench in a substrate, forming a high-density plasma (HDP) oxide layer filling a portion of the trench, forming a spin-on-dielectric (SOD) oxide layer having a certain height over the HDP oxide layer, performing a thermal treatment, and forming an enhanced high-aspect-ratio process (eHARP) oxide layer filling another portion of the trench over the SOD oxide layer.

Abstract: A method of forming a transistor in a semiconductor device includes forming device isolation structures in a substrate to define an active region. An oxide-based layer and a nitride-based layer are then formed between the active region and the device isolation structures. A predetermined gate region is etched in the active region to form a recess region. The damage layers are formed by a tilted ion implantation process using neutral elements on portions of the oxide-based layer exposed at the sidewalls of the recess region and other portions of the oxide-based layer below the recess region. The damage layers are then removed, thus causing a portion of the active region exposed at the bottom of the recess region to protrude.

Abstract: A shallow isolation trench structure and methods of forming the same wherein the method of formation comprises a layered structure of a buffer film layer over a dielectric layer which is atop a semiconductor substrate. Tile buffer film layer comprises a material which is oxidation resistant and can be etched selectively to oxide films. The layered structure is patterned with a resist material and etched to form a shallow trench. A thin oxide layer is formed in the trench and the buffer film layer is selectively etched to move the buffer film layer back from the corners of the trench. An isolation material is then used to fill the shallow trench and the buffer film layer is stripped to form an isolation structure. When the structure is etched by subsequent processing step(s), a capped shallow trench isolation structure which covers the shallow trench corners is created.

Abstract: A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first dielectric plug has a layer of a first dielectric material and a layer of a second dielectric material formed on the layer of the first dielectric material. A second dielectric plug of a third dielectric material is formed on the upper surface of the first dielectric plug.

Abstract: Some embodiments include methods of forming isolation regions in which spin-on material (for example, polysilazane) is converted to a silicon dioxide-containing composition. The conversion may utilize one or more oxygen-containing species (such as ozone) and a temperature of less than or equal to 300° C. In some embodiments, the spin-on material is formed within an opening in a semiconductor material to form a trenched isolation region. Other dielectric materials may be formed within the opening in addition to the silicon dioxide-containing composition formed from the spin-on material. Such other dielectric materials may include silicon dioxide formed by chemical vapor deposition and/or silicon dioxide formed by high-density plasma chemical vapor deposition.

Abstract: An SOI wafer and a method for forming the same, where the method for forming an SOI wafer includes: preparing a monocrystalline silicon wafer on which a mask layer is formed; etching the mask layer and the monocrystalline silicon wafer to form several trenches; forming a first insulating layer on the sidewalls and the bottoms of the trenches; etching and removing the first insulating layer on the bottoms of the trenches; etching along the trenches the monocrystalline silicon wafer beneath the trenches to form cavities; processing the inner walls of the cavities to form a second insulating layer; and filling up the trenches and the cavities with an insulating material layer. The process of the invention is easy to be implemented at a low manufacturing cost and an SOI wafer being formed is of high quality while being capable of being compatible with a standard process of manufacturing a bulk silicon CMOS.

Abstract: The active region of an NMOS transistor and the active region of a PMOS transistor are divided by an STI element isolation structure. The STI element isolation structure is made up of a first element isolation structure formed so as to include the interval between both active regions, and a second element isolation structure formed in the region other than the first element isolation structure.

Abstract: A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first dielectric plug has a layer of a first dielectric material and a layer of a second dielectric material formed on the layer of the first dielectric material. A second dielectric plug of a third dielectric material is formed on the upper surface of the first dielectric plug.

Abstract: A mask pattern is formed on a semiconductor substrate in which a cell region, a PMOS region, and an NMOS region are defined. Trenches are formed in the cell region, the PMOS region, and the NMOS region. A sidewall oxide layer and a protection layer are formed in the trenches, and a portion of the protection layer in the PMOS region is removed. A first device isolation insulating layer is formed on the substrate, filling the trenches. Portions of the first device isolation insulating layer are removed to expose the mask pattern and the trenches of the cell region and the NMOS region and to leave a portion of the first device isolation insulating layer in the trench in the PMOS region. A liner is formed on the portion of the first device isolation region in the trench in the PMOS region and conforming to sidewalls of the trenches in the cell region and the NMOS region. A second device isolation insulating layer is formed on the substrate, filling the trenches in the cell region and the NMOS region.

Abstract: A method of filling a trench in a substrate ensures that a void or seam is not left in the material occupying the trench. First, a preliminary insulating layer is formed so as to extend contiguously along the bottom and sides of the trench and along an upper surface of the substrate. Impurities are then implanted into a portion of the preliminary insulating layer adjacent the top of the first trench to form a first insulating layer having a doped region and an undoped region. The doped region is removed to form a first insulating layer pattern at the bottom and sides of the first trench, and which first insulating layer pattern defines a second trench. The second trench is then filled with insulating material.

Abstract: Disclosed are a transistor and a method for fabricating the same capable of increasing a threshold voltage and a driving current of the transistor. The method includes the steps of forming a first etch mask on a silicon substrate, forming a trench by etching the exposed isolation area, forming a first insulation layer in the trench and the first etch mask, forming a second insulation layer on the first insulation layer, removing the second insulation layer and the first insulation layer until the first etch mask is exposed, forming a trench type isolation layer on the isolation area, forming a second etch mask on an entire surface of the silicon substrate, etching the exposed channel area, performing an etching process with respect to a resultant substrate structure, and forming a gate in the recess.