Abstract: Disclosed is a method for fabricating a semiconductor device capable of preventing a depth of a plurality of moats M from getting deeper as preventing lowering a threshold voltage by forming a round shape of a top corner of a trench. Particularly, the method includes the steps of: forming a pad pattern by sequentially stacking a pad oxide layer and a pad nitride layer on a substrate; forming a trench by etching process to an exposed surface of the substrate by using the pad pattern as a mask; filling an insulation layer for isolating device elements filled into the trench; removing the pad nitride layer; performing a pre-cleaning process for removing the pad oxide layer; selectively recessing the surface of the substrate to remove a plurality of moats M taken place after removing the pad oxide layer; and forming a screen oxide layer on the surface of the substrate.

Abstract: A method for forming a trench having rounded corners in a semiconductor device comprises providing a substrate; forming a first pad oxide layer, a first silicon nitride layer, and a first oxide layer on the substrate sequentially; removing portions of the first oxide layer, the first silicon nitride layer, the first pad oxide layer, and the substrate to form at least one trench; and removing portions of the first oxide layer, the first silicon nitride layer, and the first pad oxide layer in the trench above an upper corner of the substrate in the trench. The substrate includes a lower corner at a bottom of the trench.

Abstract: In a method of manufacturing MOSFET devices, and particularly to the trench-type MOSFET devices, embodiments of the present invention provide methods of forming bottom oxide layers having uniform thickness on the bottom of the trenches and avoiding undesired damage in the partial semiconductor substrate near the top of the trenches. In one embodiment, a method for manufacturing a trench-type MOSFET comprises providing a semiconductor substrate and forming a trench on the semiconductor substrate; forming a first oxide layer on a bottom and sidewalls of the trench and on the semiconductor substrate; forming a bottom anti-reflective coating (BARC) layer in the trench to cover the first oxide layer; forming a photoresist layer on the bottom anti-reflective coating layer; removing the photoresist layer; removing the bottom anti-reflective coating layer; and removing the first oxide layer on the sidewalls of the trench to form a bottom oxide layer on the bottom of the trench.

Abstract: In a trench isolation structure of a semiconductor device, oxide liners are formed within the trenches, wherein a non-oxidizable mask is employed during various oxidation steps, thereby creating different types of liner oxides and thus different types of corner rounding and thus mechanical stress. Therefore, for a specified type of circuit elements, the characteristics of the corresponding isolation trenches may be tailored to achieve an optimum device performance.

Abstract: A method for fabricating a self-aligning mask layer includes the steps of forming a surface to be masked in a carrier substrate, the surface having different radii of curvature, forming an undensified conformal insulation layer on the surface such that, on account of the different radii of curvature, regions with different mechanical stress are produced in the insulation layer, and carrying out an etching-back to remove partial regions of the insulation layer in a manner dependent on the different mechanical stress in the insulation layer.

Abstract: A method for forming word line of semiconductor device wherein a lower portion of the word line on the channel region is a I-type and a upper portion of the word line is a line-type is disclosed. The method comprises (a) forming a sacrificial insulation film on a semiconductor substrate including an active region; (b) etching the sacrificial insulation film to form an I-type sacrificial insulation film pattern whereon a channel region is to be formed; (c) forming a source/drain region; (d) forming a first interlayer insulation film; (e) planarizing the first interlayer insulation film to expose the sacrificial insulation film pattern; (f) sequentially forming a insulation film and a second interlayer insulation film; (g) etching the second interlayer insulation film and insulation film using a word line mask; (h) removing the sacrificial insulation film pattern; (i) growing a gate oxide film; (j) forming a conductive layer; and (k) planarizing the conductive layer.

Abstract: A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area above the deep implantation region. The deep implantation region is formed at various process stages according to embodiments. An active device is also disclosed that is achieved by the process. A system is also disclosed that uses the active device.

Abstract: A disposable spacer for use in a semiconductor device fabrication process is formed of a germanium-silicon alloy. The germanium-silicon alloy may include a first portion (x) of germanium and a second portion (1-x) of silicon, wherein x is greater than about 0.2. A method of forming the disposal spacer includes providing a device structure and forming a layer of germanium-silicon alloy on the device structure. The layer is then etched to form the disposable spacer. The device structure may include a substrate and a gate structure with the disposable spacers formed at sidewalls thereof. Further, the device structure may include a substrate having an oxidation mask formed thereon with the disposable spacers formed relative to sidewalls of the oxidation mask. In addition, the method includes removing the disposable spacer by oxidizing the spacer to form volatile GexSiyO. Any unvolatilized GexSiyO may be removed using water.

Abstract: A flash memory cell and fabrication method thereof are disclosed. An example fabrication method deposits a pad oxide layer and a pad nitride layer on a semiconductor substrate, patterns the pad nitride layer, implants ions into the substrate to form an ion implant region, forms spacers on sidewalls of the pad nitride layer pattern, removes some part of the pad oxide layer and the top portion of the substrate through an etching process using the spacers as a mask to form a trench that divides the ion implant region into two parts. The example fabrication method also forms a gap filling insulating layer over the resulting substrate, and forms a trench isolation layer and junction regions simultaneously by removing the spacers, the pad nitride layer pattern, the pad oxide layer, and the top portion of the gap filling insulating layer.

Abstract: The present invention relates to a method for forming an isolation film for semiconductor devices.

Abstract: In a method for shallow trench isolation and a method for manufacturing a non-volatile memory device using the same, a hard mask layer pattern, a stopper layer pattern and an oxide film pattern are formed by patterning a hard mask layer, a stopper layer and an oxide film. A trench is formed by etching an upper portion of a substrate adjacent to the stopper layer pattern with the hard mask layer pattern. After removing the hard mask layer, a field oxide layer is formed in the trench. After etching the trench with the hard mask, the aspect ratio of the trench region is reduced by removing the hard mask prior to filling the trench, enhancing the gap filling margin of the trench fill process.

Abstract: Forming a vertical MOS transistor or making another three-dimensional integrated circuit structure in a silicon wafer exposes planes having at least two different crystallographic orientations. Growing oxide on different crystal planes is inherently at different growth rates because the inter-atomic spacing is different in the different planes. Heating the silicon in a nitrogen-containing ambient to form a thin layer of nitride and then growing the oxide through the thin nitrided layer reduces the difference in oxide thickness to less than 1%.

Abstract: A method of forming trench isolation within a semiconductor substrate includes forming a first isolation trench of a first open dimension within a semiconductor substrate. The first isolation trench has a base. A second isolation trench is formed into the semiconductor substrate through the base of the first isolation trench. The second isolation trench has a second open dimension along a line parallel with the first open dimension which is less than the first open dimension. Insulative isolation material is formed within the first and second isolation trenches. The insulative isolation material has a void therein extending from within the second isolation trench to the first isolation trench. Other aspects and implementations are contemplated.

Abstract: A process for making a semiconductor structure, includes forming a second dielectric layer on exposed regions of an intermediate structure. The intermediate structure includes: a semiconductor substrate having the regions, a first dielectric layer on at least a first portion of the semiconductor substrate, an etch-stop layer on at least a second portion of the first dielectric layer, and spacers on at least a third portion of said semiconductor substrate. The spacers are adjacent edges of the etch-stop layer and adjacent the exposed regions.

Abstract: Structure and method for filling an opening in a semiconductor structure that is less susceptible to the formation of voids. A first layer of a first material is formed over the layer in which the opening is to be formed, and a faceted opening is formed in the first layer. The opening in the underlying layer is subsequently formed, and the material that is to fill the opening is deposited over the faceted opening and into the opening of the underlying layer.

Abstract: Field isolation structures and methods of forming field isolation structures are described. In one implementation, the method includes etching a trench within a monocrystalline silicon substrate. The trench has sidewalls and a base, with the base comprising monocrystalline silicon. A dielectric material is formed on the sidewalls of the trench. Epitaxial monocrystalline silicon is grown from the base of the trench and over at least a portion of the dielectric material. An insulating layer is formed over the epitaxial monocrystalline silicon. According to one implementation, the invention includes a field isolation structure formed within a monocrystalline silicon comprising substrate. The field isolation structure includes a trench having sidewalls. A dielectric material is received on the sidewalls within the trench. Monocrystalline silicon is received within the trench between the dielectric material of the sidewalls. An insulating layer is received over the monocrystalline silicon within the trench.

Abstract: In a method of producing a trench insulation in a silicon substrate a first silicon-oxide layer is deposited on a front surface of a sequence of layers including the silicon substrate. Then the first silicon-oxide layer is structured so as to define a mask for a subsequent production of a trench. A trench is etched with a predetermined depth in the silicon substrate making use of the mask and filled with a silicon oxide. Then a first polysilicon layer is conformally deposited on the first silicon-oxide layer and on the oxide-filled trench. The first polysilicon layer is removed in such a way that a polysilicon cover remains on the oxide-filled trench, and the first silicon-oxide layer is removed.

Abstract: A trench isolation region is formed in a substrate by forming a trench-etching mask on the substrate. A trench is formed by etching the substrate through the trench-etching mask. An oxide layer is formed on sidewall and bottom surfaces of the trench. A liner layer is formed on the trench-etching mask and on the oxide layer. The liner layer is then removed at a boundary between the trench etching mask and the oxide layer so as to separate the liner layer into a first liner layer disposed on the trench etching mask and a second liner layer disposed on the oxide layer.

Abstract: Methods are presented for fabrication of alignment features of a desired depth, and shallow trench isolation (STI) features in Silicon-On-Insulator (SOI) material. Specific embodiments require no more than two lithography and etch processes, which represents an improvement over current methodology requiring three lithography and etch processes in order to produce the desired features during manufacture of a semiconductor device.

Abstract: A method for filling narrow isolation trenches during a semiconductor fabrication process is disclosed. The semiconductor includes both high-aspect ratio narrow isolation trenches formed in a core area of a substrate, and wide isolation trenches formed in a circuit area of the substrate. After trench formation, a thick liner oxidation is performed in all of the isolation trenches in which a layer of thermal oxide is grown to a thickness sufficient to completely fill the high-aspect ratio narrow isolation trenches. Subsequent to the liner oxidation, the wide isolation trenches are filled with an isolation dielectric, whereby all of the trenches are uniformly filled with minimal voids.

Abstract: Integrated circuit devices and methods of manufacturing same are disclosed in which an insulation layer is selectively etched to increase the self-aligned contact area adjacent a semiconductor region. For example, a pair of interconnection patterns may be formed on a substrate with the substrate having a semiconductor region disposed between the interconnection patterns. An etch-stop layer may then be formed on the pair of interconnection patterns and the substrate followed by the formation of a sacrificial insulation on the pair of interconnection patterns and on the semiconductor region. The sacrificial insulation layer is then selectively etched to expose portions of the etch-stop layer that extend on the surfaces of the pair of interconnection patterns.

Abstract: A method of etch polysilicon adjacent to a recessed STI structure feature is described. A substrate is provided with a dielectric layer thereon and a polysilicon layer on the dielectric layer. A shallow trench is formed that extends through the polysilicon and dielectric layers into the substrate. An insulating material is used to fill the trench and is then recessed in the trench below the surface of the substrate by polishing and etching steps. A conformal buffer layer is deposited which covers the polysilicon and sidewalls of the trench above the recessed insulating layer. The buffer layer is etched back to expose the insulating layer and the polysilicon is removed by a plasma etch. A spacer comprised of a portion of the buffer layer protects the substrate during the polysilicon etch to prevent unwanted trenches from being formed adjacent to the STI structure, thereby increasing the etch process window.

Abstract: A fabrication method for a read-only memory with a silicon nitride floating gate is provided. A first oxide layer and a silicon nitride layer are sequentially formed on a substrate. The silicon nitride layer and the first oxide layer are then patterned to form an opening, exposing a portion of the substrate. An oxidation process is then conducted to form a second oxide layer on the silicon nitride layer and concurrently to form a field oxide layer on the exposed substrate. The second oxide layer, the silicon nitride layer and the first oxide layer are then patterned to form an oxide dielectric layer, a silicon nitride floating gate layer and a tunnel oxide layer.

Abstract: A semiconductor flash memory device is formed with shallow trench isolation (STI) and a low-resistance source bus line (Vss Bus). Embodiments include forming core and peripheral field oxide regions, as by conventional STI techniques, bit lines by ion implantation, polysilicon floating gates above the channel regions and polysilicon word lines. The Vss Bus is then formed by etching away portions of the field oxide between corresponding source regions of adjacent bit lines to expose portions of the substrate, ion implanting impurities into the source regions and the exposed substrate, forming insulating spacers on the sides of the floating gates and word lines, and forming a metal silicide layer, such as titanium silicide, on the implanted source regions and exposed portions of the substrate to form a continuous conductor between the source regions.

Abstract: The buried oxide region has a layer added which etches selectively with respect to oxide, allowing the contacts to a gate or to a back gate to be created without overetching into the buried oxide region.

Abstract: A method of manufacturing a shallow trench isolation using a polishing step with reduced dishing. A pad layer, a polish stop layer, a buffer layer and a hard mask layer are formed over a substrate. The hard mask layer has a hard mask opening. We etch a trench opening in the buffer layer, the polish stop layer, the pad layer and form a trench in the substrate using the hard mask layer as an etch mask. We form an oxide trench liner layer along the sidewalls of the trench and an oxide buffer liner layer on the sidewalls of the buffer layer using a thermal oxidation. The hard mask layer prevents the oxidation of the top surface of the buffer layer during the oxidation of the oxide trench liner. This prevents the buffer layer from being consumed by the oxidation and leaves the buffer layer to act in the subsequent chemical-mechanical polish (CMP) step. Next, an insulating layer is formed at least partially filling the trench.

Abstract: Methods for expanding trenches are disclosed. A trench is formed in a substrate having side walls including at least two crystallographic planes. One crystallographic plane is etchable at a faster rate than a second crystallographic plane. A dielectric layer is selectively grown on surfaces of the crystallographic planes such that the dielectric layer includes a greater thickness on one of the crystallographic plane than on the other. The dielectric layer and the substrate are etched such that an etch rate inversion is achieved. That is, the second crystallographic plane is effectively etched at a faster rate than the first crystallographic plane.

Abstract: The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.

Abstract: Within a local oxidation of silicon (LOCOS) method for forming a silicon oxide isolation region, there is first amorphized areally completely at least a surface sub-layer portion of a silicon layer within an isolation region location within the silicon layer defined by an oxidation mask layer formed over the silicon layer, to form an amorphized silicon region within the isolation region location. Thus, when thermally oxidizing the silicon layer having formed thereover the oxidation mask layer to form at least in part from the amorphized silicon region a silicon oxide isolation region, the silicon oxide isolation region is formed with an attenuated bird's beak extension.

Abstract: Provided is a method for increasing an etching selectivity of photoresist material. The method initiates with providing a substrate with a developed photoresist layer. The developed photoresist layer on the substrate is formulated to contain a hardening agent. Next, the substrate is exposed to a gas, where the gas is formulated to interact with the hardening agent. A portion of the developed photoresist layer is then converted to a hardened layer where the hardened layer is created by an interaction of the hardening agent with the gas. Some notable advantages of the discussed methods of increasing the selectivity of a photoresist include improved etch profile control. Additionally, by combining fabrication steps such as the hardening of the photoresist in an etch chamber, downstream etching processes may be performed without having to transfer the wafer to an additional chamber, thereby improving wafer throughput while minimizing handling.

Abstract: A method of forming a shallow trench isolation layer in a semiconductor device is provided, wherein a first trench and a second trench are formed in an area selected from a semiconductor substrate and a sidewall oxide layer, an anti-oxidation liner, and a mask layer are formed on the semiconductor substrate including the inner surfaces of the first and second trenches, in the same order. Using photoresist lithography, the mask layer and the anti-oxidation layer are etched in the second trench. An isolation layer is formed in the first and second trenches by depositing and then chemically and mechanically polishing the dielectric material and the layers underneath until the semiconductor substrate surface is exposed. The first trench provides isolation between N-FETs, an N-FET and a P-FET, an N-FET and other circuit devices, a P-FET and other circuit devices, and other circuit devices and the second trench provides isolation between P-FETs.

Abstract: A method of manufacturing a semiconductor device, in which the depth of a divot in a shallow trench isolation can be decreased. The method comprises forming a trench in a semiconductor substrate, for isolating elements, forming a nitride film on a surface of the trench, depositing mask material on an entire surface of the semiconductor substrate, filling the trench with the mask material, etching the mask material until a surface level of the mask material in the trench falls below the surface of the semiconductor substrate, removing an exposed upper portion of the nitride film on the surface of the trench, removing the mask material from the trench, filling the trench with element-isolating material, thereby forming an element-isolating region, and forming a transistor in an element region isolated from another element region by the element-isolating region.

Abstract: A method that, using the surface-reaction mechanism of polysilicon in the chemical vapor deposition (CVD) process, starts in depositing a conformal first polysilicon layer on a uneven surface of a semiconductor wafer. The first polysilicon layer is then oxidized to a conformal first silicon oxide thin film. By repeating the previous two steps, a second polysilicon layer is formed on the surface of the first silicon oxide thin film and then oxidized to a second silicon oxide thin film with the required thickness. The conformal silicon oxide thin film formed by the method can be applied in structures of various devices in refined processes.

Abstract: This invention relates to a method for manufacturing electronic devices integrated monolithically in a semiconductor substrate delimited by two opposed front and back surfaces of a semiconductor material wafer. The method comprises at least a step of implanting ions of a noble gas, followed by a thermal treatment directed to form gettering microvoids in the semiconductor by evaporation of the gas. The ion implanting step is carried out through the back surface of the semiconductor wafer prior to starting the manufacturing process for the electronic devices, and also can be before the step of cleaning the front surface of the wafer.

Abstract: A method of forming a semiconductor component having a conductive line (24) and a silicide region (140) that crosses a trench (72). The method involves forming nitride sidewalls (127) to protect the stack during the silicidation process.

Abstract: A method for forming an element isolation film of a semiconductor device and the semiconductor device. A pad insulator is constructed on a semiconductor substrate. An over-etching process is performed to recess the semiconductor substrate to a predetermined depth while giving a pad insulator pattern. After an insulator spacer is formed at the side wall of the pad insulator pattern, the exposed region of the semiconductor substrate is thermally oxidized to grow an oxide which is, then, removed to form a recess. An element isolation film is formed in the recess by break-through field oxidation and high temperature field oxidation. The element isolation film thus obtained can prevent the field oxide “ungrowth” phenomenon and at the same time mitigate the field oxide thinning effect as well as improve the properties of the gate oxide.

Abstract: A method for forming isolation regions on a semiconductor substrate, comprises partially covering the surface of the semiconductor substrate 10 with oxidation inhibiting films 12a, and heat-treating the portions of the semiconductor substrate which are exposed from the oxidation inhibiting films. The heat treatment consists of a wet-type heating step in a gaseous atmosphere containing oxygen and hydrogen and a dry-type heating step in an atmosphere without hydrogen, which is performed after the wet-type heating step.

Abstract: A process for fabricating a structure including a carrier substrate and a layer of semiconductor material on one surface of the carrier substrate. The process a) forms a layer of semiconductor material on one surface of a first substrate, b) forms a cleavage zone in the first substrate, which delimits a superficial layer, c) transfers the first substrate, with the layer of semiconductor material, onto the carrier substrate, d) provides energy to cause cleavage of the first substrate along the cleavage zone, and e) removes said superficial layer to uncover the layer of semiconductor material.

Abstract: A method for fabrication a shallow trench isolation (STI) structure by combining uses of a STI process and a local oxidation (LOCAS) process is provided. The method includes forming a first liner oxide layer over a substrate, on which a patterned hard material layer is formed. A hard spacer is formed on each sidewall of the hard material layer. A LOCOS structure is formed on the substrate other than the hard spacer and the hard material layer. Then, the hard spacer is removed to expose a portion of the pad oxide on the substrate. A trench is formed in the substrate on each side of the LOCOS structure. A conformal second liner oxide layer is formed on the inner surface of the trench. The trench is filled with a polysilicon layer, having a surface higher than the substrate surface. A second thermal process is performed to oxidize the polysilicon layer so as to merge the LOCOS structure to cover the surface of the polysilicon layer.

Abstract: A semiconductor wafer in which black silicon does not form during trench etching even when side rinsing is carried out during a photolithography process. In an embedded oxide film interposed between first and second semiconductor wafers of a bonded SOI wafer, the film thickness of a peripheral part thereof is made greater than a predetermined thickness Dsio so that it functions as an oxide film for etching prevention. When side rinsing is carried out in a resist coating process to form an opening in an oxide film for masking use in trench etching, the oxide film for masking use at the periphery is also etched during formation of the opening. Due to over-etching at that time, the oxide film for etching prevention is etched by a film thickness d1. During trench etching also, the oxide film for etching prevention is etched by a film thickness d2.

Abstract: A method for forming a pullback opening above a shallow trench isolation structure. A patterned mask layer is formed over a substrate. A sacrificial layer is formed on the sidewalls of the mask layer. The exposed portion of the substrate is etched to form a trench in the substrate. The sacrificial layer is removed to increase the width of the opening above the trench.

Abstract: With the present invention, a filled isolation trench is fabricated as part of an integrated circuit on a semiconductor wafer using nitrogen implantation into at least one side wall of the isolation trench. An isolation trench is etched within a layer of semiconductor material. The isolation trench has at least one side wall comprised of the semiconductor material, and the isolation trench has a bottom wall. Nitrogen ions are implanted into the at least one side wall of the isolation trench. A layer of an insulator material is thermally grown from the at least one side wall and the bottom wall of the isolation trench. The isolation trench is then filled with the insulator material using a deposition process to form the filled isolation trench. With the present invention, the nitrogen ions implanted into the at least one side wall of the isolation trench reduce a radius of a bird's beak formed on the at least one side wall of the isolation trench.

Abstract: A method for manufacturing a semiconductor device includes the steps of (1) forming a pad oxide film of 5 nm or more on a circuit forming surface of a semiconductor substrate; (2) forming an oxidation inhibition film on the pad oxide film; (3) forming grooves of a given depth with the oxidation inhibition film as a mask; (4) receding the pad oxide film; (5) oxidizing the grooves formed on the semiconductor substrate in the range of 0<C≦0.88t−924 in which the oxidizing atmosphere is dry oxidation (H2/O2≈0), the oxygen partial pressure in the air corresponding to the oxygen partial pressure ratio is C %, and the oxidizing temperature is t (° C.

Abstract: A method for forming an element isolation film of a semiconductor device and the semiconductor device. A pad insulator is constructed on a semiconductor substrate. An over-etching process is performed to recess the semiconductor substrate to a predetermined depth while giving a pad insulator pattern. After an insulator spacer is formed at the side wall of the pad insulator pattern, the exposed region of the semiconductor substrate is thermally oxidized to grow an oxide which is, then, removed to form a recess. An element isolation film is formed in the recess by break-through field oxidation and high temperature field oxidation. The element isolation film thus obtained can prevent the field oxide “ungrowth” phenomenon and at the same time mitigate the field oxide thinning effect as well as improve the properties of the gate oxide.

Abstract: A low dielectric constant (k) material, such as methylsilsesquioxane (MSQ), used as an interlevel dielectric is expected to reduce the parasitic capacitance in integrated circuit. However, MSQ film can be easily degraded during resist ashing after the film is etched with the damascene trenches being created. The present invention discloses an innovative sidewall capping technology to solve the degradation issue. Prior to resist ashing, a high-quality, low-k oxide film is selectively deposited onto the sidewalls of MSQ trenches using selective liquid-phase deposition. Experimental results demonstrate that the capping oxide can effectively protect the sidewalls of MSQ trenches from ashing-induced degradation.

Abstract: In a fabrication process, photoresist is disposed over a semiconductor substrate (10), covering a front surface (11) of the substrate (10) and filling trenches (12, 14, 16, 18) therein. The photoresist is planarized in chemical mechanical polishing to achieve a uniform thickness throughout the substrate (10). An anisotropic etching process partially removes the photoresist in the trenches (12, 14, 16, 18), thereby creating recesses in the trenches (12, 14, 16, 18). Because the thickness of the photoresist is uniform throughout the substrate (10) before the etching process, the depths of the recesses in different trenches (12, 14, 16, 18) are substantially equal to each other. A uniform recess depth throughout the substrate (10) is thereby achieved. The uniform recess depth facilitates in ensuring the semiconductor devices fabricated on the substrate (10) to have consistent parameters, characteristics, and performances.

Abstract: In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions.

Abstract: A method of fabricating shallow trench isolations has been achieved. A semiconductor substrate is provided. A pad oxide layer is grown overlying the semiconductor substrate. A silicon nitride layer is deposited. The silicon nitride layer and the pad oxide layer are patterned to form a hard mask. The openings in the hard mask correspond to planned trenches in the semiconductor substrate. A silicon dioxide layer is deposited overlying the silicon nitride layer and the semiconductor substrate. The silicon dioxide layer is anisotropically etched to form sidewall spacers on the inside of the openings of the hard mask. The semiconductor substrate is etched to form the trenches. The sidewall spacers are etched away. The semiconductor substrate is sputter etched to round the corners of the trenches. An oxide trench lining layer is grown overlying the semiconductor substrate. A trench fill layer is deposited overlying the silicon nitride layer and filling the trenches.

Abstract: The method includes forming a pad oxide, a polysilicon layer over a substrate. Next, an oxide layer is formed over the polysilicon layer. An opening is formed in the oxide layer, the polysilicon layer, and the pad layer. A trench is formed by etching the substrate using the oxide layer as a mask. A sidewall structure is then formed on the opening. Next, an exposed portion of the substrate is etched by using the sidewall structure as a mask. The sidewall structure and the oxide layer are then removed. An oxide and an oxynitride layer are then formed on the aforesaid feature. A semiconductor layer is then formed over the oxynitride layer. A portion of the semiconductor layer is oxidized for forming an insulating layer. Finally, a refilling layer is formed over the insulating layer and the substrate is planarized for having a planar surface.

Abstract: In order to form an isolation structure in a substrate, a blocking layer (13, 14) is fabricated over the substrate (12), after which portions of the blocking layer and the substrate are removed at an isolation region (22). A dielectric layer (26) is then deposited over the blocking layer and the isolation region. Thereafter, a chemical-mechanical polishing process is carried out on the dielectric layer, so as to remove a substantial portion of the dielectric layer disposed above an upper surface of the blocking layer. A non-patterned etch is then carried out on the dielectric layer, in order to remove a remaining portion of the dielectric layer disposed above the upper surface of the blocking layer.