Abstract: Examples of methods and systems for laser processing of materials are disclosed. Methods and systems for singulation of a wafer comprising a coated substrate can utilize a laser outputting light that has a wavelength that is transparent to the wafer substrate but which may not be transparent to the coating layer(s). Using techniques for managing fluence and focal condition of the laser beam, the coating layer(s) and the substrate material can be processed through ablation and internal modification, respectively. The internal modification can result in die separation.

Abstract: A spalling method is provided that includes depositing a stressor layer on surface of a base substrate, and contacting the stressor layer with a planar transfer. The planar transfer surface is then traversed along a plane that is parallel to and having a vertical offset from the upper surface of the base substrate. The planar transfer surface is traversed in a direction from a first edge of the base substrate to an opposing second edge of the base substrate to cleave the base substrate and transfer a spalled portion of the base substrate to the planar transfer surface. The vertical offset between the plane along which the planar transfer surface is traversed and the upper surface of the base substrate is a fixed distance. The fixed distance of the vertical offset provides a uniform spalling force. A spalling method is also provided that includes a transfer roller.

Abstract: A method for producing singulated semiconductor components includes providing a starting substrate. An etching process is carried out to form depressions at a side of the starting substrate. The depressions are arranged in the region of the semiconductor components to be produced. Walls present between the depressions are arranged in the region of separating regions provided for severing the starting substrate. The method furthermore comprises forming a metallic layer on the side of the starting substrate with the depressions and walls and carrying out a further etching process for severing the starting substrate in the separating regions and forming the singulated semiconductor components.

Abstract: Methods of fabricating semiconductor devices that include interposers include the formation of conductive vias through a material layer on a recoverable substrate. A carrier substrate is bonded over the material layer, and the recoverable substrate is then separated from the material layer to recover the recoverable substrate. A detachable interface may be provided between the material layer and the recoverable substrate to facilitate the separation. Electrical contacts that communicate electrically with the conductive vias may be formed over the material layer on a side thereof opposite the carrier substrate. Semiconductor structures and devices are formed using such methods.

Abstract: Methods of forming a semiconductor structure include exposing a carrier substrate to a silane material to form a coating, removing a portion of the coating at least adjacent a periphery of the carrier substrate, adhesively bonding another substrate to the carrier substrate, and separating the another substrate from the carrier substrate. The silane material includes a compound having a structure of (XO)3Si(CH2)nY, (XO)2Si((CH2)nY)2, or (XO)3Si(CH2)nY(CH2)nSi(XO)3, wherein XO is a hydrolyzable alkoxy group, Y is an organofunctional group, and n is a nonnegative integer. Some methods include forming a polymeric material comprising Si—O—Si over a first substrate, removing a portion of the polymeric material, and adhesively bonding another substrate to the first substrate.

Abstract: A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes.

Abstract: Provided is a novel method for forming a groove composed of two smooth inclined surfaces on a surface of a flat plate formed of a nitride semiconductor crystal having an A, C, M-axes. In the present invention, a disk-shaped dicing blade is moved along a direction of the A-axis to form first and second inclined surfaces on the surface of the flat plate. The following mathematical formulae (I)-(III) are satisfied: 45 degrees??b?a?60 degrees (I) 45 degrees??b+a?60 degrees (II), 0 degrees?|a|?7.5 degrees, where angle ?b represents an angle formed between a surface of the edge and a radial direction of the dicing blade in a cross-sectional view which includes the M-axis and the C-axis. The angle a represents an angle formed between the principal surface and the M-axis.

Abstract: A method for calculating a warpage of a bonded SOI wafer includes: assuming that the epitaxial growth SOI wafer is a silicon single crystal wafer having the same dopant concentration as dopant concentration of the bond wafer; calculating a warpage A that occurs at the time of performing the epitaxial growth relative to the assumed silicon single crystal wafer; calculating a warpage B caused due to a thickness of the BOX layer of the epitaxial growth SOI wafer; determining a measured value of a warpage of the base wafer before bonding as a warpage C; and calculating a sum of the warpages (A+B+C) as the warpage of the bonded SOI wafer.

Abstract: An image display device includes a resin film, an organic film which is formed above the resin film, a circuit layer which is formed above the organic film and includes at least a thin film transistor, and a barrier layer which is formed between the organic film and the circuit layer. The organic film has a first surface which faces the circuit layer and a side surface which crosses the first surface. The barrier layer covers the first surface and the side surface.

Abstract: The disclosure relates to a method for implantation of atomic or ionic species into a batch of substrates made of semiconductor material, in which: each substrate made of semiconductor material is positioned on a respective support of a batch implanter, each substrate comprising a thin layer of electrical insulator on its surface; and a dose of at least one ionic or atomic species is implanted over the whole surface of the substrates, through their layer of insulator, so as to form a fragilization region within each substrate and to bound there a thin layer of semiconductor material between the thin layer of insulator and the fragilization region of the substrate, the implantation method being characterized in that, during the method, each support on which a substrate is positioned has at least two separate inclinations with respect to the plane orthogonal to the direction of implantation of the species in order to improve the implantation depth of the species in the substrate.

Abstract: Engineered substrates having mechanically weak structures for separating substrates from epitaxially grown semiconductor structures and associated systems and methods are disclosed herein. In several embodiments, for example, an engineered substrate can be manufactured by forming an intermediary material at an upper surface of a structural material and forming a plurality of pores in the intermediary material. The porous intermediary material and the structural material can define a handle substrate. The method can further include bonding an epitaxial formation structure on the handle substrate such that the porous intermediary material is between the epitaxial formation structure and the structural material. In various embodiments, the porous intermediary material is configured to break under mechanical stress.

Abstract: The present invention relates to a LED (light-emitting diode) phosphor and fabricating method thereof, and particularly relates to a LED phosphor having a light-emitting thin film (or photoluminescence thin film) made of an organic material and a zinc oxide microstructure (or nanostructure) and a method for fabricating the LED phosphor by hydrothermal method and combination of the organic material and the zinc oxide microstructure (or nanostructure). In this invention, the light-emitting thin film (or photoluminescence thin film) made of the organic material and the zinc oxide microstructure (or nanostructure) is applied instead of rare earth elements to fabricate the LED phosphor. Therefore, the cost of the LED phosphor and the white LED can be reduced and the processes for fabricating the LED phosphor and the white LED can be simplified.

Abstract: A method of manufacturing a display panel having a display part and a terminal part each formed on a different area on a TFT substrate, comprising: a step of forming the display part on the TFT substrate; a step of forming a conductive layer of a conductive metal oxide or a metal on an area where the terminal part is to be formed; a step of forming a chemical vapor deposition layer of an inorganic compound by a chemical vapor deposition method so that the chemical vapor deposition layer covers the display part and comes into contact at least with an upper surface of the conductive layer and so that the upper surface of the conductive layer alters; and a step of removing a portion of the chemical vapor deposition layer on the conductive layer.

Abstract: A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive.

Abstract: An objective of the present invention is to increase production efficiency of high-performance flexible semiconductor devices. A semiconductor device manufacturing method includes: a step of forming an insulating substrate (10) which is configured of glass substrates (11, 13) with a thermal expansion coefficient which approximates the thermal expansion coefficient of a single-crystal silicon substrate (20) and a plastic substrate (12) which is positioned between both of the glass substrates; and a step of, after bonding the insulating substrate (10) with the single-crystal silicon substrate (20), separating a portion of the single-crystal silicon substrate (20) with heat processing, and forming a single-crystal silicon layer (14) upon the glass substrate (11).

Abstract: A method for fabricating a semiconductor device includes a first step of forming, on a first substrate, a first element region in which a plurality of elements are collectively arranged, a second step of relocating the plurality of elements formed on the first substrate to a holding member in the same arrangement as in the first element region to have the plurality of elements held on the holding member, a third step of rearranging the plurality of elements held on the holding member and having the plurality of elements held on an intermediate substrate, thereby forming a second element region having a shape different from a shape of the first element region on the intermediate substrate, and a fourth step of dispersing the plurality of elements held on the intermediate substrate and adhering the plurality of elements to a second substrate.

Abstract: A method for mechanically separating a laminar structure from a first carrier assembly, comprising or consisting of a first carrier, wherein the laminar structure comprises a wafer and a second, stretchable carrier is disclosed. Also disclosed are the use of a particular separating aid for separating a laminar structure and a device for carrying out the method.

Abstract: An apparatus for performing communication control includes a control module implemented with at least one integrated circuit (IC) whose package includes a plurality of sets of terminals, each set of the plurality of sets of terminals corresponding to one of a plurality of sub-modules of the control module, and within the sets of terminals, a set of terminals corresponding to a specific sub-module of the sub-modules include a power-input terminal arranged to input power from outside the control module. For example, on a printed circuit board (PCB) of the apparatus, arrangement of some modules is similar to that of some contact pads associated to the sets of terminals. In another example, the control module includes a power distribution system including at least one power distribution wire. In another example, a PCB within the apparatus includes at least one signal transmission wire and at least one set of co-plane ground wires.

Abstract: The invention relates to a process for fabricating a semiconductor that comprises providing a handle substrate comprising a seed substrate and a weakened sacrificial layer covering the seed substrate; joining the handle substrate with a carrier substrate; optionally treating the carrier substrate; detaching the handle substrate at the sacrificial layer to form the semiconductor structure; and removing any residue of the sacrificial layer present on the seed substrate.

Abstract: A method of manufacturing a semiconductor substrate includes forming a first semiconductor layer on a substrate, forming a metallic material layer on the first semiconductor layer, forming a first portion of a second semiconductor layer on the first semiconductor layer and the metallic material layer, removing the metallic material layer under the first portion of the second semiconductor layer by dipping the substrate in a solution, forming a second portion of the second semiconductor layer on the first portion of the second semiconductor layer, and forming a cavity in a portion of the first semiconductor layer located under where the metallic material layer was removed.

Abstract: A GaN-based diode may include an intrinsic GaN-based semiconductor layer, GaN-based semiconductor layers configured to have a first conductivity type and bonded to the intrinsic GaN-based semiconductor layer. A first electrode made of metal is placed on a surface opposite a surface bonded to the GaN-based semiconductor layers of the intrinsic GaN-based semiconductor layer; a second electrode is placed on a surface opposite to a surface bonded to the intrinsic GaN-based semiconductor layer of the GaN-based semiconductor layers of the first conductivity type. Voltage-resistant layers configured to have a second conductivity type are formed in regions of the intrinsic GaN-based semiconductor layer that come in contact with edges of the first electrode.

Abstract: A method of processing a laminated wafer in which a first wafer is laminated on a second wafer, the method including: a laminated wafer forming step of forming the laminated wafer by laminating the first wafer on the second wafer; a modified layer forming step of forming a modified layer within the first wafer by positioning a focusing point of a laser beam within the first wafer and moving the first wafer in a horizontal direction relative to the focusing point while applying the laser beam, the modified layer forming step being performed before or after the laminated wafer forming step is performed; and a separating step of separating part of the first wafer from the laminated wafer with the modified layer as a boundary, the separating step being performed after the laminated wafer forming step and the modified layer forming step are performed.

Abstract: Methods of forming a semiconductor structure include exposing a carrier substrate to a silane material to form a coating, removing a portion of the coating at least adjacent a periphery of the carrier substrate, adhesively bonding another substrate to the carrier substrate, and separating the another substrate from the carrier substrate. The silane material includes a compound having a structure of (XO)3Si(CH2)nY, (XO)2Si((CH2)nY)2, or (XO)3Si(CH2)nY(CH2)nSi(XO)3, wherein XO is a hydrolyzable alkoxy group, Y is an organofunctional group, and n is a nonnegative integer. Some methods include forming a polymeric material comprising Si—O—Si over a first substrate, removing a portion of the polymeric material, and adhesively bonding another substrate to the first substrate.

Abstract: Film thickness variations are prevented in a plurality of single crystal semiconductor films separated at a fragile layer reliably and transferred to a base substrate.

Abstract: A method includes forming a release layer over a donor substrate. A plurality of devices made of a first semiconductor material are formed over the release layer. A first dielectric layer is formed over the plurality of devices such that all exposed surfaces of the plurality of devices are covered by the first dielectric layer. The plurality of devices are chemically attached to a receiving device made of a second semiconductor material different than the first semiconductor material, the receiving device having a receiving substrate attached to a surface of the receiving device opposite the plurality of devices. The release layer is etched to release the donor substrate from the plurality of devices. A second dielectric layer is applied over the plurality of devices and the receiving device to mechanically attach the plurality of devices to the receiving device.

Abstract: There is provided a method of fabricating a semiconductor device, method including: a) forming semiconductor elements in plural element regions surrounded by assumed dicing lines on a first principal surface of a semiconductor wafer; b) grinding the second principal surface in such a way that an outer peripheral portion of a second principal surface on the opposite side of the first principal surface of the semiconductor wafer becomes thicker than an inner peripheral portion of the second principal surface; c) forming a metal film, in such a way as to avoid sections corresponding to the dicing lines, on the second principal surface that has been ground in the grinding step; and d) cutting the semiconductor wafer from the second principal surface side along portions where the metal film is not formed on the dicing lines.

Abstract: A method for reducing irregularities at a surface of a layer transferred from a source substrate to a glass-based support substrate, by generating a weakening zone in the source substrate; contacting the source substrate and the glass-based support substrate; and splitting the source substrate at the weakening zone; wherein the glass-based substrate has a thickness of between 300 ?m and 600 ?m.

Abstract: A laser processing method is provided, which, even when a substrate formed with a laminate part including a plurality of functional devices is thick, can cut the substrate and laminate part with a high precision. This laser processing method irradiates a substrate 4 with laser light L while using a rear face 21 as a laser light entrance surface and locating a light-converging point P within the substrate 4, so as to form modified regions 71, 72, 73 within the substrate 4. Here, the HC modified region 73 is formed at a position between the segmented modified region 72 closest to the rear face 21 and the rear face 21, so as to generate a fracture 24 extending along a line to cut from the HC modified region 73 to the rear face 21.

Abstract: Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes). By this test, conduction between the bumps (electrodes) on the back surface side is checked.

Abstract: Systems and methods of separating bonded wafers are disclosed. In one embodiment, a system for separating bonded wafers includes a support for the bonded wafers and means for applying a sheer force to the bonded wafers. The system also includes means for applying a vacuum to the bonded wafers.

Abstract: A device is intended for a laser lift-off method to sever at least one layer from a carrier. The device includes a laser that generates pulsed laser radiation and at least one beam splitter. The laser radiation is divided into at least two partial beams by the at least one beam splitter. The partial beams are superimposed in an irradiation plane, the irradiation plane being provided such that a major side of the carrier remote from the layer is arranged therein. At the irradiation plane, an angle (?) between the at least two partial beams is at least 1.0°.

Abstract: It is an object to provide a method for manufacturing an SOI substrate in which crystal defects of a single crystal semiconductor layer are reduced even when a single crystal semiconductor substrate in which crystal defects exist is used. Such an SOI substrate can be manufactured through the steps of forming a single crystal semiconductor layer which has an extremely small number of defects over a single crystal semiconductor substrate by an epitaxial growth method; forming an oxide film on the single crystal semiconductor substrate by thermal oxidation treatment; introducing ions into the single crystal semiconductor substrate through the oxide film; bonding the single crystal semiconductor substrate into which the ions are introduced and a semiconductor substrate to each other; causing separation by heat treatment; and performing planarization treatment on the single crystal semiconductor layer provided over the semiconductor substrate.

Abstract: A method for separating a layer for transfer includes forming a crack guiding layer on a substrate and forming a device layer on the crack-guiding layer. The crack guiding layer is weakened by exposing the crack-guiding layer to a gas which reduces adherence at interfaces adjacent to the crack guiding layer. A stress inducing layer is formed on the device layer to assist in initiating a crack through the crack guiding layer and/or the interfaces. The device layer is removed from the substrate by propagating the crack.

Abstract: The invention relates to a process for thinning the active silicon layer of a substrate, which comprises an insulator layer between the active layer and a support, this process comprising one step of sacrificial thinning of active layer by formation of a sacrificial oxide layer by sacrificial thermal oxidation and deoxidation of the sacrificial oxide layer. The process is noteworthy in that it comprises: a step of forming a complementary oxide layer, on the active layer, using an oxidizing plasma, this layer having a thickness profile complementary to that of oxide layer, so that the sum of the thicknesses of the oxide layer and of the sacrificial silicon oxide layer are constant over the surface of the treated substrate, a step of deoxidation of this oxide layer, so as to thin active layer by a uniform thickness.

Abstract: A method for manufacturing a semiconductor nano layer structure includes: two substrates are provided; a plurality of semiconductor nanowires are formed on one of the substrates; an absorption surface is formed on the other substrate; one of the substrates is fixed on a cylindrical roller, the cylindrical roller is brought into contact with a surface of the substrate which is stationary and is not fixed on the cylindrical roller, and rolled with a constant velocity and pressure so that the semiconductor nanowires are break, detached, transferred and absorbed, and a semiconductor nano layer structure is formed on the stationary substrate; a de-laminating process is performed to separate the semiconductor nano layer structure from the second substrate; an electric Joule heat welding process is locally performed to bond each of the semiconductor nanowires of the semiconductor nano layer structure or each semiconductor nano layer structure.

Abstract: Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also include an attachment feature between the first and second dies. The attachment feature can be composed of a dielectric adhesive material. The attachment feature includes (a) a single, unitary structure covering at least approximately all of the back side of the second die, and (b) a plurality of interconnect structures electrically coupled to internal active features of both the first die and the second die.

Abstract: A method to remove epitaxial semiconductor layers from a substrate by growing an epitaxial sacrificial layer on the substrate where the sacrificial layer is a transition metal nitride (TMN) or a TMN ternary compound, growing one or more epitaxial device layers on the sacrificial layer, and separating the device layers from the substrate by etching the sacrificial layer to completely remove the sacrificial layer without damaging or consuming the substrate or any device layer. Also disclosed are the related semiconductor materials made by this method.

Abstract: A temporary bonding adhesive composition includes a first compound including a thermosetting polyorganosiloxane and a second compound including a thermoplastic polyorganosiloxane.

Abstract: An object is to provide a manufacturing method of a semiconductor device in which a defect in characteristics due to a crack occurring in a semiconductor device is reduced. Provision of a crack suppression layer formed of a metal film in the periphery of a semiconductor element makes it possible to suppress a crack occurring from the outer periphery of a substrate and reduce damage to the semiconductor element. In addition, even if the semiconductor device is subjected to physical forces from the outer periphery in separation and transposition steps, progression (growth) of a crack to the semiconductor device can be suppressed by the crack suppression layer.

Abstract: A semiconductor device has a semiconductor wafer with a plurality of semiconductor die separated by a non-active region. The semiconductor die can be circular or polygonal with three or more sides. A plurality of bumps is formed over the semiconductor die. A portion of semiconductor wafer is removed to thin the semiconductor wafer. A wafer ring is mounted to mounting tape. The semiconductor wafer is mounted to the mounting tape within the wafer ring. The mounting tape includes translucent or transparent material. A penetrable layer is applied over the bumps formed over the semiconductor wafer. An irradiated energy from a laser is applied through the mounting tape to the non-active region to form a modified region within the non-active region. The semiconductor wafer is singulated along the modified region to separate the semiconductor die.

Abstract: The present invention is directed to a method for manufacturing an SOI wafer in which the bonded SOI wafer after the delamination by the ion implantation delamination method is subjected to a rapid thermal oxidation process such that an oxide film is formed on a surface of the SOI layer, the oxide film is removed, the bonded SOI wafer is then subjected to a flattening heat treatment to flatten the surface of the SOI layer, the flattening heat treatment causing migration of silicon atoms of the surface of the SOI layer, and the bonded SOI wafer is then subjected to a sacrificial oxidation process to adjust a film thickness of the SOI layer. The method enables efficient manufacture of a high quality SOI wafer having an SOI layer with sufficiently reduced surface roughness of the SOI layer surface and fewer deep pits in the SOI layer surface.

Abstract: A recessed portion is formed around an outer edge of a device wafer at a peripheral edge portion of a first face of the device wafer. A recessed portion is formed around an outer edge of a support substrate, at a bonding face of the support substrate. The first face of the device wafer and the bonding face of the support substrate are bonded together by an adhesive. The device wafer is ground from a second face side, on the opposite side to the first face 11, as far as a depth position to reach a bottom face of the recessed portion.

Abstract: A substrate separating method includes: holding, in a predetermined position, a substrate sandwiched between a first holder and a second holder opposed to each other; and relatively moving the first holder and the second holder while the substrate is held in the predetermined position. In holding the substrate, the substrate may be held in the predetermined position by effecting a pressurizing force or a suction force onto the substrate. Also in holding the substrate, the substrate may be held in contact with one of the first holder and the second holder.

Abstract: Fabrication methods are disclosed that facilitate the production of electronic structures that are both flexible and stretchable to conform to non-planar (e.g. curved) surfaces without suffering functional damage due to excessive strain. Electronic structures including CMOS devices are provided that can be stretched or squeezed within acceptable limits without failing or breaking. The methods disclosed herein further facilitate the production of flexible, stretchable electronic structures having multiple levels of intra-chip connectors. Such connectors are formed through deposition and photolithographic patterning (back end of the line processing) and can be released following transfer of the electronic structures to flexible substrates.

Abstract: Methods for forming semiconductor devices include providing a textured template, forming a buffer layer over the textured template, forming a substrate layer over the buffer layer, removing the textured template, thereby exposing a surface of the buffer layer, and forming a semiconductor layer over the exposed surface of the buffer layer.

Abstract: Methods and structures for heterogeneous integration of diverse material systems and device technologies onto a single substrate incorporate layer transfer techniques into an epitaxy level packaging process. A planar substrate surface of multiple epitaxial areas of different materials can be heterogeneously integrated with a substrate material. Complex assembly and lattice engineering is significantly reduced. Microsystems of different circuits made from different materials can be built from a single wafer Fab line employing the claimed processes.

Abstract: A method for wafer transfer includes forming a spreading layer, including graphene, on a single crystalline SiC substrate. A semiconductor layer including one or more layers is formed on and is lattice matched to the crystalline SiC layer. The semiconductor layer is transferred to a handle substrate, and the spreading layer is split to remove the single crystalline SiC substrate.

Abstract: Methods for removing a material layer from a base substrate utilizing spalling in which mode III stress, i.e., the stress that is perpendicular to the fracture front created in the base substrate, during spalling is reduced. The substantial reduction of the mode III stress during spalling results in a spalling process in which the spalled material has less surface roughness at one of its' edges as compared to prior art spalling processes in which the mode III stress is present and competes with spalling.

Abstract: Fabrication methods are disclosed that facilitate the production of electronic structures that are both flexible and stretchable to conform to non-planar (e.g. curved) surfaces without suffering functional damage due to excessive strain. Electronic structures including CMOS devices are provided that can be stretched or squeezed within acceptable limits without failing or breaking The methods disclosed herein further facilitate the production of flexible, stretchable electronic structures having multiple levels of intra-chip connectors. Such connectors are formed through deposition and photolithographic patterning (back end of the line processing) and can be released following transfer of the electronic structures to flexible substrates.

Abstract: A method for forming a multi-material thin film includes providing a multi-material donor substrate comprising single crystal silicon and an overlying film comprising GaN. Energetic particles are introduced through a surface of the multi-material donor substrate to a selected depth within the single crystal silicon. The method includes providing energy to a selected region of the donor substrate to initiate a controlled cleaving action in the donor substrate. Then, a cleaving action is made using a propagating cleave front to free a multi-material film from a remaining portion of the donor substrate, the multi-material film comprising single crystal silicon and the overlying film.