Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

Abstract: The present invention relates to a resin composition which includes a copolymer consisting of a first monomer containing a monomer unit having at least one carboxyl group and a second monomer copolymerizable with the first monomer, and also includes an ultraviolet absorber. The resin composition used is a resin composition for which, when ?1 represents an absorbance coefficient per unit weight of a resin film 2 in a solution prepared by dissolving, in a solvent, the resin film 2 formed by application of the resin composition as a liquid, ?1 at a light wavelength at which the resin film 2 is to be irradiated is at least 0.01 (L/(g·cm)).

Abstract: Embodiments of the present disclosure relate to a leadless surface mount assembly package, an electronic device, and a method for forming a surface mount assembly package, which package comprising: a first lead; a second lead; a chip fixed on an upper surface of the first lead; a clip coupled to the second lead, a lower surface of the clip being fixed to an upper surface of the chip. The surface mount assembly package further comprises a molding compound for molding the first lead, the second lead, the chip, and the clip, wherein ends of the first lead and the second lead are only exposed from the molding compound, without outward extending from the molding compound. By using the embodiments of the present disclosure, costs can be saved and processing flow can be simplified, and a new-model leadless surface mount assembly package is obtained.

Abstract: A light-emitting diode device and a manufacturing method thereof. The light-emitting diode device includes: a substrate (1); an epitaxial layer at one side of the substrate (1) and including an N-type layer (2), a P-type layer (4), and an active layer (3) between the N-type layer (2) and the P-type layer (4); an N-type electrode (5); a P-type electrode (7); an adhesive layer (8); and a patterned substrate (9). The light-emitting diode device further includes an insulating layer (6) between the N-type electrode (5) and the P-type electrode (7), the insulating layer (6) electrically insulating the N-type electrode (5) and the P-type electrode (7). In the light-emitting diode device and the manufacturing method thereof, light-emitting efficiency and luminous efficiency of the light-emitting diode device can be improved, wiring is easier as compared with conventional chips, and the manufacturing process can be optimized.

Abstract: A method and system of hybrid laser dicing are described. In one embodiment, a method includes focusing a laser beam inside a substrate in regions between integrated circuits, inducing defects inside the substrate in the regions. The method involves patterning a surface of the substrate with a laser scribing process in the regions after inducing the defects in the substrate. The method further involves singulating the integrated circuits at the regions with the induced defects. In another embodiment, a system includes a first laser module configured to focus a laser beam inside a substrate in regions between integrated circuits, inducing defects inside the substrate in the regions. A second laser module is configured to pattern a surface of the substrate with a laser scribing process in the regions after inducing the defects. A tape extender is configured to stretch tape over which the substrate is mounted, singulating the integrated circuits.

Abstract: A substrate dividing method which can thin and divide a substrate while preventing chipping and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within the substrate, so as to form a modified region including a molten processed region due to multiphoton absorption within the semiconductor substrate 1, and causing the modified region including the molten processed region to form a starting point region for cutting; and grinding a rear face 21 of the semiconductor substrate 1 after the step of forming the starting point region for cutting such that the semiconductor substrate 1 attains a predetermined thickness.

Abstract: In embodiments, a hybrid wafer or substrate dicing process involving an initial laser scribe and subsequent plasma etch is implemented for die singulation while also removing an oxidation layer from metal bumps on the wafer. In one embodiment, a method includes forming a mask over the semiconductor wafer covering the plurality of ICs, the plurality of ICs including metal bumps or pads with an oxidation layer. The method includes patterning the mask with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the ICs. The method includes plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the plurality of ICs and remove the oxidation layer from the metal bumps or pads.

Abstract: A semiconductor wafer with modified regions formed in the substrate is provided. A modified region is formed apart from the side of a wafer and a pad is formed over an insulating film, which is formed over the main surface of the substrate of the wafer. Further, the modified region is formed closer to the side surface of the substrate than the pad. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.

Abstract: A semiconductor device includes: a first semiconductor chip; and a second semiconductor chip that is stacked on the first semiconductor chip. The first semiconductor chip includes a first wiring portion of which a side surface is exposed at a side portion of the first semiconductor chip. The second semiconductor chip includes a second wiring portion of which a side surface is exposed at a side portion of the second semiconductor chip. The respective side surfaces of the first wiring portion and the second wiring portion, which are exposed at the side portions of the first semiconductor chip and the second semiconductor chip, are covered by a conductive layer, and the first wiring portion and the second wiring portion are electrically connected to each other through the conductive layer.

Abstract: A wafer processing method divides a wafer into a plurality of individual devices along a plurality of crossing division lines formed on the front side of the wafer. The method includes a functional layer removing step of applying a CO2 laser beam to the wafer along each division line with the spot of the CO2 laser beam, having a width corresponding to the width of each division line set on the upper surface of each division line, thereby removing a functional layer along each division line to form a groove along each division line where the functional layer has been removed, and a groove shaping and debris removing step of applying a laser beam having a wavelength in the ultraviolet region to the wafer along each groove, thereby removing debris sticking to the bottom surface of each groove and also shaping the side walls of each groove.

Abstract: A laser dicing method of a work piece on a surface of which a metal film is provided, includes: a first metal film removing of irradiating a pulse laser beam defocused from the metal film, along a first line, and removing the metal film; a second metal film removing of irradiating the pulse laser beam defocused from the metal film, along a second line orthogonal to the first line, and removing the metal film; and a crack forming of irradiating the pulse laser beam in an area from which the metal film of the work piece is removed, and forming the crack in the work piece, and, in an area in which the first line and the second line cross, irradiation of the pulse laser beam is interrupted in the first metal film removing or the second metal film removing.

Abstract: In one embodiment, a method of forming a semiconductor device comprises forming a groove on and/or over a first side of a substrate. A dicing layer is formed from a second side of the substrate using a laser process. The second side is opposite the first side. The dicing layer is disposed under the groove within the substrate. The substrate is singulated through the dicing layer.

Abstract: In one embodiment, the semiconductor die includes a selective epitaxial layer including device regions, and a masking structure disposed around sidewalls of the epitaxial layer. The masking structure is part of an exposed surface of the semiconductor die.

Abstract: In a wafer dicing press for reducing time and cost for wafer dicing and for evenly applying a dicing pressure to a whole wafer, a wafer dicing press includes a support unit supporting a first side of a wafer; and a pressurization device applying a pressure, by dispersing the pressure, to a second side of the wafer so that a laser-scribed layer of the wafer operates as a division starting point. Accordingly, the wafer dicing press reduces laser radiation and pressure-application times for dividing a wafer into semiconductor devices. This increased efficiency is achieved without increasing the likelihood of damaging the wafer.

Abstract: Microelectronic packages and methods for fabricating microelectronic packages having optical mask layers are provided. In one embodiment, the method includes building redistribution layers over the frontside of a semiconductor die. The redistribution layers includes a body of dielectric material in which a plurality of interconnect lines are formed. An optical mask layer is formed over the frontside of the semiconductor die and at least a portion of the redistribution layers. The optical mask layer has an opacity greater than the opacity of the body of dielectric material and blocks or obscures visual observation of an interior portion of the microelectronic package through the redistribution layers.

Abstract: An integrated, integrated circuit singulation system is provided including scribing a substrate using mechanical cutting or a plurality of passes of laser cutting, and dicing the substrate using mechanical cutting or laser cutting.

Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and separating portions of the backmetal layer within the singulation lines using a pressurized fluid applied to the carrier tape.

Abstract: Embodiments of the present invention provide for the provisioning of efficient support to semiconductor-on-insulator (SOI) structures. Embodiments of the present invention may additionally provide for SOI structures with improved heat dissipation performance while preserving the beneficial electrical device characteristics that accompany SOI architectures. In one embodiment, an integrated circuit is disclosed. The integrated circuit comprises a silicon-on-insulator die from a silicon-on-insulator wafer. The silicon on insulator die comprises an active layer, an insulator layer, a substrate, and a strengthening layer. The substrate consists of an excavated substrate region, and a support region, the support region is in contact with the insulator layer. The support region and the strengthening layer are configured to act in combination to provide a majority of a required stabilizing force to the silicon-on-insulator die when it is singulated from the silicon-on-insulator wafer.

Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.

Abstract: A method of manufacturing a semiconductor device includes providing a carrier including a first layer, a second layer, a first surface of the first layer and a second surface of the second layer, disposing a plurality of solder bumps on the second surface, disposing a molding between the plurality of solder bumps and over the second surface, cutting the first layer to form a first recess in the first layer, wherein the first recess is above a position between at least two of the plurality of solder bumps, and cutting the molding from a bottom surface of the first recess to form a second recess in the molding between the at least two of the plurality of solder bumps.

Abstract: In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer.

Abstract: After performing a dividing step to divide a wafer into individual chips, an irradiation step is performed to apply ultraviolet radiation or plasma to the mount side of each chip, thereby generating ozone and active oxygen, which functions to remove organic matter sticking to the mount side of each chip. Accordingly, it is possible to remove from the mount side of each chip not only foreign matter sticking to the wafer during handling the wafer, but also foreign matter generated in dividing the wafer, so that faulty mounting of each chip can be reduced.

Abstract: A semiconductor device includes a trench transistor cell array in a silicon semiconductor body with a first main surface and a second main surface opposite to the first main surface. A main lateral face of the semiconductor body between the first main surface and the second main surface has a first length along a first lateral direction parallel to the first and second main surfaces. The first length is equal or greater than lengths of other lateral faces of the semiconductor body. The trench transistor cell array includes predominantly linear gate trench portions. At least 50% of the linear gate trench portions extend along a second lateral direction or perpendicular to the second lateral direction. An angle between the first and second lateral directions is in a range of 45°±15°.

Abstract: A method for forming a semiconductor gate structure and a semiconductor gate structure are provided. The method includes: providing a substrate with a Ge layer as a surface thereof; forming a Sn layer on the Ge layer, in which an interface between the Ge layer and the Sn layer is a GeSn layer; removing the Sn layer to expose the GeSn layer; forming a GeSnOx passivation layer by performing an oxidation treatment for the GeSn layer, or forming a GeSnN or GeSnON passivation layer by performing a passivation treatment for the GeSn layer; and forming a gate stack on the GeSnOx , GeSnN or GeSnON passivation layer.

Abstract: Approaches for protecting a wafer during plasma etching wafer dicing processes are described. In an example, a method of dicing a semiconductor wafer with a front surface having a plurality of integrated circuits thereon involves laminating a pre-patterned mask on the front surface of the semiconductor wafer. The pre-patterned mask covers the integrated circuits and exposes streets between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the streets to singulate the integrated circuits. The pre-patterned mask protects the integrated circuits during the plasma etching.

Abstract: A semiconductor element is formed on a first surface of the substrate. A resin layer is formed over a second surface of the substrate which is opposite to the first surface of the substrate and on a part of the side surface of the substrate. A step is formed on the side surface of the substrate. The width of the upper section of the substrate with a step is narrower than the lower section of the substrate with a step. Therefore, the substrate can also be a protrusion.

Abstract: A graphene device may include a channel layer including graphene, a first electrode and second electrode on a first region and second region of the channel layer, respectively, and a capping layer covering the channel layer and the first and second electrodes. A region of the channel layer between the first and second electrodes is exposed by an opening in the capping layer. A gate insulating layer may be on the capping layer to cover the region of the channel layer, and a gate may be on the gate insulating layer.

Abstract: A discrete Through-Assembly Via (TAV) module includes a substrate, and vias extending from a surface of the substrate into the substrate. The TAV module is free from conductive features in contact with one end of each of the conductive vias.

Abstract: In one aspect of the present invention, a method of sawing a semiconductor wafer will be described. A semiconductor wafer is positioned in a wafer sawing apparatus that includes a sawing blade and a movable support structure that physically supports the semiconductor wafer. The semiconductor wafer is coupled with the support structure with various layers, including a dicing tape and an anchoring material. The anchoring material and the wafer are cut with the sawing blade. During the cutting operation, the anchoring material reduces backside chipping of the die and eliminates fly-away die. Various aspects of the present invention relate to arrangements and a wafer sawing apparatus that involve the aforementioned sawing method.

Abstract: A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor wafer having a thick portion in an outer circumferential end portion and a thin portion in a central portion, attaching a support material to one surface of the semiconductor wafer, dividing the semiconductor wafer into the thick portion and the thin portion, and cutting the thin portion, after the division, while supporting the thin portion by the support material.

Abstract: The present invention provides a semiconductor wafer, semiconductor package and semiconductor process. The semiconductor wafer includes a substrate, at least one metal segment and a plurality of dielectric layers. The semiconductor wafer is defined as a plurality of die areas and a plurality of trench areas, each of the die areas has an integrated circuit including a plurality of patterned metal layers disposed between the dielectric layers. The trench areas are disposed between the die areas, and the at least one metal segment is disposed in the trench area and insulated from the integrated circuit of the die area.

Abstract: Approaches for patterning semiconductor or other wafers and dies are described. For example, a method of patterning features within a substrate involves forming a mask layer above a surface of a semiconductor or glass substrate. The method also involves laser ablating the mask layer to provide a pattern of openings through the mask layer. The method also involves plasma etching portions of the semiconductor or glass substrate through the pattern of openings to provide a plurality of trenches in the semiconductor or glass substrate. The plurality of trenches has a pattern corresponding to the pattern of openings and comprising a pattern of through-substrate-via openings or redistribution layer (RDL) openings. The method also involves, subsequent to the plasma etching, removing the mask layer.

Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.

Abstract: A method includes providing a semiconductor wafer including multiple semiconductor chips, forming a first scribe line on a frontside of the semiconductor wafer, wherein the first scribe line has a first width and separates semiconductor chips of the semiconductor wafer, forming a second scribe line on the frontside of the semiconductor wafer, wherein the second scribe line has a second width and separates semiconductor chips of the semiconductor wafer, wherein the first scribe line and the second scribe line intersect in a crossing area which is greater than a product of the first width and the second width, and plasma etching the semiconductor wafer in the crossing area.

Abstract: A dicing/die bonding integral film of the present invention includes a base film, a pressure-sensitive adhesive layer which is formed on the base film and to which a wafer ring for blade dicing is bonded, and a bonding layer formed on the adhesive layer and having a central portion to which a semiconductor wafer to be diced is bonded, wherein a planar shape of the bonding layer is circular, an area of the bonding layer is greater than an area of the semiconductor wafer and smaller than an area of each of the base film and the adhesive layer, and a diameter of the bonding layer is greater than a diameter of the semiconductor wafer and less than an inner diameter of the wafer ring, and a difference in diameter between the bonding layer and the semiconductor wafer is greater than 20 mm and less than 35 mm.

Abstract: Various methods and apparatuses are provided relating to separation of a substrate into a plurality of parts. For example, first a partial separation is performed and then the partially separated substrate is completely separated into a plurality of parts.

Abstract: A separating device separates a chip mounted on a substrate through a connecting material, from the substrate. The separating device includes a heating unit that heats the substrate at a temperature less than a melting point of the connecting material.

Abstract: A method for producing singulated semiconductor components includes providing a starting substrate. An etching process is carried out to form depressions at a side of the starting substrate. The depressions are arranged in the region of the semiconductor components to be produced. Walls present between the depressions are arranged in the region of separating regions provided for severing the starting substrate. The method furthermore comprises forming a metallic layer on the side of the starting substrate with the depressions and walls and carrying out a further etching process for severing the starting substrate in the separating regions and forming the singulated semiconductor components.

Abstract: An electronic circuit unit includes a circuit substrate having a rectangular shape and is obtained by cutting an integral substrate along a vertical cut line and a horizontal cut line to be separated; a copper foil land soldered to components; and a substrate outer edge, which is formed by cutting, of two sides orthogonal to each other. The copper foil land and the substrate outer edge are positioned in the vicinity of a corner of the circuit substrate. Solder resist is provided around the copper foil land. A plurality of substrate exposure portions without the solder resist is provided in the vicinity of the substrate outer edge.

Abstract: Provided is a novel method for forming a groove composed of two smooth inclined surfaces on a surface of a flat plate formed of a nitride semiconductor crystal having an A, C, M-axes. In the present invention, a disk-shaped dicing blade is moved along a direction of the A-axis to form first and second inclined surfaces on the surface of the flat plate. The following mathematical formulae (I)-(III) are satisfied: 45 degrees??b?a?60 degrees (I) 45 degrees??b+a?60 degrees (II), 0 degrees?|a|?7.5 degrees, where angle ?b represents an angle formed between a surface of the edge and a radial direction of the dicing blade in a cross-sectional view which includes the M-axis and the C-axis. The angle a represents an angle formed between the principal surface and the M-axis.

Abstract: In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer.

Abstract: A method of processing wafers for saving material and protecting environment is implemented to collect defective or incomplete wafers and perform cutting operation to create a plurality of separate dies. According to the requirement of a specification, the backs of the dies are grinded to allow each die to have a predetermined thickness. Thereafter, the grinded dies with completeness are sequentially placed onto a carrying means. With the method, the defective or incomplete wafers, which would be discarded in general wafer manufacturing, may be reclaimed to go through cutting, grinding, and selecting operations, so that the dies with completeness on the defective wafers can be picked out and processed again, so as to increase the yield, lower the manufacturing cost, reduce the amount of the wafer waste, increase the wafer utilization, and meet the demands of energy saving, carbon reduction, and environmental protection.

Abstract: A method to prevent contamination of the principal surface side in a process of grinding the back surface side of a semiconductor wafer. At an intersection of a scribe region of a semiconductor wafer whose back surface side is to be ground, a plurality of insulating layers is laminated over the principal surface in the same manner as an insulating layer constituting a wiring layer laminated over a device region. Moreover, in the same layer as an uppermost wiring disposed at the uppermost layer among a plurality of the wiring layers formed for a device region, a metal pattern is formed. Furthermore, a second insulating layer covering the uppermost wiring is also formed over the metal pattern so as to cover the same.

Abstract: A method for manufacturing an SOI wafer includes performing a flattening heat treatment on an SOI wafer under an atmosphere containing an argon gas, in which conditions of SOI wafer preparation are set so that a thickness of an SOI layer of the SOI wafer to be subjected to the flattening heat treatment is 1.4 or more times thicker than that of a BOX layer, and the thickness of the SOI layer is reduced to less than a thickness 1.4 times the thickness of the BOX layer by performing a sacrificial oxidation treatment on the SOI layer of the SOI wafer after the flattening heat treatment.

Abstract: A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A recessed portion is formed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer. Then, a protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion.

Abstract: A singulated semiconductor structure comprises a molding compound; a first conductive post in the molding compound having a first geometric shape in a top view; a second conductive post or an alignment mark in the molding compound having a second geometric shape in a top view, wherein the second geometric shape is different from the first geometric shape. The second conductive post or an alignment mark can be positioned at the corner, the center, the edge, or the periphery of the singulated semiconductor structure. The second geometric shape can be any geometric construct distinguishable from the first geometric shape. The second conductive post or an alignment mark can be placed at an active area or a non-active area of the singulated semiconductor structure.

Abstract: In a splitting method for an optical device wafer, the wafer having optical devices formed individually in regions partitioned by a plurality of crossing scheduled splitting lines provided on a front surface and having a reflective film formed on a reverse surface, a focal point of a laser beam is positioned to the inside of the optical device wafer and the laser beam is irradiated along the scheduled splitting lines from the reverse surface side of the wafer to form modification layers in the inside of the wafer. An external force is applied to the wafer to split the wafer along the scheduled splitting lines and form a plurality of optical device chips. The laser beam has a wavelength that produces transmittance through the reflective film equal to or higher than 80%.

Abstract: An optical device processing method including: a groove forming step of forming a plurality of grooves on a front side of a sapphire substrate; a film forming step of forming an epitaxial film on the front side of the sapphire substrate after performing the groove forming step, thereby forming a plurality of optical devices and a plurality of crossing division lines for partitioning the optical devices; and a dividing step of dividing the sapphire substrate with the epitaxial film along the division lines after performing the film forming step, thereby obtaining a plurality of individual optical device chips.

Abstract: A laser processing method is provided, which, even when a substrate formed with a laminate part including a plurality of functional devices is thick, can cut the substrate and laminate part with a high precision. This laser processing method irradiates a substrate 4 with laser light L while using a rear face 21 as a laser light entrance surface and locating a light-converging point P within the substrate 4, so as to form modified regions 71, 72, 73 within the substrate 4. Here, the HC modified region 73 is formed at a position between the segmented modified region 72 closest to the rear face 21 and the rear face 21, so as to generate a fracture 24 extending along a line to cut from the HC modified region 73 to the rear face 21.

Abstract: A method for cutting a semiconductor wafer into semiconductor chips that reduces defects at the semiconductor chip corners. The method includes a pre-cutting processing step of trimming the semiconductor chip corners so that mechanical stress is reduced at the corners. The method includes dicing channels on a semiconductor wafer thereby defining the geometrical shape of one of the semiconductor chips, modifying the corners of the one of the semiconductor chips, and cutting the semiconductor wafer to separate the one of the semiconductor chips from other semiconductor chips.