Heterojunction Patents (Class 438/47)
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Patent number: 12132145Abstract: A method of manufacturing a nitride semiconductor light-emitting element includes: growing an n-side superlattice layer that includes InGaN layers and GaN layers; and, after the step of growing the n-side superlattice layer, growing a light-emitting layer. The step of growing the n-side superlattice layer comprises repeating a cycle n times (n is a number of repetition), the cycle including growing one InGaN layer and growing one GaN layer. In the step of growing the n-side superlattice layer, the step of growing one GaN layer in each cycle from a first cycle to an mth cycle is performed using carrier gas that contains N2 gas and does not contain H2 gas. The step of growing one GaN layer in each cycle from a (m+1)th cycle to an nth cycle is performed using gas containing H2 gas as the carrier gas.Type: GrantFiled: June 25, 2021Date of Patent: October 29, 2024Assignee: NICHIA CORPORATIONInventor: Tomoya Yamashita
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Patent number: 12107113Abstract: InxAlyGa1-x-yN semiconductor structures having optoelectronic elements characterized by epitaxial layers having different in-plane a-lattice parameters and different InN mole fractions are disclosed. The active regions are configured to emit radiation in different wavelength ranges and are characterized by strain states within about 1% to 2% of compressive strain. The epitaxial layers are grown on patterned InxAlyGa1-x-yN seed regions on a single substrate, where the relaxed InGaN growth layers provide (0001) InxAlyGa1-x-yN growth surfaces characterized by different in-plane a-lattice parameters and different InN mole fractions. InxAlyGa1-x-yN semiconductor structures can be used in optoelectronic devices such as in light sources for illumination and in display applications.Type: GrantFiled: December 29, 2023Date of Patent: October 1, 2024Assignee: OPNOVIX CORP.Inventor: Michael R. Krames
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Patent number: 12057332Abstract: A photoresist material is deposited, patterned, and developed on a backside of a wafer to expose specific regions on the backside of chips for etching. These specific regions are etched to form etched regions through the backside of the chips to a specified depth within the chips. The specified depth may correspond to an etch stop material. Etching of the backside of the wafer can also be done along the chip kerf regions to reduce stress during singulation/dicing of individual chips from the wafer. Etching of the backside of the chips can be done with the chips still part of the intact wafer. Or, the wafer having the pattered and developed photoresist on its backside can be singulated/diced before etching through the backside of the individual chips. The etched region(s) formed through the backside of a chip can be used for attachment of optical component(s) to the chip.Type: GrantFiled: July 10, 2017Date of Patent: August 6, 2024Assignee: Ayar Labs, Inc.Inventors: Chen Sun, Roy Edward Meade, Mark Wade, Alexandra Wright, Vladimir Stojanovic
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Patent number: 12040424Abstract: A process for fabricating a growth substrate comprises preparing a donor substrate by forming a crystalline semiconductor surface layer on a seed layer of a carrier. This preparation comprises forming the surface layer as a plurality of alternations of an InGaN primary layer and of an AlGaN secondary layer, the indium concentration and the thickness of the primary layers and the aluminum concentration and the thickness of the secondary layers being selected so that a homogeneous AlInGaN layer that is equivalent, in terms of concentration of aluminum and indium, to the surface layer has a natural lattice parameter different from the lattice parameter of the seed layer.Type: GrantFiled: November 29, 2019Date of Patent: July 16, 2024Assignee: SoitecInventors: Jean-Marc Bethoux, Mariia Rozhavskaia
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Patent number: 12027568Abstract: A device including first and second light-emitting cells respectively emitting in first and second wavelength ranges, wherein: each cell includes a stack of a first layer of a first semiconductor material and of a second layer of a second semiconductor material having a different mesh parameter; in the first cell, the first layer is in contact with the second layer across the entire surface of the cell; and in the second cell, a mask provided with a plurality of through nano-openings forms an interface between the first layer and the second layer, the second layer comprising a plurality of nanopillars of the second material arranged in the nano-openings of the mask, and a coalesced layer extending across substantially the entire surface of the cell on the side of the mask opposite to the first layer.Type: GrantFiled: December 3, 2019Date of Patent: July 2, 2024Assignee: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventor: Matthew Charles
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Patent number: 11939700Abstract: In various embodiments, single-crystal aluminum nitride boules and substrates are formed from the vapor phase with controlled levels of impurities such as carbon. Single-crystal aluminum nitride may be heat treated via quasi-isothermal annealing and controlled cooling to improve its ultraviolet absorption coefficient and/or Urbach energy.Type: GrantFiled: October 8, 2021Date of Patent: March 26, 2024Assignee: Crystal IS, Inc.Inventors: Robert T. Bondokov, James R. Grandusky, Jianfeng Chen, Shichao Wang, Toru Kimura, Thomas Miebach, Keisuke Yamaoka, Leo J. Schowalter
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Patent number: 11929442Abstract: A semiconductor structure includes a group IV substrate including group IV dies separated by a scribe line. A group IIIV-chiplet is situated over the group IV substrate at least partially over the scribe line. A group III-V process control monitoring device in the group III-V chiplet is situated over the scribe line. Functional group III-V optoelectronic devices can be situated over the group IV dies.Type: GrantFiled: February 17, 2020Date of Patent: March 12, 2024Assignee: Newport Fab, LLCInventor: Edward Preisler
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Patent number: 11917849Abstract: A quantum dot light emitting diode and a method for fabricating the same. The quantum dot light emitting diode includes: a substrate, a bottom electrode, a light-emitting function layer, and a top electrode. A functional layer is formed by the bottom electrode, the light-emitting function layer, and the top electrode; and an outer surface of the functional layer is provided with a first protective layer. The first protective layer is made from a fluoro-acrylate copolymer, which has hydrophobicity, good light transmittance, flexibility, and heat dissipation, and can effectively prevent moisture and oxygen from penetrating into an internal structure of the quantum dot light emitting diode, thereby having a good protection effect, and in the meanwhile, the quantum dot light emitting diode can dissipate heat timely, which is beneficial for the device to keep its performance, improve light-emitting efficiency, and the service life.Type: GrantFiled: March 14, 2018Date of Patent: February 27, 2024Assignee: TCL TECHNOLOGY GROUP CORPORATIONInventors: Chengyu Yang, Yixing Yang
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Patent number: 11888089Abstract: A light emitting element includes an n-side nitride semiconductor layer; an active layer disposed on the n-side nitride semiconductor layer and including a plurality of nitride semiconductor well layers and a plurality of nitride semiconductor barrier layers, the active layer being configured to emit ultraviolet light; and a p-side nitride semiconductor layer disposed on the active layer. At least one of the plurality of barrier layers including, successively from the n-side nitride semiconductor layer side, a first barrier layer containing Al and Ga, and a second barrier layer disposed in contact with the first barrier layer, containing Al, Ga, and In, and having a smaller band gap energy than the first barrier layer. At least one of the plurality of well layers is disposed in contact with a second barrier layer and has a smaller band gap energy than the second barrier layer.Type: GrantFiled: May 25, 2021Date of Patent: January 30, 2024Assignee: NICHIA CORPORATIONInventor: Hiroki Kondo
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Patent number: 11862937Abstract: Optical devices having a structured active region configured for selected wavelengths of light emissions are disclosed.Type: GrantFiled: November 10, 2020Date of Patent: January 2, 2024Assignee: KYOCERA SLD Laser, Inc.Inventor: James W. Raring
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Patent number: 11854802Abstract: The present invention discloses a super-flexible transparent semiconductor film and a preparation method thereof, the method includes: providing an epitaxial substrate; growing a sacrificial layer on the epitaxial substrate; stacking and growing at least one layer of Al1-nGanN epitaxial layer on the sacrificial layer, wherein 0<n?1; growing a nanopillar array containing GaN materials on the Al1-nGanN epitaxial layer; etching the sacrificial layer so as to peel off an epitaxial structure on the sacrificial layer as a whole; and transferring the epitaxial structure after peeling onto a surface of the flexible transparent substrate. Compared to traditional planar films, the present invention can not only improve the crystal quality by releasing stress, but also improve flexibility and transparency through characteristics of the nanopillar materials.Type: GrantFiled: April 3, 2020Date of Patent: December 26, 2023Assignee: Suzhou Institute of Nano-Tech and Nano-Bionics (Sinano), Chinese Academy of SciencesInventors: Yukun Zhao, Shulong Lu, Zhiwei Xing, Jianya Zhang
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Patent number: 11818450Abstract: A camera system includes a light source having a peak emission wavelength at room temperature in a near-infrared region, and an imaging device including a photoelectric conversion element that converts near-infrared light into an electric charge. An external quantum efficiency of the photoelectric conversion element has a first peak at a first wavelength longer than the peak emission wavelength, and the external quantum efficiency at the first wavelength is higher than the external quantum efficiency at the peak emission wavelength.Type: GrantFiled: October 27, 2022Date of Patent: November 14, 2023Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hiroaki Iijima, Masaya Hirade, Yuko Kishimoto
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Patent number: 11810783Abstract: A gallium nitride semiconductor device includes: a chip formation substrate made of gallium nitride and having one surface and an other surface opposite to the one surface; a one surface side element component disposed on the one surface and providing a component of an one surface side of a semiconductor element; and a metal film constituting a back surface electrode in contact with the other surface. The other surface has an irregularity provided by a plurality of convex portions with a trapezoidal cross section and a plurality of concave portions located between the convex portions; and an upper base surface of the trapezoidal cross section in each of the plurality of convex portions is opposed to the one surface.Type: GrantFiled: April 13, 2021Date of Patent: November 7, 2023Assignees: DENSO CORPORATION, HAMAMATSU PHOTONICS K.K., National University Corporation Tokai National Higher Education and Research SystemInventors: Chiaki Sasaoka, Jun Kojima, Shoichi Onda, Masatake Nagaya, Kazukuni Hara, Daisuke Kawaguchi
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Patent number: 11715813Abstract: A light emitting diode (LED) structure includes a semiconductor template having a template top-surface, an active quantum well (QW) structure formed over the semiconductor template, and a p-type layer. The p-type layer has a bottom-surface that faces the active QW and the template top-surface. The bottom-surface includes a recess sidewall. The recess sidewall of the p-type layer is configured for promoting injection of holes into the active QW structure through a QW sidewall of the active QW structure.Type: GrantFiled: May 19, 2021Date of Patent: August 1, 2023Assignee: GOOGLE LLCInventors: Benjamin Leung, Miao-Chan Tsai
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Patent number: 11651954Abstract: A method for porosifying a Ill-nitride material in a semiconductor structure is provided, the semiconductor structure comprising a sub-surface structure of a first Ill-nitride material, having a charge carrier density greater than 5×1017 cm?3, beneath a surface layer of a second Ill-nitride material, having a charge carrier density of between 1×1014 cm?3 and 1×1017 cm?3. The method comprises the steps of exposing the surface layer to an electrolyte, and applying a potential difference between the first Ill-nitride material and the electrolyte, so that the sub-surface structure is porosified by electrochemical etching, while the surface layer is not porosified. A semiconductor structure and uses thereof are further provided.Type: GrantFiled: September 27, 2017Date of Patent: May 16, 2023Assignee: CAMBRIDGE ENTERPRISE LTDInventors: Tongtong Zhu, Rachel A. Oliver, Yingjun Liu
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Patent number: 11641006Abstract: Disclosed in an embodiment is a semiconductor device comprising: a semiconductor structure comprising a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer disposed between the first conductive type semiconductor layer and the second conductive type semiconductor layer; a second electrode electrically connected to the second conductive type semiconductor layer; and a reflective layer disposed under the second electrode, wherein the second conductive type semiconductor layer comprises a first sub-layer and a second sub-layer disposed between the first sub-layer and the active layer and having an aluminum (Al) composition higher than that of the first sub-layer, the reflective layer comes into contact with the lower surface of the second sub-layer, and the second electrode comes into contact with the first sub-layer.Type: GrantFiled: March 22, 2019Date of Patent: May 2, 2023Assignee: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.Inventors: Youn Joon Sung, Min Sung Kim
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Patent number: 11591270Abstract: A method for forming ceramic matrix composite (CMC) component includes forming a fiber preform, positioning the fiber preform into a chemical vapor infiltration reactor chamber, and densifying the fiber preform. Densification includes infiltrating the fiber preform with a first gas comprising precursors of silicon carbide and infiltrating the fiber preform with a second gas comprising a first rare earth element, wherein the steps of infiltrating the fiber preform with the first gas and infiltrating the fiber preform with the second gas are conducted simultaneously to produce a first rare earth-doped silicon carbide matrix in a first region of the component.Type: GrantFiled: February 7, 2020Date of Patent: February 28, 2023Assignee: Raytheon Technologies CorporationInventors: Ying She, Andrew J. Lazur, Kathryn S. Read
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Patent number: 11581701Abstract: Provided is a nitride semiconductor laser element which includes: a stacked structure including a plurality of semiconductor layers including a light emitting layer, the stacked structure including a pair of resonator end faces located on opposite ends; and a protective film including a dielectric body and disposed on at least one of the pair of resonator end faces. The protective film includes a first protective film (a first emission surface protective film), a second protective film (a second emission surface protective film), and a third protective film (a third emission surface protective film) disposed in stated order above the stacked structure. The first protective film is amorphous, the second protective film is crystalline, and the third protective film is amorphous.Type: GrantFiled: August 13, 2020Date of Patent: February 14, 2023Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Hideo Kitagawa, Shinji Yoshida, Isao Kidoguchi
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Patent number: 11569408Abstract: In some embodiments, a semiconductor structure comprises a semiconductor layer, a metal layer, and a contact layer adjacent to the metal layer, and between the semiconductor layer and the metal layer. The contact layer can comprise one or more piezoelectric materials comprising spontaneous piezoelectric polarization that depends on material composition and/or strain, and a region comprising a gradient in materials composition and/or strain adjacent to the metal layer. In some embodiments, a light emitting diode (LED) device comprises an n-doped short period superlattice (SPSL) layer, an intrinsically doped AlN/GaN SPSL layer adjacent to the n-doped SPSL layer, a metal layer, and an ohmic-chirp layer between the metal layer and the intrinsically doped AlN/GaN SPSL layer.Type: GrantFiled: December 17, 2020Date of Patent: January 31, 2023Assignee: Silanna UV Technologies Pte LtdInventors: Guilherme Tosi, Norbert Krause
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Patent number: 11523037Abstract: A camera system includes a light source having a peak emission wavelength at room temperature in a near-infrared region, and an imaging device including a photoelectric conversion element that converts near-infrared light into an electric charge. An external quantum efficiency of the photoelectric conversion element has a first peak at a first wavelength longer than the peak emission wavelength, and the external quantum efficiency at the first wavelength is higher than the external quantum efficiency at the peak emission wavelength.Type: GrantFiled: April 15, 2021Date of Patent: December 6, 2022Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hiroaki Iijima, Masaya Hirade, Yuko Kishimoto
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Patent number: 11462659Abstract: Provided is a semiconductor light emitting device including a growth substrate; a pillar-shaped semiconductor layer formed on the growth substrate; and a buried semiconductor layer formed to cover the pillar-shaped semiconductor layer, wherein the pillar-shaped semiconductor layer has an n-type nanowire layer formed at a center, an active layer formed on an outermore side than the n-type nanowire layer, a p-type semiconductor layer formed on an outermore side than the active layer and a tunnel junction layer formed on an outermore side than the p-type semiconductor layer, and wherein at least a part of the pillar-shaped semiconductor layer is provided with a removed region formed by removing from the buried semiconductor layer to a part of the tunnel junction layer.Type: GrantFiled: September 9, 2020Date of Patent: October 4, 2022Assignees: KOITO MANUFACTURING CO., LTD., MEIJO UNIVERSITY, TOYODA GOSEI CO., LTD.Inventors: Satoshi Kamiyama, Tetsuya Takeuchi, Motoaki Iwaya, Isamu Akasaki, Lu Weifang, Naoki Sone, Kazuyoshi Iida, Ryo Nakamura, Masaki Oya
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Patent number: 11398464Abstract: A micro light emitting element includes: a body including a compound semiconductor layer in which a first conductive layer, a light emission layer, and a second conductive layer with a conductive type opposite to a conductive type of the first conductive layer are stacked in order from a light emitting surface side; a first electrode including a transparent electrode on the light emitting surface side; a second electrode including a metal film on a side opposite to the light emitting surface side; and a first reflective material covering a side surface of the body. The light emission layer is disposed on the light emitting surface side of the body. The side surface of the body is tapered at an inclination angle to open in a light emitting direction.Type: GrantFiled: July 14, 2020Date of Patent: July 26, 2022Assignee: Sharp Fukuyama Laser Co., Ltd.Inventors: Katsuji Iguchi, Hidenori Kawanishi
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Patent number: 11390800Abstract: Disclosed is a zinc oxide-based quantum dot aggregate capable of emitting white light is a mixture of a zinc oxide quantum dot and a zinc oxide-graphene quantum dot, in which the zinc oxide quantum dot emits yellow light when being irradiated with an excitation wavelength shorter than a wavelength corresponding to an energy band gap of the zinc oxide quantum dot, the zinc oxide-graphene quantum dot is in a form in which a zinc oxide quantum dot is bound with graphene via a Zn—O—C bond and emits blue-based light, and white light emission is possible through color rendering of yellow light emission by the zinc oxide quantum dot and blue-based light emission by the zinc oxide-graphene quantum dot.Type: GrantFiled: March 6, 2019Date of Patent: July 19, 2022Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Won-Kook Choi, Hong Hee Kim, Yeonju Lee
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Patent number: 11271023Abstract: A quantum waveguide infrared photodetector includes: a photon absorption layer that receives infrared photons propagating longitudinally along a longitudinal length of the photon absorption layer, converts the infrared photons into electrons, and communicates the electrons to a conductor layer; a first conductor layer that receives a first electrical potential; and a second conductor layer that receives a second electrical potential, wherein electrons produced by the photon absorption layer are communicated from the photon absorption layer: to the first conductor layer when the first electrical potential is more positive than the second electrical potential, and to the second conductor layer when the second electrical potential is more positive than the first electrical potential, an electrical current produced by the electrons is proportional to an amount of absorption of the infrared photons in the photon absorption layer.Type: GrantFiled: July 2, 2020Date of Patent: March 8, 2022Assignee: GOVERNMENT OF THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCEInventor: Eric John Stanton
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Semiconductor laminate, light-receiving element, and method for manufacturing semiconductor laminate
Patent number: 11081605Abstract: A semiconductor laminate includes a substrate formed of a group III-V compound semiconductor and a quantum well structure disposed on the substrate. The quantum well structure includes a second element layer formed of a group III-V compound semiconductor and containing Sb and a first element layer formed of a group III-V compound semiconductor and disposed in contact with the second element layer. In the first element layer, the thickness of a region in which the content of Sb decreases in a direction away from the substrate from 80% of the maximum content of Sb in the second element layer to 6% of the maximum content is from 0.5 nm to 3.0 nm inclusive.Type: GrantFiled: August 24, 2018Date of Patent: August 3, 2021Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Takuma Fuyuki, Tomohiro Doi, Takashi Go, Takashi Ishizuka -
Patent number: 10923346Abstract: A Group III nitride semiconductor for growing a high-quality crystal having a low defect density and a method for producing the Group III nitride semiconductor. The Group III nitride semiconductor includes an RAMO4 substrate including a single crystal represented by the general formula RAMO4 (where R represents one or more trivalent elements selected from the group consisting of Sc, In, Y and lanthanoid elements, A represents one or more trivalent elements selected from the group consisting of Fe(III), Ga and Al, and M represents one or more divalent elements selected from the group consisting of Mg, Mn, Fe(II), Co, Cu, Zn and Cd); a p-type Group III nitride crystal layer disposed on the RAMO4 substrate; a plurality of n-type Group III nitride crystal layers disposed on the p-type Group III nitride crystal layer; and a Group III nitride crystal layer disposed on the n-type Group III nitride crystal layers.Type: GrantFiled: September 6, 2019Date of Patent: February 16, 2021Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Akihiko Ishibashi, Hiroshi Ono, Kenya Yamashita
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Patent number: 10644199Abstract: Provided is a group III nitride stacked body having an n-type AlXGa1-XN (0.5?X<1) layer formed on an AlN single crystal substrate while being lattice-matched to the AlN single crystal substrate wherein the n-type AlXGa1-XN (0.5?X<1) layer has at least a stacked structure in which a first n-type AlX1Ga1-X1N (0.5?X1<1) layer, a second n-type AlX2Ga1-X2N (0.5?X2<1) layer, and a third n-type AlX3Ga1-X3N (0.5?X3<1) layer are stacked in this order from the AlN single crystal substrate side, and X1, X2, and X3 indicating the Al compositions of the respective layers satisfy 0<|X1?X2|?0.1, and satisfy 0<|X2?X3|?0.1.Type: GrantFiled: August 28, 2017Date of Patent: May 5, 2020Assignee: STANLEY ELECTRIC CO., LTD.Inventors: Toru Kinoshita, Toshiyuki Obata
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Patent number: 10535784Abstract: Embodiments include apparatuses and methods related to vertically stacked varactors. Specifically two varactors may be constructed of vertically stacked layers including an anode layer, a contact layer, and a varactor layer. The two varactors may share one or more layers in common. In some embodiments the two varactors may share the anode layer in common, while in other embodiments the two varactors may share the contact layer in common.Type: GrantFiled: February 21, 2018Date of Patent: January 14, 2020Assignee: Qorvo US, Inc.Inventors: Peter V. Wright, Timothy S. Henderson
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Patent number: 10317785Abstract: The invention provides a light emitting apparatus including a projector color wheel and a light emitting diode (LED) device using a composite material, a method of manufacturing the composite material, and an optical film. The stability of the composite material has been greatly improved. Light emitting devices using the composite material have wide color gamut.Type: GrantFiled: August 23, 2018Date of Patent: June 11, 2019Assignee: Unique Materials Co., Ltd.Inventors: Pi-Tai Chou, Shang-Wei Chou
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Patent number: 10297731Abstract: Light emitting diode (LED) constructions comprise an LED having a pair of electrical contacts along a bottom surface. A lens is disposed over the LED and covers a portion of the LED bottom surface. A pair of electrical terminals is connected with respective LED contacts, are sized larger than the contacts, and connect with the lens material along the LED bottom surface. A wavelength converting material may be interposed between the LED and the lens. LED constructions may comprise a number of LEDs, where the light emitted by each LED differs from one another by about 2.5 nm or less. LED constructions are made by attaching 2 or more LEDs to a common wafer by adhesive layer, forming a lens on a wafer level over each LED to provide a rigid structure, removing the common wafer, forming the electrical contacts on a wafer level, and then separating the LEDs.Type: GrantFiled: November 26, 2014Date of Patent: May 21, 2019Assignee: Bridgelux, Inc.Inventors: Vladimir A. Odnoblyudov, R. Scott West
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Patent number: 10297722Abstract: Light emitting diodes and display systems are disclosed. In an embodiment a light emitting diode (150) includes a p-n diode (120) including a mesa structure (129) that protrudes from a base structure (131). A reflective metallization (130) laterally surrounds the mesa structure, which also includes a quantum well layer of the p-n diode.Type: GrantFiled: September 30, 2015Date of Patent: May 21, 2019Assignee: Apple Inc.Inventors: Kevin K. C. Chang, Hsin-Hua Hu, Chien-Hsing Huang
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Patent number: 10236178Abstract: GaN based nanowires are used to grow high quality, discreet base elements with c-plane top surface for fabrication of various semiconductor devices, such as diodes and transistors for power electronics.Type: GrantFiled: May 12, 2017Date of Patent: March 19, 2019Assignee: HEXAGEM ABInventors: Jonas Ohlsson, Mikael Bjork
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Patent number: 10193301Abstract: A method of manufacturing a light emitting device includes: providing a wafer including a conductive first substrate, a laser element structure on an upper side of the first substrate, and an upper surface electrode on an upper surface of the element structure; bonding the wafer to a second substrate at an upper surface electrode side of the wafer; removing a portion of the first substrate to reduce a thickness of the wafer; forming a lower surface electrode on a lower surface of the first substrate at which the removing of the portion of the first substrate has been performed; singulating the wafer to obtain a laser element; and mounting the laser element on a submount such that the lower surface electrode faces the submount.Type: GrantFiled: March 28, 2018Date of Patent: January 29, 2019Assignee: NICHIA CORPORATIONInventors: Shingo Tanisaka, Shingo Masui
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Patent number: 10026751Abstract: A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include one or more transition metal dichalcogenide materials such as MoS2, WS2, WSe2, and/or combinations thereof.Type: GrantFiled: July 14, 2016Date of Patent: July 17, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Titash Rakshit, Borna J. Obradovic, Rwik Sengupta, Wei-E Wang, Ryan Hatcher, Mark S. Rodder
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Patent number: 10002989Abstract: The present invention provides a method for producing a semiconductor light-emitting device in which fine protrusions and recesses are formed on a bottom surface between the protrusions on a surface of a substrate. The method comprises forming a first resist pattern on a nitrogen surface of the substrate, forming a plurality of first protrusions on the nitrogen surface of the substrate, and forming a plurality of second protrusions on the nitrogen surface of the transparent nitride-based substrate. In forming the first protrusions, the plurality of first protrusions and a bottom surface between the first protrusions are formed by dry etching. In forming the second protrusions, the plurality of second protrusions having a height lower than the height of the first protrusions are formed on the bottom surface by wet etching without removing the first resist pattern subjected to dry etching.Type: GrantFiled: March 20, 2017Date of Patent: June 19, 2018Assignee: TOYOTA GOSEI CO., LTD.Inventors: Kimiyasu Ide, Shingo Totani
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Patent number: 9944627Abstract: The present invention relates to compounds of the formula (1), to the use thereof in electroluminescent devices, and particularly organic electroluminescence devices, comprising said compounds according to the invention.Type: GrantFiled: May 9, 2017Date of Patent: April 17, 2018Assignee: NATIONAL TAIWAN UNIVERSITYInventors: Ken-Tsung Wong, Chung-Chih Wu, Tanmay Chatterjee, Ting-An Lin, Wei-Lung Tsai, Meng-Jung Wu
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Patent number: 9842967Abstract: Provided is a nitride semiconductor light emitting element in which deep-level light emission is suppressed, monochromaticity is improved, and light is emitted in a high-efficiency manner. A nitride semiconductor light emitting element having a light-emitting layer between an n-type nitride semiconductor layer and a p-type nitride semiconductor layer, wherein the n-type nitride semiconductor layer contains AlnGa1-nN (0<n?1), and has a C concentration of 1×1017/cm3 or less.Type: GrantFiled: June 13, 2014Date of Patent: December 12, 2017Assignee: USHIO DENKI KABUSHIKI KAISHAInventors: Masashi Tsukihara, Kohei Miyoshi, Toru Sugiyama
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Patent number: 9812607Abstract: There is provided a method for manufacturing a nitride semiconductor template, including the steps of: growing and forming a buffer layer in a thickness of not more than a peak width of a projection and in a thickness of not less than 10 nm and not more than 330 nm on a sapphire substrate formed by arranging conical or pyramidal projections on its surface in a lattice pattern; and growing and forming a nitride semiconductor layer on the buffer layer.Type: GrantFiled: July 8, 2015Date of Patent: November 7, 2017Assignee: SUMITOMO CHEMICAL COMPANY, LIMITEDInventor: Hajime Fujikura
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Patent number: 9806223Abstract: A method for producing an optoelectronic semiconductor chip based on a nitride semiconductor system is specified. The method comprises the steps of: forming a semiconductor section with at least one p-doped region; and forming a covering layer disposed downstream of the semiconductor section in a growth direction of the semiconductor chip, said covering layer having at least one n-doped semiconductor layer. An activation step suitable for electrically activating the p-doped region is effected before or during the formation of the covering layer. An optoelectronic semiconductor chip which can be produced by the method is additionally specified.Type: GrantFiled: January 6, 2011Date of Patent: October 31, 2017Assignee: OSRAM Opto Semiconductors GmbHInventors: Magnus Ahlstedt, Lutz Höppel, Matthias Peter, Matthias Sabathil, Uwe Strauss, Martin Strassburg
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Patent number: 9698305Abstract: A high voltage LED flip chip includes two or more regions; a Mesa-platform, the Mesa-platform in each region has a first groove; a first electrode located on the Mesa-platform, an area between the first electrodes in two adjacent regions forms a second groove; a first insulation layer covering the Mesa-platforms and the first electrodes, the first insulation layer fills the second groove and partially fills the first groove, and a part of the first groove which is not filled forms a third groove; a fourth groove formed in the first insulation layer, the fourth groove exposes a surface of the first electrode; and an interconnection electrode, the interconnection electrode comprises a first portion connecting the first semiconductor layer through the third groove in a particular region with the first electrode through the fourth groove in another region adjacent to the particular region. The LED formed has improved performance.Type: GrantFiled: May 25, 2016Date of Patent: July 4, 2017Assignee: Enraytek Optoelectronics Co., Ltd.Inventors: Huiwen Xu, Yu Zhang, Qiming Li
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Patent number: 9552979Abstract: A process for depositing aluminum nitride is disclosed. The process comprises providing a plurality of semiconductor substrates in a batch process chamber and depositing an aluminum nitride layer on the substrates by performing a plurality of deposition cycles without exposing the substrates to plasma during the deposition cycles. Each deposition cycle comprises flowing an aluminum precursor pulse into the batch process chamber, removing the aluminum precursor from the batch process chamber, and removing the nitrogen precursor from the batch process chamber after flowing the nitrogen precursor and before flowing another pulse of the aluminum precursor. The process chamber may be a hot wall process chamber and the deposition may occur at a deposition pressure of less than 1 Torr.Type: GrantFiled: May 31, 2013Date of Patent: January 24, 2017Assignee: ASM IP HOLDING B.V.Inventors: Werner Knaepen, Bert Jongbloed, Dieter Pierreux, Peter Zagwijn, Hessel Sprey, Cornelius A. van der Jeugd, Marinus Josephus de Blank, Robin Roelofs, Qi Xie, Jan Willem Maes
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Patent number: 9543476Abstract: A UV light emitting diode and a method of fabricating the same are provided. The light emitting diode includes an active area between an n-type nitride-based semiconductor layer and a p-type nitride-based semiconductor layer, wherein the active area includes a plurality of barrier layers containing Al, a plurality of well layers containing Al and alternately arranged with the barrier layer, and at least one conditioning layer. Each conditioning layer is placed between the well layer and the barrier layer adjacent to the well layer and is formed of a binary nitride semiconductor. The design of the conditioning layer can reduce stress of the active area while allowing uniform control of the composition of the well layers and/or the barrier layers.Type: GrantFiled: November 28, 2014Date of Patent: January 10, 2017Assignee: SEOUL VIOSYS CO., LTD.Inventors: Ki Yon Park, Jeong Hun Heo, Hwa Mok Kim, Chang Suk Han, Hyo Shik Choi
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Patent number: 9478708Abstract: A method and structure for integrating gallium nitride into a semiconductor substrate. The method may also include means for isolating the gallium nitride from the semiconductor substrate.Type: GrantFiled: March 11, 2015Date of Patent: October 25, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William J. Gallagher, Effendi Leobandung, Devendra K. Sadana, Ghavam G. Shahidi
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Patent number: 9450124Abstract: A method of forming an integrated circuit employs a plurality of layers supported on a substrate that include i) n-type contact layer, ii) a p-type modulation doped quantum well structure (MDQWS) above the n-type contact layer, iii) n-type MDQWS above the p-type MDQWS, and iv) p-type contact layer(s) above the n-type MDQWS. A feature for a thyristor is defined by a mesa at the p-type contact layer of iv). A first layer of metal is deposited on the feature, which is then etched for at least one other device. Additional layer(s) of metal is deposited on the feature to form cumulative metal layers, which are etched away to form a set of mesas and corresponding electrodes for the thyristor. The cumulative metal layers that cover the feature and contact the mesa at the p-type contact layer of iv) are patterned to form an anode electrode of the thyristor.Type: GrantFiled: June 11, 2015Date of Patent: September 20, 2016Assignees: Opel Solar, Inc., THE UNIVERSITY OF CONNECTICUTInventor: Geoff W. Taylor
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Patent number: 9425349Abstract: A lift-off method transfers an optical device layer of an optical device wafer onto a transfer substrate. The optical device layer is stacked on a front face of an epitaxy substrate with a buffer layer provided therebetween. A complex substrate formation step forms a complex substrate by joining the transfer substrate to a front face of the optical device layer of the optical device wafer with an adhesive. A buffer layer destruction step irradiates a laser beam at a wavelength that penetrates the epitaxy substrate and is absorbed by the buffer layer from a rear side of the epitaxy substrate of the complex substrate so as to destroy the buffer layer. An optical device layer transfer step peels off the epitaxy substrate and transfers the optical device layer onto the transfer substrate.Type: GrantFiled: February 3, 2015Date of Patent: August 23, 2016Assignee: DISCO CORPORATIONInventor: Hiroshi Morikazu
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Patent number: 9391237Abstract: The present invention provides a Group III nitride semiconductor exhibiting reduced contact resistance. A first p-type contact layer of GaN doped with Mg is formed on a p-type cladding layer, using hydrogen as a carrier gas at a growth temperature of 850° C. to 1,050° C., so as to have a thickness of 10 nm to 300 nm. The Mg concentration is 1×1019/cm3 to 1×1020/cm3. Subsequently, a second p-type contact layer of GaN doped with Mg is formed, using nitrogen instead of hydrogen as a carrier gas at a temperature of 600° C. to 800° C. so as to have a thickness of two monolayers to 100 ?. The Mg concentration is 2×1020/cm3 to 1×1021/cm3.Type: GrantFiled: March 3, 2015Date of Patent: July 12, 2016Assignee: Toyoda Gosei Co., Ltd.Inventor: Shinya Boyama
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Patent number: 9368756Abstract: An organic electroluminescence device includes a support substrate, a first transparent electrode on the support substrate, an organic light-emitting layer on the first transparent electrode, a second transparent electrode on the organic light-emitting layer, and a high refractive index layer arranged between the support substrate and the first transparent electrode, having at least one layer having a refractive index greater than or equal to a refractive index of the support substrate, having a light dispersion portion for dispersing incident light from the organic light-emitting layer, and having a planar surface contacting the first transparent electrode.Type: GrantFiled: October 11, 2013Date of Patent: June 14, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ryuichi Satoh, Hiroshi Miyao, Tadao Yagi
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Patent number: 9337039Abstract: The method includes the steps of a) Providing a stack having a support substrate and a film of GaN having dopant species, b) Directly bonding a shielding layer having a thickness higher than 2 micrometers to the surface of the film of GaN, so as to form an activation structure, and c) Applying a thermal budget to the activation structure according to conditions allowing to electrically activate at least one portion of the dopant species.Type: GrantFiled: June 25, 2014Date of Patent: May 10, 2016Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventor: Claire Agraffeil
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Patent number: 9287441Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can prepare a substrate unit including a base substrate, an intermediate crystal layer, and a first mask layer. The intermediate crystal layer has a major surface having a first region, a second region, and a first intermediate region. The first mask layer is provided on the first intermediate region. The method can implement a first growth to grow a first lower layer on the first region and grow a second lower layer on the second region. The first and second lower layers include a semiconductor crystal. The method can implement a second growth to grow a second upper layer while growing a first upper layer to cover the first mask layer with the first and second upper layers. The method can implement cooling to separate the first and second upper layers.Type: GrantFiled: February 28, 2013Date of Patent: March 15, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Jongil Hwang, Rei Hashimoto, Shinji Saito, Hung Hung, Shinya Nunoue
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Patent number: 9276117Abstract: The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes The device includes a strain-relaxed buffer (SRB) stack over a substrate, a first fin structure disposed over the SRB stack and a liner layer extending along the portion of the second SRB layer and the first semiconductor material layer of the first fin structure.Type: GrantFiled: August 19, 2014Date of Patent: March 1, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Pang-Yen Tsai, Tze-Liang Lee