Heterojunction Patents (Class 438/47)
  • Patent number: 11271023
    Abstract: A quantum waveguide infrared photodetector includes: a photon absorption layer that receives infrared photons propagating longitudinally along a longitudinal length of the photon absorption layer, converts the infrared photons into electrons, and communicates the electrons to a conductor layer; a first conductor layer that receives a first electrical potential; and a second conductor layer that receives a second electrical potential, wherein electrons produced by the photon absorption layer are communicated from the photon absorption layer: to the first conductor layer when the first electrical potential is more positive than the second electrical potential, and to the second conductor layer when the second electrical potential is more positive than the first electrical potential, an electrical current produced by the electrons is proportional to an amount of absorption of the infrared photons in the photon absorption layer.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: March 8, 2022
    Inventor: Eric John Stanton
  • Patent number: 11081605
    Abstract: A semiconductor laminate includes a substrate formed of a group III-V compound semiconductor and a quantum well structure disposed on the substrate. The quantum well structure includes a second element layer formed of a group III-V compound semiconductor and containing Sb and a first element layer formed of a group III-V compound semiconductor and disposed in contact with the second element layer. In the first element layer, the thickness of a region in which the content of Sb decreases in a direction away from the substrate from 80% of the maximum content of Sb in the second element layer to 6% of the maximum content is from 0.5 nm to 3.0 nm inclusive.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: August 3, 2021
    Inventors: Takuma Fuyuki, Tomohiro Doi, Takashi Go, Takashi Ishizuka
  • Patent number: 10923346
    Abstract: A Group III nitride semiconductor for growing a high-quality crystal having a low defect density and a method for producing the Group III nitride semiconductor. The Group III nitride semiconductor includes an RAMO4 substrate including a single crystal represented by the general formula RAMO4 (where R represents one or more trivalent elements selected from the group consisting of Sc, In, Y and lanthanoid elements, A represents one or more trivalent elements selected from the group consisting of Fe(III), Ga and Al, and M represents one or more divalent elements selected from the group consisting of Mg, Mn, Fe(II), Co, Cu, Zn and Cd); a p-type Group III nitride crystal layer disposed on the RAMO4 substrate; a plurality of n-type Group III nitride crystal layers disposed on the p-type Group III nitride crystal layer; and a Group III nitride crystal layer disposed on the n-type Group III nitride crystal layers.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: February 16, 2021
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Akihiko Ishibashi, Hiroshi Ono, Kenya Yamashita
  • Patent number: 10644199
    Abstract: Provided is a group III nitride stacked body having an n-type AlXGa1-XN (0.5?X<1) layer formed on an AlN single crystal substrate while being lattice-matched to the AlN single crystal substrate wherein the n-type AlXGa1-XN (0.5?X<1) layer has at least a stacked structure in which a first n-type AlX1Ga1-X1N (0.5?X1<1) layer, a second n-type AlX2Ga1-X2N (0.5?X2<1) layer, and a third n-type AlX3Ga1-X3N (0.5?X3<1) layer are stacked in this order from the AlN single crystal substrate side, and X1, X2, and X3 indicating the Al compositions of the respective layers satisfy 0<|X1?X2|?0.1, and satisfy 0<|X2?X3|?0.1.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: May 5, 2020
    Inventors: Toru Kinoshita, Toshiyuki Obata
  • Patent number: 10535784
    Abstract: Embodiments include apparatuses and methods related to vertically stacked varactors. Specifically two varactors may be constructed of vertically stacked layers including an anode layer, a contact layer, and a varactor layer. The two varactors may share one or more layers in common. In some embodiments the two varactors may share the anode layer in common, while in other embodiments the two varactors may share the contact layer in common.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: January 14, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Peter V. Wright, Timothy S. Henderson
  • Patent number: 10317785
    Abstract: The invention provides a light emitting apparatus including a projector color wheel and a light emitting diode (LED) device using a composite material, a method of manufacturing the composite material, and an optical film. The stability of the composite material has been greatly improved. Light emitting devices using the composite material have wide color gamut.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: June 11, 2019
    Assignee: Unique Materials Co., Ltd.
    Inventors: Pi-Tai Chou, Shang-Wei Chou
  • Patent number: 10297731
    Abstract: Light emitting diode (LED) constructions comprise an LED having a pair of electrical contacts along a bottom surface. A lens is disposed over the LED and covers a portion of the LED bottom surface. A pair of electrical terminals is connected with respective LED contacts, are sized larger than the contacts, and connect with the lens material along the LED bottom surface. A wavelength converting material may be interposed between the LED and the lens. LED constructions may comprise a number of LEDs, where the light emitted by each LED differs from one another by about 2.5 nm or less. LED constructions are made by attaching 2 or more LEDs to a common wafer by adhesive layer, forming a lens on a wafer level over each LED to provide a rigid structure, removing the common wafer, forming the electrical contacts on a wafer level, and then separating the LEDs.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: May 21, 2019
    Assignee: Bridgelux, Inc.
    Inventors: Vladimir A. Odnoblyudov, R. Scott West
  • Patent number: 10297722
    Abstract: Light emitting diodes and display systems are disclosed. In an embodiment a light emitting diode (150) includes a p-n diode (120) including a mesa structure (129) that protrudes from a base structure (131). A reflective metallization (130) laterally surrounds the mesa structure, which also includes a quantum well layer of the p-n diode.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: May 21, 2019
    Assignee: Apple Inc.
    Inventors: Kevin K. C. Chang, Hsin-Hua Hu, Chien-Hsing Huang
  • Patent number: 10236178
    Abstract: GaN based nanowires are used to grow high quality, discreet base elements with c-plane top surface for fabrication of various semiconductor devices, such as diodes and transistors for power electronics.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: March 19, 2019
    Assignee: HEXAGEM AB
    Inventors: Jonas Ohlsson, Mikael Bjork
  • Patent number: 10193301
    Abstract: A method of manufacturing a light emitting device includes: providing a wafer including a conductive first substrate, a laser element structure on an upper side of the first substrate, and an upper surface electrode on an upper surface of the element structure; bonding the wafer to a second substrate at an upper surface electrode side of the wafer; removing a portion of the first substrate to reduce a thickness of the wafer; forming a lower surface electrode on a lower surface of the first substrate at which the removing of the portion of the first substrate has been performed; singulating the wafer to obtain a laser element; and mounting the laser element on a submount such that the lower surface electrode faces the submount.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: January 29, 2019
    Inventors: Shingo Tanisaka, Shingo Masui
  • Patent number: 10026751
    Abstract: A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include one or more transition metal dichalcogenide materials such as MoS2, WS2, WSe2, and/or combinations thereof.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: July 17, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Titash Rakshit, Borna J. Obradovic, Rwik Sengupta, Wei-E Wang, Ryan Hatcher, Mark S. Rodder
  • Patent number: 10002989
    Abstract: The present invention provides a method for producing a semiconductor light-emitting device in which fine protrusions and recesses are formed on a bottom surface between the protrusions on a surface of a substrate. The method comprises forming a first resist pattern on a nitrogen surface of the substrate, forming a plurality of first protrusions on the nitrogen surface of the substrate, and forming a plurality of second protrusions on the nitrogen surface of the transparent nitride-based substrate. In forming the first protrusions, the plurality of first protrusions and a bottom surface between the first protrusions are formed by dry etching. In forming the second protrusions, the plurality of second protrusions having a height lower than the height of the first protrusions are formed on the bottom surface by wet etching without removing the first resist pattern subjected to dry etching.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: June 19, 2018
    Assignee: TOYOTA GOSEI CO., LTD.
    Inventors: Kimiyasu Ide, Shingo Totani
  • Patent number: 9944627
    Abstract: The present invention relates to compounds of the formula (1), to the use thereof in electroluminescent devices, and particularly organic electroluminescence devices, comprising said compounds according to the invention.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: April 17, 2018
    Inventors: Ken-Tsung Wong, Chung-Chih Wu, Tanmay Chatterjee, Ting-An Lin, Wei-Lung Tsai, Meng-Jung Wu
  • Patent number: 9842967
    Abstract: Provided is a nitride semiconductor light emitting element in which deep-level light emission is suppressed, monochromaticity is improved, and light is emitted in a high-efficiency manner. A nitride semiconductor light emitting element having a light-emitting layer between an n-type nitride semiconductor layer and a p-type nitride semiconductor layer, wherein the n-type nitride semiconductor layer contains AlnGa1-nN (0<n?1), and has a C concentration of 1×1017/cm3 or less.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: December 12, 2017
    Inventors: Masashi Tsukihara, Kohei Miyoshi, Toru Sugiyama
  • Patent number: 9812607
    Abstract: There is provided a method for manufacturing a nitride semiconductor template, including the steps of: growing and forming a buffer layer in a thickness of not more than a peak width of a projection and in a thickness of not less than 10 nm and not more than 330 nm on a sapphire substrate formed by arranging conical or pyramidal projections on its surface in a lattice pattern; and growing and forming a nitride semiconductor layer on the buffer layer.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: November 7, 2017
    Inventor: Hajime Fujikura
  • Patent number: 9806223
    Abstract: A method for producing an optoelectronic semiconductor chip based on a nitride semiconductor system is specified. The method comprises the steps of: forming a semiconductor section with at least one p-doped region; and forming a covering layer disposed downstream of the semiconductor section in a growth direction of the semiconductor chip, said covering layer having at least one n-doped semiconductor layer. An activation step suitable for electrically activating the p-doped region is effected before or during the formation of the covering layer. An optoelectronic semiconductor chip which can be produced by the method is additionally specified.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: October 31, 2017
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Magnus Ahlstedt, Lutz Höppel, Matthias Peter, Matthias Sabathil, Uwe Strauss, Martin Strassburg
  • Patent number: 9698305
    Abstract: A high voltage LED flip chip includes two or more regions; a Mesa-platform, the Mesa-platform in each region has a first groove; a first electrode located on the Mesa-platform, an area between the first electrodes in two adjacent regions forms a second groove; a first insulation layer covering the Mesa-platforms and the first electrodes, the first insulation layer fills the second groove and partially fills the first groove, and a part of the first groove which is not filled forms a third groove; a fourth groove formed in the first insulation layer, the fourth groove exposes a surface of the first electrode; and an interconnection electrode, the interconnection electrode comprises a first portion connecting the first semiconductor layer through the third groove in a particular region with the first electrode through the fourth groove in another region adjacent to the particular region. The LED formed has improved performance.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: July 4, 2017
    Assignee: Enraytek Optoelectronics Co., Ltd.
    Inventors: Huiwen Xu, Yu Zhang, Qiming Li
  • Patent number: 9552979
    Abstract: A process for depositing aluminum nitride is disclosed. The process comprises providing a plurality of semiconductor substrates in a batch process chamber and depositing an aluminum nitride layer on the substrates by performing a plurality of deposition cycles without exposing the substrates to plasma during the deposition cycles. Each deposition cycle comprises flowing an aluminum precursor pulse into the batch process chamber, removing the aluminum precursor from the batch process chamber, and removing the nitrogen precursor from the batch process chamber after flowing the nitrogen precursor and before flowing another pulse of the aluminum precursor. The process chamber may be a hot wall process chamber and the deposition may occur at a deposition pressure of less than 1 Torr.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: January 24, 2017
    Assignee: ASM IP HOLDING B.V.
    Inventors: Werner Knaepen, Bert Jongbloed, Dieter Pierreux, Peter Zagwijn, Hessel Sprey, Cornelius A. van der Jeugd, Marinus Josephus de Blank, Robin Roelofs, Qi Xie, Jan Willem Maes
  • Patent number: 9543476
    Abstract: A UV light emitting diode and a method of fabricating the same are provided. The light emitting diode includes an active area between an n-type nitride-based semiconductor layer and a p-type nitride-based semiconductor layer, wherein the active area includes a plurality of barrier layers containing Al, a plurality of well layers containing Al and alternately arranged with the barrier layer, and at least one conditioning layer. Each conditioning layer is placed between the well layer and the barrier layer adjacent to the well layer and is formed of a binary nitride semiconductor. The design of the conditioning layer can reduce stress of the active area while allowing uniform control of the composition of the well layers and/or the barrier layers.
    Type: Grant
    Filed: November 28, 2014
    Date of Patent: January 10, 2017
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Ki Yon Park, Jeong Hun Heo, Hwa Mok Kim, Chang Suk Han, Hyo Shik Choi
  • Patent number: 9478708
    Abstract: A method and structure for integrating gallium nitride into a semiconductor substrate. The method may also include means for isolating the gallium nitride from the semiconductor substrate.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: October 25, 2016
    Inventors: William J. Gallagher, Effendi Leobandung, Devendra K. Sadana, Ghavam G. Shahidi
  • Patent number: 9450124
    Abstract: A method of forming an integrated circuit employs a plurality of layers supported on a substrate that include i) n-type contact layer, ii) a p-type modulation doped quantum well structure (MDQWS) above the n-type contact layer, iii) n-type MDQWS above the p-type MDQWS, and iv) p-type contact layer(s) above the n-type MDQWS. A feature for a thyristor is defined by a mesa at the p-type contact layer of iv). A first layer of metal is deposited on the feature, which is then etched for at least one other device. Additional layer(s) of metal is deposited on the feature to form cumulative metal layers, which are etched away to form a set of mesas and corresponding electrodes for the thyristor. The cumulative metal layers that cover the feature and contact the mesa at the p-type contact layer of iv) are patterned to form an anode electrode of the thyristor.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: September 20, 2016
    Assignees: Opel Solar, Inc., THE UNIVERSITY OF CONNECTICUT
    Inventor: Geoff W. Taylor
  • Patent number: 9425349
    Abstract: A lift-off method transfers an optical device layer of an optical device wafer onto a transfer substrate. The optical device layer is stacked on a front face of an epitaxy substrate with a buffer layer provided therebetween. A complex substrate formation step forms a complex substrate by joining the transfer substrate to a front face of the optical device layer of the optical device wafer with an adhesive. A buffer layer destruction step irradiates a laser beam at a wavelength that penetrates the epitaxy substrate and is absorbed by the buffer layer from a rear side of the epitaxy substrate of the complex substrate so as to destroy the buffer layer. An optical device layer transfer step peels off the epitaxy substrate and transfers the optical device layer onto the transfer substrate.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: August 23, 2016
    Inventor: Hiroshi Morikazu
  • Patent number: 9391237
    Abstract: The present invention provides a Group III nitride semiconductor exhibiting reduced contact resistance. A first p-type contact layer of GaN doped with Mg is formed on a p-type cladding layer, using hydrogen as a carrier gas at a growth temperature of 850° C. to 1,050° C., so as to have a thickness of 10 nm to 300 nm. The Mg concentration is 1×1019/cm3 to 1×1020/cm3. Subsequently, a second p-type contact layer of GaN doped with Mg is formed, using nitrogen instead of hydrogen as a carrier gas at a temperature of 600° C. to 800° C. so as to have a thickness of two monolayers to 100 ?. The Mg concentration is 2×1020/cm3 to 1×1021/cm3.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: July 12, 2016
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Shinya Boyama
  • Patent number: 9368756
    Abstract: An organic electroluminescence device includes a support substrate, a first transparent electrode on the support substrate, an organic light-emitting layer on the first transparent electrode, a second transparent electrode on the organic light-emitting layer, and a high refractive index layer arranged between the support substrate and the first transparent electrode, having at least one layer having a refractive index greater than or equal to a refractive index of the support substrate, having a light dispersion portion for dispersing incident light from the organic light-emitting layer, and having a planar surface contacting the first transparent electrode.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: June 14, 2016
    Inventors: Ryuichi Satoh, Hiroshi Miyao, Tadao Yagi
  • Patent number: 9337039
    Abstract: The method includes the steps of a) Providing a stack having a support substrate and a film of GaN having dopant species, b) Directly bonding a shielding layer having a thickness higher than 2 micrometers to the surface of the film of GaN, so as to form an activation structure, and c) Applying a thermal budget to the activation structure according to conditions allowing to electrically activate at least one portion of the dopant species.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: May 10, 2016
    Inventor: Claire Agraffeil
  • Patent number: 9287441
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can prepare a substrate unit including a base substrate, an intermediate crystal layer, and a first mask layer. The intermediate crystal layer has a major surface having a first region, a second region, and a first intermediate region. The first mask layer is provided on the first intermediate region. The method can implement a first growth to grow a first lower layer on the first region and grow a second lower layer on the second region. The first and second lower layers include a semiconductor crystal. The method can implement a second growth to grow a second upper layer while growing a first upper layer to cover the first mask layer with the first and second upper layers. The method can implement cooling to separate the first and second upper layers.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: March 15, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jongil Hwang, Rei Hashimoto, Shinji Saito, Hung Hung, Shinya Nunoue
  • Patent number: 9276117
    Abstract: The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes The device includes a strain-relaxed buffer (SRB) stack over a substrate, a first fin structure disposed over the SRB stack and a liner layer extending along the portion of the second SRB layer and the first semiconductor material layer of the first fin structure.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: March 1, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Pang-Yen Tsai, Tze-Liang Lee
  • Patent number: 9218967
    Abstract: The present invention provides a method for separating an epitaxial layer from a growth substrate, comprising growing an epitaxial layer including a plurality of layers on a growth substrate; etching an edge of at least one layer in the epitaxial layer to form a notch; forming a bonding layer on the epitaxial layer, contacting a bonding substrate onto the bonding layer, and then heating the bonding layer to a bonding temperature for joining the epitaxial layer and the bonding substrate; and cooling the bonding layer after the heating of the boding layer, so that the epitaxial layer and the bonding substrate are joined by the bonding layer, and the epitaxial layer is separated from the growth substrate, wherein the separating the epitaxial layer from the growth substrate starts with separation from the at least one layer where the notch is formed.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: December 22, 2015
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Daewoong Suh, Kyu Ho Lee, Jong Min Jang, Chi Hyun In
  • Patent number: 9184337
    Abstract: A method is provided for producing a light-emitting diode. In one embodiment, a series of layers is deposited on the silicon surface of a carrier in a direction of growth and a light-emitting diode structure is deposited on the series of layers. The series of layers includes a GaN layer, which is formed with gallium nitride. The series of layers includes a masking layer, which is formed with silicon nitride. The masking layer follows at least part of the GaN layer in the direction of growth.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: November 10, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Peter Stauss, Philipp Drechsel
  • Patent number: 9082619
    Abstract: Described herein are systems and methods method for forming semiconductor films. In some embodiment, the methods comprising depositing the source solution containing a solvent and plurality of types of metal ionic species and a second type on a substrate heated to a temperature at or above the boiling point of the solvent. In some embodiments, methods and apparatus for exposing a substrate to a gas are also provided.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: July 14, 2015
    Assignee: International Solar Electric Technology, Inc.
    Inventors: Vijay K. Kapur, Joel Haber, Vincent Kapur, Ashish Bansal, Dan Guevarra
  • Patent number: 9059374
    Abstract: A method for manufacturing a semiconductor light emitting device is provided. The device includes: an n-type semiconductor layer; a p-type semiconductor layer; and a light emitting unit provided between the n-type semiconductor layer and the p-type semiconductor layer. The method includes: forming a buffer layer made of a crystalline AlxGa1?xN (0.8?x?1) on a first substrate made of c-plane sapphire and forming a GaN layer on the buffer layer; stacking the n-type semiconductor layer, the light emitting unit, and the p-type semiconductor layer on the GaN layer; and separating the first substrate by irradiating the GaN layer with a laser having a wavelength shorter than a bandgap wavelength of GaN from the first substrate side through the first substrate and the buffer layer.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: June 16, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuo Ohba, Kei Kaneko, Toru Gotoda, Hiroshi Katsuno, Mitsuhiro Kushibe
  • Patent number: 9054235
    Abstract: Semiconductor device assemblies having solid-state transducer (SST) devices and associated semiconductor devices, systems, and are disclosed herein. In one embodiment, a method of forming a semiconductor device assembly includes forming a support substrate, a transfer structure, and a plurality semiconductor structures between the support substrate and the transfer structure. The method further includes removing the support substrate to expose an active surface of the individual semiconductor structures and a trench between the individual semiconductor structures. The semiconductor structures can be attached to a carrier substrate that is optically transmissive such that the active surface can emit and/or receive the light through the carrier substrate. The individual semiconductor structures can then be processed on the carrier substrate with the support substrate removed.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: June 9, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Martin F. Schubert, Vladimir Odnoblyudov, Scott D. Schellhammer
  • Patent number: 9040332
    Abstract: A submount for a light emitting stack includes a substrate and a metallization layer having circuit traces and a planar dielectric layer that fills regions between the circuit traces. The planar dielectric layer serves to minimize the amount of light lost/absorbed by the substrate and preferably reflects the internally reflected light back toward the desired light output element. To facilitate efficient manufacture, a dielectric paste is applied over the metallized layer, then planed to expose at least portions of the metal conductors for the subsequent coupling to the light emitting stack. Pedestal elements are preferably provided at select locations on the circuit traces to facilitate this coupling while allowing the remainder of the circuit traces to be covered with the dielectric layer.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: May 26, 2015
    Assignee: Koninklijke Philips N.V.
    Inventors: Brendan Moran, Jeffrey Kmetec, Iain Black, Frederic Diana, Serge Laurent Rudaz, Li Zhang
  • Patent number: 9040331
    Abstract: In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Patent number: 9034738
    Abstract: A method for manufacturing a light-emitting diode, which includes the steps of: providing a substrate having a plurality of protruded portions on one main surface thereof wherein the protruded portion is made of a material different in type from that of the substrate and growing a first nitride-based III-V Group compound semiconductor layer on each recess portion of the substrate through a state of making a triangle in section wherein a bottom surface of the recess portion becomes a base of the triangle; laterally growing a second nitride-based III-V Group compound semiconductor layer on the substrate from the first nitride-based III-V Group compound semiconductor layer; and successively growing, on the second nitride-based III-V Group compound semiconductor layer, a third nitride-based III-V Group compound semiconductor layer of a first conduction type, an active layer, and a fourth nitride-based III-V compound semiconductor layer of a second conduction type.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: May 19, 2015
    Inventors: Akira Ohmae, Michinori Shiomi, Noriyuki Futagawa, Takaaki Ami, Takao Miyajima, Yuuji Hiramatsu, Izuho Hatada, Nobukata Okano, Shigetaka Tomiya, Katsunori Yanashima, Tomonori Hino, Hironobu Narui
  • Patent number: 9034675
    Abstract: Techniques are provided for manufacturing a light-emitting device having high internal quantum efficiency, consuming less power, having high luminance, and having high reliability. The techniques include forming a conductive light-transmitting oxide layer comprising a conductive light-transmitting oxide material and silicon oxide, forming a barrier layer in which density of the silicon oxide is higher than that in the conductive light-transmitting oxide layer over the conductive light-transmitting oxide layer, forming an anode having the conductive light-transmitting oxide layer and the barrier layer, heating the anode under a vacuum atmosphere, forming an electroluminescent layer over the heated anode, and forming a cathode over the electroluminescent layer. According to the techniques, the barrier layer is formed between the electroluminescent layer and the conductive light-transmitting oxide layer.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: May 19, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Junichiro Sakata, Yoshiharu Hirakata, Norihito Sone
  • Patent number: 9029177
    Abstract: An optoelectronic semiconductor chip has a first semiconductor layer sequence which comprises a multiplicity of microdiodes, and a second semiconductor layer sequence which comprises an active region The first semiconductor layer sequence and the second semiconductor layer sequence are based on a nitride compound semiconductor material, the first semiconductor layer sequence is before the first semiconductor layer sequence in the direction of growth, and the microdiodes form an ESD protection for the active region.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: May 12, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Rainer Butendeich, Alexander Walter, Matthias Peter, Tobias Meyer, Tetsuya Taki, Hubert Maiwald
  • Publication number: 20150125982
    Abstract: A nitride semiconductor device may include a substrate, a dislocation control layer formed on the substrate and including a plurality of hollow structures including a nitride, and a nitride semiconductor layer formed on the dislocation control layer.
    Type: Application
    Filed: October 23, 2014
    Publication date: May 7, 2015
    Inventors: Moon-Sang LEE, Sung-Soo PARK, Bong-Kyun KANG, Dae-Ho YOON
  • Publication number: 20150125983
    Abstract: A semiconductor light-emitting device, and a method of manufacturing the same. The semiconductor light-emitting device includes a first electrode layer, an insulating layer, a second electrode layer, a second semiconductor layer, an active layer, and a first semiconductor layer that are sequentially stacked on a substrate, a first contact that passes through the substrate to be electrically connected to the first electrode layer, and a second contact that passes through the substrate, the first electrode layer, and the insulating layer to communicate with the second electrode layer. The first electrode layer is electrically connected to the first semiconductor layer by filling a contact hole that passes through the second electrode layer, the second semiconductor layer, and the active layer, and the insulating layer surrounds an inner circumferential surface of the contact hole to insulate the first electrode layer from the second electrode layer.
    Type: Application
    Filed: January 9, 2015
    Publication date: May 7, 2015
    Inventors: Jong-In YANG, Tae-Hyung KIM, Si-Hyuk LEE, Sang-Yeob SONG, Cheol-Soo SONE, Hak-Hwan KIM, Jin-Hyun LEE
  • Publication number: 20150125981
    Abstract: The present invention relates to a method for separating semiconductor devices from a substrate using a nanoporous structure, wherein electrochemical etching is carried out in the absence of a surface metal layer, then the surface metal layer is deposited, and then a GaN thin film is transferred onto a metal wafer by means of wafer bonding and lift-off.
    Type: Application
    Filed: February 6, 2013
    Publication date: May 7, 2015
    Applicants: Seoul Viosys Co., Ltd., University Industry Liaison Office of Chonnam National University
    Inventors: Sang Wan Ryu, Jin Ho Kang
  • Patent number: 9024331
    Abstract: Disclosed is a semiconductor light emitting element (LC) provided with a substrate (110) having one surface on which plural hexagonal-pyramid-shaped protrusions (110b) are provided, a base layer (130) provided so as to be in contact with the surface on which the protrusions (110b) are provided, an n-type semiconductor layer (140) provided so as to be in contact with the base layer (130), a light emitting layer (150) provided so as to be in contact with the n-type semiconductor layer (140), and a p-type semiconductor layer (160) provided so as to be in contact with the light emitting layer (150). Each protrusion (110b) scatters light in lateral and oblique directions within the semiconductor light emitting element (LC). The protrusions are densely arranged on a substrate on which semiconductor layers are laminated, so that the light extraction efficiency is improved.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: May 5, 2015
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Yohei Sakano
  • Patent number: 9024338
    Abstract: The present invention relates to the growing of nitride semiconductors, applicable for a multitude of semiconductor devices such as diodes, LEDs and transistors. According to the method of the invention nitride semiconductor nanowires are grown utilizing a CVD based selective area growth technique. A nitrogen source and a metal-organic source are present during the nanowire growth step and at least the nitrogen source flow rate is continuous during the nanowire growth step. The V/III-ratio utilized in the inventive method is significantly lower than the V/III-ratios commonly associated with the growth of nitride based semiconductor.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: May 5, 2015
    Assignee: QuNano AB
    Inventors: Werner Seifert, Damir Asoli, Zhaoxia Bi, Jonas Ohlsson, Lars Ivar Samuelson
  • Patent number: 9023673
    Abstract: A method to grow single phase group III-nitride articles including films, templates, free-standing substrates, and bulk crystals grown in semi-polar and non-polar orientations is disclosed. One or more steps in the growth process includes the use of additional free hydrogen chloride to eliminate undesirable phases, reduce surface roughness, and increase crystalline quality. The invention is particularly well-suited to the production of single crystal (11.2) GaN articles that have particular use in visible light emitting devices.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: May 5, 2015
    Assignee: Ostendo Technologies, Inc.
    Inventors: Lisa Shapovalov, Oleg Kovalenkov, Vladimir Ivantsov, Vitali Soukhoveev, Alexander Syrkin, Alexander Usikov
  • Patent number: 9024344
    Abstract: A semiconductor device has a multilayer doping to provide improved passivation by quantum exclusion. The multilayer doping includes at least two doped layers fabricated using MBE methods. The dopant sheet densities in the doped layers need not be the same, but in principle can be selected to be the same sheet densities or to be different sheet densities. The electrically active dopant sheet densities are quite high, reaching more than 1×1014 cm?2, and locally exceeding 1022 per cubic centimeter. It has been found that silicon detector devices that have two or more such dopant layers exhibit improved resistance to degradation by UV radiation, at least at wavelengths of 193 nm, as compared to conventional silicon p-on-n devices.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: May 5, 2015
    Assignee: California Institute of Technology
    Inventor: Michael E. Hoenk
  • Publication number: 20150115299
    Abstract: A device includes a substrate (10) and a III-nitride structure (15) grown on the substrate, the III-nitride structure comprising a light emitting layer (16) disposed between an n-type region (14) and a p-type region (18). The substrate is a RAO3 (MO)n where R is one of a trivalent cation: Sc, In, Y and a lanthanide; A is one of a trivalent cation: Fe (III), Ga and Al; M is one for a divalent cation: Mg, Mn, Fe (II), Co, Cu, Zn and Cd; and n is an integer ?1. The substrate has an inplane lattice constant asubstrate. At lease one III-nitride layer in the III-nitride structure has a bulk lattice constant alayer such that [(|asubstrate?alayer|)/asubstrate]*100% is no more than 1%.
    Type: Application
    Filed: October 27, 2011
    Publication date: April 30, 2015
    Inventors: Michael Jason Grundmann, Nathan Frederick Gardner, Werner Karl Goetz, Melvin Barker Mclaurin, John Edward Epler, Francisco Alexander Leon
  • Publication number: 20150115220
    Abstract: A nitride light emitting diode comprising at least one nitride-based active region formed on or above a patterned substrate, wherein the active region is comprised of at least one quantum well structure; and a nitride interlayer, formed on or above the active region, having at least two periods of alternating layers of InxGa1-xN and InyGa1-yN, where 0<x<1, 0?y<1 and x?y.
    Type: Application
    Filed: October 10, 2014
    Publication date: April 30, 2015
    Inventors: Michael Iza, James S. Speck, Shuji Nakamura, Steven P. DenBaars
  • Patent number: 9018081
    Abstract: A method is provided for fabricating a light emitting diode (LED) using three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. The method forms a plurality of GaN pillar structures, each with an n-doped GaN (n-GaN) pillar and planar sidewalls perpendicular to the c-plane, formed in either an m-plane or a-plane family. A multiple quantum well (MQW) layer is formed overlying the n-GaN pillar sidewalls, and a layer of p-doped GaN (p-GaN) is formed overlying the MQW layer. The plurality of GaN pillar structures are deposited on a first substrate, with the n-doped GaN pillar sidewalls aligned parallel to a top surface of the first substrate. A first end of each GaN pillar structure is connected to a first metal layer. The second end of each GaN pillar structure is etched to expose the n-GaN pillar second end and connected to a second metal layer.
    Type: Grant
    Filed: November 23, 2013
    Date of Patent: April 28, 2015
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Mark Albert Crowder, Changqing Zhan, Paul J. Schuele
  • Patent number: 9018025
    Abstract: A semiconductor device is manufactured by forming at least one epitaxial structure over a substrate. A portion of the substrate is cut and lifted to expose a partial surface of the epitaxial structure. A first electrode is then formed on the exposed partial surface to result in a vertical semiconductor device.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: April 28, 2015
    Assignee: Phostek Inc.
    Inventor: Yuan-Hsiao Chang
  • Publication number: 20150108494
    Abstract: The present disclosure provides a light-emitting device and manufacturing method thereof. The light-emitting device comprising: a light-emitting stack; and a semiconductor layer having a first surface connecting to the light-emitting stack, a second surface opposite to the first surface, and a void; wherein the void comprises a bottom part near the first surface and an opening on the second surface, and a dimension of the bottom part is larger than the dimension of the opening.
    Type: Application
    Filed: October 21, 2014
    Publication date: April 23, 2015
    Inventors: Wen-Luh LIAO, Chih-Chiang LU, Shih-Chang LEE, Hung-Ta CHENG, Hsin-Chan CHUNG, Yi-Chieh LIN
  • Patent number: 9012924
    Abstract: Provided is a spectrum detector capable of being miniaturized and which does not require complicated optical axis alignment. The spectrum detector of the present invention comprises: a substrate; a photodetector formed on the substrate and including a semiconductor having a plurality of convex portions; and a wavelength detection circuit for detecting a wavelength of light transmitted through the plurality of convex portions, from light incident on the photodetector. According to the present invention, a small-sized spectrum detector can be provided which can easily detect a peak wavelength distribution included in light of an unknown wavelength, without the use of optical equipment such as a grating or prism, thus dispensing with the need for the optical axis alignment of a complex optical system.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: April 21, 2015
    Assignees: Seoul Viosys Co., Ltd.
    Inventors: Shiro Sakai, Won Chul Seo, Dae Won Kim