By Layers Which Are Coated, Contacted, Or Diffused Patents (Class 438/476)
  • Patent number: 10453703
    Abstract: The disclosure is directed to a method to recover the gate oxide integrity yield of a silicon wafer after rapid thermal anneal in an ambient atmosphere comprising a nitrogen containing gas, such as NH3 or N2. Generally, rapid thermal anneals in an ambient atmosphere comprising a nitrogen containing gas, such as NH3 or N2 to thereby imprint an oxygen precipitate profile can degrade the GOI yield of a silicon wafer by exposing as-grown crystal defects (oxygen precipitate) and vacancies generated by the silicon nitride film. The present invention restores GOI yield by stripping the silicon nitride layer, which is followed by wafer oxidation, which is followed by stripping the silicon oxide layer.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: October 22, 2019
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Young Jung Lee, Jae-Woo Ryu, Byung Chun Kim, Robert J. Falster, Soon Sung Park, Tae Hoon Kim, Jun Hwan Ji, Carissima Marie Hudson
  • Patent number: 9947540
    Abstract: Various methods and structures formed by those methods are described. In accordance with a method, a first metal-containing layer is formed on a substrate. A second metal-containing layer is formed on the substrate. A material of the first metal-containing layer is different from a material of the second metal-containing layer. A chlorine-based treatment is performed on the first metal-containing layer and the second metal-containing layer. A third metal-containing layer is deposited on the first metal-containing layer and the second metal-containing layer using Atomic Layer Deposition (ALD).
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: April 17, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yen Tsai, Da-Yuan Lee, JoJo Lee, Ming-Hsing Tsai, Hsueh Wen Tsau, Weng Chang, Ying-Chieh Hung, Yi-Hung Lin
  • Patent number: 9685333
    Abstract: A method of manufacturing a silicon carbide semiconductor device includes grinding a back surface of a semiconductor substrate formed of silicon carbide to reduce thickness thereof and provide an altered layer that is ground; removing by polishing or etching, the altered layer from the back surface; forming a nickel film on the back surface of the semiconductor substrate after removing the altered layer; heat treating the nickel film to forming a nickel silicide layer by silicidation; and forming a metal electrode on a surface of the nickel silicide layer.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: June 20, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tsunehiro Nakajima, Masanobu Iwaya, Fumikazu Imai
  • Patent number: 9683308
    Abstract: Embodiments of the present invention generally relate to methods for removing contaminants and native oxides from substrate surfaces. The methods generally include removing contaminants disposed on the substrate surface using a plasma process, and then cleaning the substrate surface by use of a remote plasma assisted dry etch process.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: June 20, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Christopher S. Olsen, Theresa K. Guarini, Jeffrey Tobin, Lara Hawrylchak, Peter Stone, Chi Wei Lo, Saurabh Chopra
  • Patent number: 9567205
    Abstract: A micromechanical sensor device and a corresponding manufacturing method are described. The micromechanical sensor device includes a CMOS wafer having a front side and a rear side, a rewiring device formed on the front side of the CMOS wafer including a plurality of stacked printed conductor levels and insulation layers, an MEMS wafer having a front side and a rear side, a micromechanical sensor device formed across the front side of the MEMS wafer, a bond connection between the MEMS wafer and the CMOS wafer, a cavern between the MEMS wafer and the CMOS wafer, in which the sensor device is hermetically enclosed, and an exposed getter layer area applied to at least one of the plurality of stacked printed conductor levels and insulation layers.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: February 14, 2017
    Assignee: ROBERT BOSCH GMBH
    Inventors: Jochen Reinmuth, Julian Gonska
  • Patent number: 9390942
    Abstract: Embodiments of preparing substrates for subsequent bonding with semiconductor layer are described herein. A substrate may be prepared with one or more chemicals or a sacrificial layer to limit or remove substrate contaminants and reduce substrate surface damage. Other embodiments may be described and claimed.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: July 12, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Hiroshi Domyo, Michael McCafferty, Alain Duvallet, Masaki Sato, Christopher O'Brien, Anthony Mark Miscione, George Imthurn
  • Patent number: 9306010
    Abstract: A first semiconductor zone of a first conduction type is formed from a semiconductor base material doped with first and second dopants. The first and second dopants are different substances and also different from the semiconductor base material. The first dopant is electrically active and causes a doping of the first conduction type in the semiconductor base material, and causes either a decrease or an increase of a lattice constant of the pure, undoped first semiconductor zone. The second dopant may be electrically active, and may be of the same doping type as the first dopant, causes one or both of: a hardening of the first semiconductor zone; an increase of the lattice constant of the pure, undoped first semiconductor zone if the first dopant causes a decrease, and a decrease of the lattice constant of the pure, undoped first semiconductor zone if the first dopant causes an increase, respectively.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: April 5, 2016
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Manfred Kotek, Johannes Baumgartl, Markus Harfmann, Christian Krenn, Thomas Neidhart
  • Patent number: 9287287
    Abstract: Present example embodiments relate generally to methods of fabricating a semiconductor device, and semiconductor devices thereof, comprising providing a substrate, forming an insulating base layer on the substrate, and disposing a conductive layer on the insulating base layer at an initial temperature. The methods further comprise increasing the initial temperature at a first increase rate to a first increased temperature and performing an in-situ annealing process to the conductive layer at the first increased temperature. The methods further comprise increasing the first increased temperature at a second increase rate to a second increased temperature, and forming an insulating layer after performing the in-situ annealing process at the second increased temperature.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: March 15, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Jung-Yi Guo, Chun-Min Cheng
  • Publication number: 20150130039
    Abstract: The invention relates to a layer arrangement and a wafer level package comprising the layer arrangement, and in particular, the layer arrangement comprises a getter layer and further comprises a sacrificial layer. The wafer level package may be used in microelectromechanical systems (MEMS) packaging at a vacuum level of about 10 mTorr or less such as close to 1 mTorr (i.e. MEMS vacuum packaging).
    Type: Application
    Filed: June 18, 2013
    Publication date: May 14, 2015
    Inventors: Vivek Chidambaram, Ling Xie, Ranganathan Nagarajan, Bangtao Chen, Beng Yeung Ho
  • Publication number: 20150118828
    Abstract: Native oxide growth on germanium, silicon germanium, and InGaAs undesirably affects CET (capacitive equivalent thickness) and EOT (effective oxide thickness) of high-k and low-k metal-oxide layers formed on these semiconductors. Even if pre-existing native oxide is initially removed from the bare semiconductor surface, some metal oxide layers are oxygen-permeable in thicknesses below about 25 ? thick. Oxygen-containing species used in the metal-oxide deposition process may diffuse through these permeable layers, react with the underlying semiconductor, and re-grow the native oxide. To eliminate or mitigate this re-growth, the substrate is exposed to a gas or plasma reductant (e.g., containing hydrogen). The reductant diffuses through the permeable layers to react with the re-grown native oxide, detaching the oxygen and leaving the un-oxidized semiconductor. The reduction product(s) resulting from the reaction may then be removed from the substrate (e.g., driven off by heat).
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Applicant: Intermolecular Inc.
    Inventors: Frank Greer, Amol Joshi, Kevin Kashefi, Albert Sanghyup Lee, Abhijit Pethe, J Watanabe
  • Publication number: 20150118829
    Abstract: Methods of forming a semiconductor layer including germanium with low defectivity are provided. The methods may include sequentially forming a silicate glass layer, a diffusion barrier layer including nitride and an interfacial layer including oxide on a substrate. The methods may also include forming a first semiconductor layer on the interfacial layer and converting a portion of the first semiconductor layer into a second semiconductor layer having a germanium concentration therein that is higher than a germanium concentration of the first semiconductor layer.
    Type: Application
    Filed: September 9, 2014
    Publication date: April 30, 2015
    Inventors: Jorge A. Kittl, Mark S. Rodder
  • Publication number: 20150108617
    Abstract: A method for chemically passivating a surface of a product made of a III-V semiconductor material in which a) a P(N) polymer film is formed by deposition in a solvent comprising liquid ammonia. The film is formed by deposition, without electrochemical assistance, in the solvent, in the presence of an oxidizing chemical additive comprising phosphorous and generating electrical charge carriers in said surface.
    Type: Application
    Filed: June 12, 2012
    Publication date: April 23, 2015
    Applicants: Centre National de la Recherche Scientifique-CNRS, Universite de Versailles Saint-Quentin-En-Yvelines, Ecole Polytechnique
    Inventors: Francoise Hervagault, Elaine Le Floch, Clemence Le Floch, Paul Le Floch
  • Publication number: 20150102432
    Abstract: The present disclosure relates to a method of gettering that provides for a high efficiency gettering process by depositing a gettering material on a roughened substrate surface, and an associated apparatus. In some embodiments, the method is performed by providing a substrate into a processing chamber having residual gases. One or more cavities are formed in the substrate at locations between bonding areas on a top surface of the substrate. Respective cavities have roughened interior surfaces that vary in a plurality of directions. A getter layer is deposited into the one or more cavities. The roughened interior surfaces of the one or more cavities enable the substrate to more effectively absorb the residual gases, thereby increasing the efficiency of the gettering process.
    Type: Application
    Filed: October 15, 2013
    Publication date: April 16, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yuan-Chih Hsieh, Li-cheng Chu, Hung-Hua Lin, Chih-Jen Chan, Lan-Lin Chao
  • Publication number: 20150076597
    Abstract: A semiconductor component and a method for producing a semiconductor component are described. The semiconductor component includes a semiconductor body including an inner zone and an edge zone, and a passivation layer, which is arranged at least on a surface of the semiconductor body adjoining the edge zone. The passivation layer includes a semiconductor oxide and that includes a defect region having crystal defects that serve as getter centers for contaminations.
    Type: Application
    Filed: September 15, 2014
    Publication date: March 19, 2015
    Inventors: Hans-Joachim Schulze, Manfred Pfaffenlehner, Markus Schmitt
  • Patent number: 8981544
    Abstract: A packaging structure including at least one cavity wherein at least one micro-device is provided, the cavity being bounded by at least a first substrate and at least a second substrate integral with the first substrate through at least one bonding interface consisting of at least one metal or dielectric material, wherein at least one main face of the second substrate provided facing the first substrate is covered with at least one layer of at least one getter material, the bonding interface being provided between the first substrate and the layer of getter material.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: March 17, 2015
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Xavier Baillin, Christine Ferrandon
  • Publication number: 20150069539
    Abstract: The present disclosure relates to a method of gettering that provides for a high efficiency gettering process by increasing an area in which a getter layer is deposited, and an associated apparatus. In some embodiments, the method is performed by providing a substrate into a processing chamber having one or more residual gases. A cavity is formed within a top surface of the substrate. The cavity has a bottom surface and sidewalls extending from the bottom surface to the top surface. A getter layer, which absorbs the one or more residual gases, is deposited over the substrate at a position extending from the bottom surface of the cavity to a location on the sidewalls. By depositing the getter layer to extend to a location on the sidewalls of the cavity, the area of the substrate that is able to absorb the one or more residual gases is increased.
    Type: Application
    Filed: September 11, 2013
    Publication date: March 12, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Jen Chan, Lee-Chuan Tseng, Shih-Wei Lin, Che-Ming Chang, Chung-Yen Chou, Yuan-Chih Hsieh
  • Patent number: 8975175
    Abstract: A contact region for a semiconductor substrate is disclosed. Embodiments can include forming a seed metal layer having an exposed solder pad region on the semiconductor substrate and forming a first metal layer on the seed metal layer. In an embodiment, a solderable material, such as silver, can be formed on the exposed solder pad region prior to forming the first metal layer. Embodiments can include forming a solderable material on the exposed solder pad region after forming the first metal layer. Embodiments can also include forming a plating contact region on the seed metal layer, where the plating contact region allows for electrical conduction during a plating process.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: March 10, 2015
    Assignee: SunPower Corporation
    Inventor: Thomas Pass
  • Publication number: 20150061088
    Abstract: The present disclosure relates to a semiconductor device including an oxygen gettering layer between a group III-V compound semiconductor layer and a dielectric layer, and a method of fabricating the semiconductor device. The semiconductor device may include a compound semiconductor layer; a dielectric layer disposed on the compound semiconductor layer; and an oxygen gettering layer interposed between the compound semiconductor layer and the dielectric layer. The oxygen gettering layer includes a material having a higher oxygen affinity than a material of the compound semiconductor layer.
    Type: Application
    Filed: March 13, 2014
    Publication date: March 5, 2015
    Inventors: Dong-soo LEE, Myoung-Jae LEE, Seong-ho CHO, Mohammad Rakib Uddin, David SEO, Moon-seung YANG, Sang-moon LEE, Sung-hun LEE, Ji-hyun HUR, Eui-chul HWANG
  • Publication number: 20150064881
    Abstract: A method is for treating a doped gallium nitride substrate of a first conductivity type, having dislocations emerging on the side of at least one of its surfaces. The method may include: a) forming, where each dislocation emerges, a recess extending into the substrate from the at least one surface; and b) filling the recesses with doped gallium nitride of the second conductivity type.
    Type: Application
    Filed: August 20, 2014
    Publication date: March 5, 2015
    Inventor: Arnaud YVON
  • Publication number: 20150050799
    Abstract: A method for fabricating a semiconductor device is provided. The method includes the following steps. Firstly, a substrate having a nitride layer and a platinum (PO-containing nickel (Ni)-semiconductor compound layer is provided. Then the nitride layer and the Pt are removed in situ with a chemical solution including a sulfuric acid component and a phosphoric acid component.
    Type: Application
    Filed: August 19, 2013
    Publication date: February 19, 2015
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Bor-Shyang Liao, Tsung-Hsun Tsai, Kuo-Chih Lai, Pin-Hong Chen, Chia-Chang Hsu, Shu-Min Huang, Min-Chung Cheng, Chun-Ling Lin
  • Patent number: 8956958
    Abstract: A method for producing a substrate with buried layers of getter material, including: making a first stack including one layer of a first getter material, arranged on a first support; making a second stack including one layer of a second getter material, arranged on a second support; and bringing the first stack into contact with the second stack and performing thermocompression, the layers of the first and of the second getter material being arranged between the first and the second support, at a temperature greater than or equal to a lowest temperature among thermal activation temperatures of the first and of the second getter material, to bond the layers of the first and second getter materials together.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: February 17, 2015
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventor: Xavier Baillin
  • Publication number: 20150044858
    Abstract: A film-forming material including a metal oxide such as a SiO2 film on the surface of a substrate, in which foreign substances, such as fine particles, are generated with difficulty while being stored, and a method for forming a film, in which the method includes forming a film on the surface of a substrate using the film-forming material. The film-forming material includes a metal compound capable of generating a hydroxyl group upon hydrolysis dissolved in an organic solvent that does not have a functional group that reacts with the metal compound. The organic solvent includes a solvent having a value of Log P of from 0 to 3.5.
    Type: Application
    Filed: August 4, 2014
    Publication date: February 12, 2015
    Inventors: Daijiro Mori, Akira Kumazawa, Mai Sugawara
  • Publication number: 20150014824
    Abstract: The present invention relates to a method for fabricating a substrate for a semiconductor device comprising an interface region between a first layer and a second layer having different electrical properties and an exposed surface, wherein at least the second layer includes defects and/or dislocations, the method comprising the steps of: a) removing material at one or more locations of the defects and/or dislocations, thereby forming pits, wherein the pits intersect the interface region, and b) passivating the pits. The invention also relates to a corresponding semiconductor device structure.
    Type: Application
    Filed: December 15, 2011
    Publication date: January 15, 2015
    Applicant: SOITEC
    Inventor: Oleg Kononchuk
  • Publication number: 20150017456
    Abstract: When an etchant for metal (e.g., HF) reaches an underlying silicon oxide layer, it may form silanol bonds or other hydrogen bonds that resist rinsing, so that some etchant remains to be trapped under the next deposited layer. Trapped etchant can create voids that eventually degrade the performance of the oxide layer. Exposing the surface to a liquid solution or gaseous precursor containing silane seals the defects without causing an overall thickness change. The silane reacts at sites with silanol (or other hydrogen) bonds, breaking the bonds and replacing the hydrogen with silicon, but does not react in the absence of a hydrogen bond.
    Type: Application
    Filed: July 15, 2013
    Publication date: January 15, 2015
    Inventors: Anh Duong, Clemens Fitz
  • Publication number: 20150001680
    Abstract: According to the present invention, there is provided a method for manufacturing a silicon single crystal wafer, wherein a first heat treatment for holding a silicon single crystal wafer in an oxygen containing atmosphere at a first heat treatment temperature for 1 to 60 seconds and cooling it to 800° C. or less at a temperature falling rate of 1 to 100° C./second by using a rapid heating/rapid cooling apparatus is performed to inwardly diffuse oxygen and form an oxygen concentration peak region near a surface of the silicon single crystal wafer, and then a second heat treatment is performed to agglomerate oxygen in the silicon single crystal wafer into the oxygen concentration peak region. As a result, it is possible to provide the method for manufacturing a silicon single crystal wafer that enables forming an excellent gettering layer close to a device forming region.
    Type: Application
    Filed: December 14, 2012
    Publication date: January 1, 2015
    Inventors: Tetsuya Oka, Koji Ebara
  • Publication number: 20140377938
    Abstract: A method for producing a semiconductor device is disclosed which includes a diffusion step of forming, on a CZ-FZ silicon semiconductor substrate, a deep diffusion layer involving a high-temperature and long-term thermal diffusion process which is performed at a thermal diffusion temperature of 1290° C. to a melting temperature of a silicon crystal for 100 hours or more; and a giving step of giving a diffusion source for an interstitial silicon atom to surface layers of two main surfaces of the silicon semiconductor substrate before the high-temperature, long-term thermal diffusion process. The step of giving the diffusion source for the interstitial silicon atom to the surface layers of the two main surfaces of the silicon semiconductor substrate is performed by forming thermally-oxidized films on two main surfaces of the silicon semiconductor substrate or by implanting silicon ions into surface layers of the two main surfaces of the silicon semiconductor substrate.
    Type: Application
    Filed: September 5, 2014
    Publication date: December 25, 2014
    Inventors: Haruo NAKAZAWA, Masaaki OGINO, Hidenao KURIBAYASHI, Hideaki TERANISHI
  • Publication number: 20140353805
    Abstract: A process is provided for the removal of contaminants from a semiconductor device, for example, removing contaminants from pores of an ultra-low k film. In one aspect, a method includes: providing a dielectric layer with contaminant-containing pores and exposing the dielectric layer to a supercritical fluid. The supercritical fluid can dissolve and remove the contaminants. In another aspect, an intermediate semiconductor device structure is provided that contains a dielectric layer with contaminant-containing pores and a supercritical fluid within the pores. In another aspect, a semiconductor device structure with a dielectric layer containing uncontaminated pores is provided.
    Type: Application
    Filed: May 28, 2013
    Publication date: December 4, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Errol Todd RYAN, Moosung M. CHAE, Larry ZHAO, Kunaljeet TANWAR, Nicholas Vincent LICAUSI, Christian WITT, Ailian ZHAO, Ming HE, Sean X. LIN, Xunyuan ZHANG
  • Publication number: 20140342532
    Abstract: A method of selectively removing fluorocarbon layers from overlying low-k dielectric material is described. These protective plasma treatments (PPT) are delicate alternatives to traditional post-etch treatments (PET). The method includes sequential exposure to (1) a local plasma formed from a silicon-fluorine precursor followed by (2) an exposure to plasma effluents formed in a remote plasma from a fluorine-containing precursor. The remote plasma etch (2) has been found to be highly selective of the residual material following the local plasma silicon-fluorine exposure. The sequential process (1)-(2) avoids exposing the low-k dielectric material to oxygen which would undesirably increase its dielectric constant.
    Type: Application
    Filed: August 14, 2013
    Publication date: November 20, 2014
    Applicant: Applied Materials, Inc.
    Inventors: Lina Zhu, Sean S. Kang, Srinivas D. Nemani, Chia-Ling Kao
  • Patent number: 8878349
    Abstract: A semiconductor chip includes a semiconductor substrate having one surface, an other surface which faces away from the one surface, and through holes which pass through the one surface and the other surface; through electrodes filled in the through holes; and a gettering layer formed of polysilicon interposed between the through electrodes and inner surfaces of the semiconductor substrate whose form is defined by the through holes.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: November 4, 2014
    Assignee: SK Hynix Inc.
    Inventors: Gyu Jei Lee, Kang Won Lee, Hyun Joo Kim
  • Patent number: 8865573
    Abstract: A method for fabricating a semiconductor device include forming devices on a front side of a semiconductor substrate, forming a hydrogen-containing layer on a back side of the semiconductor substrate, forming an outgassing prevention layer over the hydrogen-containing layer, and performing a hydrogen treatment process to diffuse hydrogen, contained in the hydrogen-containing layer, into the semiconductor substrate.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: October 21, 2014
    Assignee: SK Hynix Inc.
    Inventor: Byung-Il Kwak
  • Patent number: 8859398
    Abstract: Adhesion of dielectric layer stacks to be formed after completing the basic configuration of transistor elements may be increased by avoiding the formation of a metal silicide in the edge region of the substrate. For this purpose, a dielectric protection layer may be selectively formed in the edge region prior to a corresponding pre-clean process or immediately prior to deposition of the refractory metal. Hence, non-reacted metal may be efficiently removed from the edge region without creating a non-desired metal silicide. Hence, the further processing may be continued on the basis of enhanced process conditions for forming interlayer dielectric materials.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: October 14, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Tobias Letz, Frank Feustel, Kai Frohberg
  • Patent number: 8846500
    Abstract: At least one exemplary embodiment is directed to a method of forming a multilayered gettering structure that can be used to control wafer warpage.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: September 30, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: David Lysacek, Jana Vojtechovska, Lubomir Dornak, Petr Kostelnik, Lukas Valek, Petr Panek
  • Publication number: 20140273407
    Abstract: Methods and compositions for the surface cleaning and passivation of CdTe substrates usable in solar cells are disclosed. In some embodiments amine-containing chelators are used and in other embodiments phosphorus-containing chelators are used.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Applicant: FIRST SOLAR, INC.
    Inventors: Scott Christensen, Scott Jewhurst, Minh Huu Le, Haifan Liang, Hao Lin, Wei Liu, Minh Anh Nguyen, Zhi Wen Sun, Gang Xiong
  • Publication number: 20140246760
    Abstract: A semiconductor device includes a III-nitride semiconductor substrate having a two-dimensional charge carrier gas at a depth from a main surface of the III-nitride semiconductor substrate. A surface protection layer is provided on the main surface of the III-nitride semiconductor substrate. The surface protection layer has charge traps in a band gap which exist at room temperature operation of the semiconductor device. A contact is provided in electrical connection with the two-dimensional charge carrier gas in the III-nitride semiconductor substrate. A charge protection layer is provided on the surface protection layer. The charge protection layer includes an oxide and shields the surface protection layer under the charge protection layer from radiation with higher energy than the bandgap energy of silicon nitride.
    Type: Application
    Filed: March 1, 2013
    Publication date: September 4, 2014
    Inventors: Matthias Strassburg, Roman Knoefler
  • Patent number: 8809155
    Abstract: Device structures, design structures, and fabrication methods for a varactor. The device structure includes a first electrode formed on a dielectric layer, and a semiconductor body formed on the first electrode. The semiconductor body is comprised of a silicon-containing semiconductor material in an amorphous state or a polycrystalline state. The device structure further includes an electrode insulator formed on the semiconductor body and a second electrode formed on the electrode insulator.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: John J. Ellis-Monaghan, Michael J. Hauser, Zhong-Xiang He, Xuefeng Liu, Richard A. Phelps, Robert M. Rassel, Anthony K. Stamper
  • Patent number: 8796116
    Abstract: Methods for producing silicon on insulator structures with a reduced metal content in the device layer thereof are disclosed. Silicon on insulator structures with a reduced metal content are also disclosed.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: August 5, 2014
    Assignee: SunEdison Semiconductor Limited
    Inventors: Alexis Grabbe, Larry Flannery
  • Patent number: 8785229
    Abstract: Methods of forming micromechanical resonators include forming first and second substrates having first and second semiconductor layers of first and second conductivity type therein, respectively. The first semiconductor layer of first conductivity type is bonded to the second semiconductor layer of second conductivity type to thereby define a first rectifying junction at an interface of the bonded semiconductor layers. A piezoelectric layer is formed on the first rectifying junction and at least a first electrode is formed on the piezoelectric layer.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: July 22, 2014
    Assignee: Integrated Device Technology, inc.
    Inventor: Wanling Pan
  • Patent number: 8785301
    Abstract: A method of cleaning a SiC semiconductor includes the steps of forming an oxide film at the surface of a SiC semiconductor, and removing the oxide film. At the step of forming an oxide film, an oxide film is formed using ozone water having a concentration greater than or equal to 30 ppm. The forming step preferably includes the step of heating at least one of the surface of the SiC semiconductor and the ozone water. Thus, there can be obtained a method of cleaning a SiC semiconductor that can exhibit cleaning effect on the SiC semiconductor.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: July 22, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda, Tomihito Miyazaki, Toru Hiyoshi, Satomi Itoh, Hiromu Shiomi
  • Publication number: 20140187022
    Abstract: Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 3, 2014
    Applicant: SUNEDISON, INC.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Publication number: 20140187023
    Abstract: Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 3, 2014
    Applicant: SunEdison, Inc.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Patent number: 8765571
    Abstract: A method and system are provided for manufacturing a base substrate that is used in manufacturing a semi-conductor on insulator type substrate. The base substrate may be manufactured by providing a silicon substrate having an electrical resistivity above 500 Ohm·cm; cleaning the silicon substrate so as to remove native oxide and dopants from a surface thereof; forming, on the silicon substrate, a layer of dielectric material; and forming, on the layer of dielectric material, a layer of poly-crystalline silicon. These actions are implemented successively in an enclosure.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: July 1, 2014
    Assignee: Soitec
    Inventors: Oleg Kononchuk, Frederic Allibert
  • Patent number: 8765000
    Abstract: The present disclosure suggests apparatus and methods that can be used to chemically process microfeature workpieces, e.g., semiconductor wafers. One implementation of the invention provides a method in which a surface of a microfeature workpiece is contacted with an etchant liquid. The wall of the processing chamber may be highly transmissive of an operative wavelength range of radiation, but the etchant liquid is absorptive of the operative wavelength range. The etchant liquid is heated by delivering radiation through the wall of a processing chamber. This permits processing chambers to be formed of materials (e.g., fluoropolymers) that cannot be used in conventional systems that must conduct heat through the wall of the processing chamber.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: July 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: David A. Palsulich, Ronald F. Baldner
  • Publication number: 20140151704
    Abstract: Embodiments of preparing substrates for subsequent bonding with semiconductor layer are described herein. A substrate may be prepared with one or more chemicals or a sacrificial layer to limit or remove substrate contaminants and reduce substrate surface damage. Other embodiments may be described and claimed.
    Type: Application
    Filed: March 14, 2013
    Publication date: June 5, 2014
    Applicant: PEREGRINE SEMICONDUCTOR CORPORATION
    Inventor: Peregrine Semiconductor Corporation
  • Publication number: 20140147990
    Abstract: Provided apparatus and methods for back side passivation of a substrate. The systems comprise an elongate support with an open top surface forming a support ring so that when a substrate is on the support ring, a cavity is formed within the elongate support. A plasma generator is coupled to the cavity to generate a plasma within the cavity to deposit a passivation film on the back side of the substrate.
    Type: Application
    Filed: November 22, 2013
    Publication date: May 29, 2014
    Inventors: Lara Hawrylchak, Jeff Tobin
  • Patent number: 8697503
    Abstract: A method of manufacturing a thin film electronic device includes applying a plastic coating to a rigid carrier substrate using a wet casting process, the plastic coating forming a plastic substrate and include a transparent plastic material doped with a UV absorbing additive. Thin film electronic elements are formed over the plastic substrate, and the rigid carrier substrate is released from the plastic substrate. This method forms transparent substrate materials suitable for a laser release process, through doping of the plastic material of the substrate with a UV absorber. This UV absorber absorbs in the wavelength of the lift-off laser (for example 308-351 nm, or 355 nm) with a very high absorption.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: April 15, 2014
    Assignee: Koninklijke Philips N.V.
    Inventors: Eliav Itzhak Haskal, David James McCulloch, Dirk Jan Broer
  • Patent number: 8652943
    Abstract: A method of processing a substrate is provided. The method includes providing a substrate, performing a device forming process on the substrate, and cleaning the substrate. The step of cleaning the substrate includes cleaning the substrate with an atomic spray and rinsing the substrate with deionized water.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: February 18, 2014
    Assignee: United Microelectronics Corp.
    Inventor: Tsung-Hsun Tsai
  • Publication number: 20140024201
    Abstract: A method for fabricating a semiconductor device include forming devices on a front side of a semiconductor substrate, forming a hydrogen-containing layer on a back side of the semiconductor substrate, forming an outgassing prevention layer over the hydrogen-containing layer, and performing a hydrogen treatment process to diffuse hydrogen, contained in the hydrogen-containing layer, into the semiconductor substrate.
    Type: Application
    Filed: December 19, 2012
    Publication date: January 23, 2014
    Applicant: SK HYNIX INC.
    Inventor: Byung-Il KWAK
  • Patent number: 8592937
    Abstract: A pyroelectric detector includes a substrate, a support member and a pyroelectric detection element, which includes a capacitor, first and second reducing gas barrier layers, an insulating layer, a plug and a second electrode wiring layer. The first reducing gas barrier layer covers at least a second electrode and a pyroelectric body of the capacitor, and has a first opening that overlaps the second electrode in plan view. The insulating layer covers at least the first reducing gas barrier layer, and has a second opening that overlaps the first opening in plan view. The plug is disposed in the first and second openings and connected to the second electrode. The second electrode wiring layer is formed on the insulating layer and connected to the plug. The second reducing gas barrier layer is formed on the insulating layer and the second electrode wiring layer and covers at least the plug.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: November 26, 2013
    Assignee: Seiko Epson Corporation
    Inventor: Takafumi Noda
  • Publication number: 20130309845
    Abstract: A method of processing a substrate is provided. The method includes providing a substrate, performing a device forming process on the substrate, and cleaning the substrate. The step of cleaning the substrate includes cleaning the substrate with an atomic spray and rinsing the substrate with deionized water.
    Type: Application
    Filed: May 17, 2012
    Publication date: November 21, 2013
    Applicant: UNITED MICRO ELECTRONICS CORP.
    Inventor: Tsung-Hsun Tsai
  • Patent number: 8568537
    Abstract: An epitaxial wafer comprises a silicon substrate, a gettering epitaxial film formed thereon and containing silicon and carbon, and a main silicon epitaxial film formed on the gettering epitaxial film, in which the gettering epitaxial film has a given carbon atom concentration and carbon atoms are existent between its silicon lattices.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: October 29, 2013
    Assignee: Sumco Corporation
    Inventors: Naoshi Adachi, Tamio Motoyama