Abstract: A semiconductor device comprises a semiconductor substrate, a first electrode formed on a first main surface of the semiconductor substrate, and a second electrode formed on a second main surface of the semiconductor substrate. The semiconductor substrate includes a first region in which a density of oxygen-vacancy defects is greater than a density of vacancy cluster defects, and a second region in which the density of vacancy cluster defects is greater than the density of oxygen-vacancy defects.

Abstract: It is shown in the invention a method for manufacturing a semiconductor wafer structure with an active layer for impurity removal, which method comprises phases of depositing a first layer on a first wafer surface for providing an active layer, an optional phase of preparation for said first layer for next phase, growing thermal oxide layer on a second wafer, bonding said first and second wafers into a stack, annealing the stack for a crystalline formation in said thermal oxide layer as a second layer, and thinning said first wafer to a pre-determined thickness. The invention concerns also a wafer manufactured according to the method, chip that utilizes such a wafer structure and an electronic device utilizing such a chip.

Abstract: The invention provides a method for activating impurity element added to a semiconductor and performing gettering process in shirt time, and a thermal treatment equipment enabling to perform such the heat-treating.

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first insulating layer formed over the semiconductor substrate, and a first semiconductor layer formed over the first insulation layer. At least one gettering region is formed in at least one of the first insulating layer and the first semiconductor layer. The gettering region includes a plurality of gettering sites, and at least one gettering site includes one of a precipitate, a dispersoid, an interface with the dispersoid, a stacking fault and a dislocation.

Abstract: An IC includes a substrate having a semiconductor top surface and a bottom surface, wherein the semiconductor top surface includes one or more active circuit components and a plurality of through silicon vias (TSVs) extending through the substrate. The plurality of TSVs include an outer dielectric liner. The dielectric liner includes at least one halogen or a Group 15 element metal gettering agent in an average concentration from 1 to 10 atomic %. A metal diffusion barrier layer is on the dielectric liner and a metal filler is on the metal barrier layer. The metal gettering agent getters metal filler that escapes the metal barrier layer.

Abstract: A method for fabricating a three-dimensional semiconductor memory device including three-dimensionally arranged transistors includes forming a thin film structure comprising a plurality of thin films on a semiconductor substrate, patterning the thin film structure such that a penetration region is formed to expose the semiconductor substrate, forming a polycrystalline semiconductor layer to cover the resultant structure where the penetration region is formed, patterning the semiconductor layer to locally form a semiconductor pattern within the penetration region, and performing a post-treatment process to treat the semiconductor layer or the semiconductor pattern with a post-treatment material containing hydrogen or deuterium.

Abstract: The present invention includes a substrate structural body having a high electrostatic chuck force at a low voltage even when an insulated board is used, and a method for manufacturing the substrate structural body. As the substrate structural body, there is provided a substrate structural body for attaining its fixing by an electrostatic chuck mechanism, comprising at least a first polycrystalline silicon film formed on the back surface of a substrate comprised of an insulating material or its back and side surfaces, wherein a top layer of part of the back surface or the back and side surfaces is of a first silicon insulating film.

Abstract: A method of manufacturing a thin silicon wafer by slicing a silicon single crystal includes: a thinning step S3 of polishing a rear surface of the silicon wafer to reduce the thickness of the silicon wafer after a device structure is formed on a front surface of the silicon wafer; a mirror surface forming step S4 of processing the rear surface of the silicon wafer into a mirror surface using a chemical mechanical polishing method; and a modifying step S5 of dispersing abrasive grains that are harder than those used to form the mirror surface in the mirror surface forming process and forming a damaged layer, serving as a gettering sink for heavy metal, on the rear surface of the silicon wafer using the chemical mechanical polishing method. The thickness T5b of the damaged layer W5b in a wafer depth direction is set by the chemical mechanical polishing method in the modifying step S5 to control the gettering capability of the damaged layer.

Abstract: The invention provides a method for activating impurity element added to a semiconductor and performing gettering process in shirt time, and a thermal treatment equipment enabling to perform such the heat-treating.

Abstract: A manufacturing method of a polycrystalline solar cell is disclosed. A polycrystalline silicon solar cell in accordance with the present invention performs crystallization-annealing amorphous silicon with a metal catalyst so as to reduce a crystallization temperature. The manufacturing method of a solar cell in accordance with the present invention includes the steps of (a) forming a first amorphous silicon layer on a substrate; (b) forming a second amorphous silicon layer on the first amorphous silicon layer; (c) forming a metal layer on the second amorphous silicon layer; (d) performing crystallization-annealing the second amorphous silicon layer; and (e) forming a third amorphous silicon layer on a resulting crystalline silicon layer of the step (d).

Abstract: A manufacturing method of a semiconductor device comprises a process of doping conductive impurities in a silicon carbide substrate, a process of forming a cap layer on a surface of the silicon carbide substrate, a process of activating the conductive impurities doped in the silicon carbide substrate, a process of oxidizing the cap layer after a first annealing process, and a process of removing the oxidized cap layer. It is preferred that the cap layer is formed from material that includes metal carbide. Since the oxidation onset temperature of metal carbide is comparatively low, the oxidization of the cap layer becomes easy if metal carbide is included in the cap layer. Specifically, it is preferred that the cap layer is formed from metal carbide that has an oxidation onset temperature of 1000 degrees Celsius or below, such as tantalum carbide.

Abstract: A masking paste used as a mask for controlling diffusion when diffusing a p-type dopant and an n-type dopant into a semiconductor substrate and forming a high-concentration p-doped region and a high concentration n-doped region is provided that contains at least a solvent, a thickening agent, and SiO2 precursor and/or a TiO2 precursor. Further, a manufacturing method of a solar cell is provided in which the masking paste is pattern-formed on the semiconductor substrate and then the p-type dopant and the n-type dopant are diffused.

Abstract: Embodiments of the present invention describe a method and device of preventing delamination of semiconductor layers in a semiconductor device. The semiconductor device comprises a substrate with an interlayer dielectric (ILD). A protection layer is deposited on the ILD. Next, a getter layer is formed on the protection layer to remove any native oxides on the protection layer. A capping layer is then deposited on the getter layer to prevent oxidation of the getter layer. Next, a semiconductor layer is formed on the capping layer. An oxide layer is then deposited on the semiconductor layer. Subsequently, a buffered oxide etch solution is used to remove the oxide layer. By removing the native oxides on the protection layer, the getter layer prevents the reaction between the buffered oxide etch solution and the native oxides which may cause delamination of the semiconductor layer and protection layer.

Abstract: Upgraded metallurgical grade silicon (UMG-Si) is fabricated by a ‘green’ (environmental protected) external gettering procedure. Impurities concentration of the fabricated UMG-Si is reduced for 100 times than its source material. The UMG-Si obtained has a purity ratio reaching 4N to 6N. Thus, substrates made of the UMG-Si can be used in solar cells and related photoelectrical applications.

Abstract: An nitride semiconductor device according to the present invention is a nitride semiconductor device including: an n-GaN substrate 10; a semiconductor multilayer structure 100 formed on a principal face of the n-GaN substrate 10, the semiconductor multilayer structure 100 including a p-type region and an n-type region; a p-side electrode 32 which is in contact with a portion of the p-type region included in the semiconductor multilayer structure 100; and an n-side electrode 34 provided on the rear face of the n-GaN substrate 10. The rear face of the n-GaN substrate includes a nitrogen surface, such that a carbon concentration at an interface between the rear face and the n-side electrode 34 is adjusted to 5 atom % or less.

Abstract: A method of manufacturing a semiconductor device may include, but is not limited to the following processes. An epitaxial layer is formed on a semiconductor substrate. A semiconductor element is formed in the epitaxial layer. The semiconductor substrate is removed from the epitaxial layer.

Abstract: The specification teaches a system for manufacturing microelectronic, microoptoelectronic or micromechanical devices (microdevices) in which a contaminant absorption layer improves the life and operation of the microdevice. In an embodiment, a system for manufacturing the devices includes efficiently integrating a getter material in multiple microdevices.

Abstract: The invention provides methods and structures for reducing surface dislocations of a semiconductor layer, and can be employed during the epitaxial growth of semiconductor structures and layers comprising III-nitride materials. Embodiments involve the formation of a plurality of dislocation pit plugs to prevent propagation of dislocations from an underlying layer of material into a following semiconductor layer of material.

Abstract: A method of fabricating an epi-wafer includes providing a wafer including boron by cutting a single crystal silicon ingot, growing an insulating layer on one surface of the wafer, performing thermal treatment of the wafer, removing the insulating layer formed on one surface of the wafer, mirror-surface-grinding one surface of the wafer, and growing an epitaxial layer on one surface of the wafer and forming a high-density boron layer within the wafer that corresponds to the interface between the wafer and the epitaxial layer.

Abstract: A method of manufacturing a solar cell by providing a gallium arsenide carrier with a prepared bonding surface; providing a sapphire substrate; bonding the gallium arsenide carrier and the sapphire substrate to produce a composite structure; detaching the bulk of the gallium arsenide carrier from the composite structure, leaving a gallium arsenide growth substrate on the sapphire substrate; and depositing a sequence of layers of semiconductor material forming a solar cell on the growth substrate. For some solar cells, the method further includes mounting a surrogate second substrate on top of the sequence of layers of semiconductor material forming a solar cell; and removing the growth substrate.

Abstract: The present invention relates to multicrystalline p-type silicon wafers with high lifetime. The silicon wafers contain 0.2-2.8 ppma boron and 0.06-2.8 ppma phosphorous and/or arsenic and have been subjected to phosphorous diffusion and phosphorous gettering at a temperature of above 925° C. The invention further relates to a method for production of such multicrystalline silicon wafers and to solar cells comprising such silicon wafers.

Abstract: In an example embodiment of the method of manufacturing an epitaxial semiconductor substrate, a gettering layer is grown over a semiconductor substrate. An epitaxial layer may then be formed over the gettering layer, and a semiconductor device may be formed on the epitaxial layer.

Abstract: A solid-state image pick-up device is provided which includes a semiconductor substrate main body which has an element forming layer and a gettering layer provided on an upper layer thereof; photoelectric conversion elements, each of which includes a first conductive type region, provided in the element forming layer; and a dielectric film which is provided on an upper layer of the gettering layer and which induces a second conductive type region in a surface of the gettering layer.

Abstract: Provided are methods of removing water adsorbed or bonded to a surface of a semiconductor substrate, and methods of depositing an atomic layer using the method of removing water described herein. The method of removing water includes applying a chemical solvent to the surface of a semiconductor substrate, and removing the chemical solvent from the surface of the semiconductor substrate.

Abstract: First, a base structure provided with the main parts of a memory cell is prepared, and a lower electrode comprising a polycrystalline silicon film is thereafter formed on the base structure. Next, the surface of the lower electrode is thermally nitrided at a predetermined temperature to form a silicon nitride film. In the thermal nitridation of the lower electrode, the temperature is increased to a predetermined nitriding temperature, after which the temperature is reduced at a rate that is more gradual than usual. Aluminum oxide (Al2O3) or another metal oxide dielectric film is thereafter formed as the capacitive insulating film on the lower electrode, and an upper electrode is formed on the capacitive insulating film.

Abstract: In one embodiment, a multi-layer extrinsic gettering structure includes plurality of polycrystalline semiconductor layers each separated by a dielectric layer.

Abstract: The invention provides methods which can be applied during the epitaxial growth of two or more layers of semiconductor materials so that the qualities of successive layer are successively improved. In preferred embodiments, surface defects present in one epitaxial layer are capped with a masking material. A following layer is then grown so it extends laterally above the caps according to the known phenomena of epitaxial lateral overgrowth. The methods of the invention can be repeated by capping surface defects in the following layer and then epitaxially growing a second following layer according to ELO. The invention also includes semiconductor structures fabricated by these methods.

Abstract: A silicon epitaxial layer 2 is grown in vapor phase on a silicon single crystal substrate 1 manufactured by the Czochralski method, and doped with boron so as to adjust the resistivity to 0.02 ?·cm or below, oxygen precipitation nuclei 11 are formed in the silicon single crystal substrate 1, by carrying out annealing at 450° C. to 750° C., in an oxidizing atmosphere, for a duration of time allowing formation of a silicon oxide film only to as thick as 2 nm or below on the silicon epitaxial layer 2 as a result of the annealing, and thus-formed silicon oxide film 3 is etched as the first cleaning after the low-temperature annealing, using a cleaning solution. By this process, the final residual thickness of the silicon oxide film can be suppressed only to a level equivalent to native oxide film, without relying upon the hydrofluoric acid cleaning.

Abstract: Described is a wet chemical surface treatment involving NH4OH that enables extremely strong direct bonding of two wafer such as semiconductors (e.g., Si) to insulators (e.g., SiO2) at low temperatures (less than or equal to 400° C.). Surface energies as high as ˜4835±675 mJ/m2 of the bonded interface have been achieved using some of these surface treatments. This value is comparable to the values reported for significantly higher processing temperatures (less than 1000° C.). Void free bonding interfaces with excellent yield and surface energies of ˜2500 mJ/m2 have also be achieved herein.

Abstract: The present invention provides a method for manufacturing a silicon single crystal wafer, in which a silicon single crystal wafer that is fabricated based on a Czochralski method and has an entire plane in a radial direction formed of an N region is subjected to a rapid thermal annealing in an oxidizing atmosphere, an oxide film formed in the rapid thermal annealing in the oxidizing atmosphere is removed, and then a rapid thermal annealing is carried out in a nitriding atmosphere, an Ar atmosphere, or a mixed atmosphere of these atmospheres. As a result, there can be provided the manufacturing method that can inexpensively manufacture a silicon single crystal wafer both in which a DZ layer is formed in a wafer surface layer to provide excellent device characteristics and in which an oxide precipitate functioning as a gettering site can be sufficiently formed in a bulk region.

Abstract: The present invention provides a method for blocking the dislocation propagation of a semiconductor. A semiconductor layer is formed by epitaxial process on a substrate. A plurality of recesses is formed on the semiconductor layer by etching fragile locations of the semiconductor layer where dislocation occurs. Thereafter, a blocking layer is formed on each of the plurality of recesses. The aforesaid semiconductor layer undergoes epitaxial process again on the aforesaid semiconductor layer, and laterally overgrows to redirect the dislocation defects.

Abstract: A method of forming a shadow layer on a wafer bevel region is provided. First, a substrate having the wafer bevel region and a central region is provided. Thereafter, an upper insulator and a lower insulator are provided. The upper insulator is disposed on an upper surface of the substrate and at least covers the central region. The lower insulator is disposed on a lower surface of the substrate and at least covers the central region. A shadow layer is then formed on the upper surface which is not covered by the upper insulator and on the lower surface which is not covered by the lower insulator. Next, the upper insulator and the lower insulator are removed.

Abstract: One aspect of this disclosure relates to a method for creating proximity gettering sites in a silicon on insulator (SOI) wafer. In various embodiments of this method, a relaxed silicon germanium region is formed over an insulator region of the SOI to be proximate to a device region. The relaxed silicon germanium region generates defects to getter impurities from the device region. Other aspects are provided herein.

Abstract: A silicon wafer is produced through the steps of forming a silicon ingot by a CZ method with an interstitial oxygen concentration of not more than 7.0×1017 atoms/cm3, slicing a wafer from the silicon ingot after doping the silicon ingot with phosphorus, forming a polysilicon layer or a strained layer on one main surface of the wafer, mirror polishing the other main surface of the wafer, and performing a heat treatment for the wafer in a non-oxidizing atmosphere.

Abstract: Methods for fabricating semiconductor structures with backside stress layers are provided. In one exemplary embodiment, the method comprises the steps of providing a semiconductor device formed on and within a front surface of a semiconductor substrate. The semiconductor device comprises a channel region. A plurality of dielectric layers is formed overlying the semiconductor device. The plurality of dielectric layers comprises conductive connections that are in electrical communication with the semiconductor device. A backside stress layer is formed on a back surface of the semiconductor substrate. The backside stress layer is configured to apply to the channel region of the semiconductor device a uniaxial compressive or tensile stress that, with stresses applied by the plurality of dielectric layers, results in an overall stress exerted on the channel region to achieve a predetermined overall strain of the channel region.

Abstract: One aspect of this disclosure relates to a method for creating proximity gettering sites in a silicon on insulator (SOI) wafer. In various embodiments of this method, a relaxed silicon germanium region is formed over an insulator region of the SOI to be proximate to a device region. The relaxed silicon germanium region generates defects to getter impurities from the device region. Other aspects are provided herein.

Abstract: The present application relates to a multiple component which is to be subsequently individualized by forming components containing active structures, in addition to a corresponding component which can be used in microsystem technology systems. The multiple component and/or component comprises a flat substrate and also a flat cap structure which are bound to each other such that they surround at least one first and one second cavity per component, which are sealed against each other and towards the outside. The first of the two cavities is provided with getter material and due to the getter material has a different internal pressure and/or a different gas composition than the second cavity. The present application also relates to a method for producing the type of component and/or components for which gas mixtures of various types of gas have a different absorption ratio in relation to the getter material.

Abstract: A wafer manufacturing method includes after flattening both upper and lower surfaces of a wafer sliced from a single crystal ingot, processing the wafer having damage on both surfaces caused by the flattening, so as to obtain desired damage at least on the lower surface of the wafer, the desired damage having a damage depth ranging from 5 nm-10 ?m; forming a polysilicon layer at least on the lower surface of the wafer while the damage on the lower surface of the wafer remains; single-wafer etching the upper surface of the wafer; and final polishing the upper surface of the wafer to have a mirrored surface, after the single-wafer etching.

Abstract: This method for manufacturing a silicon substrate for a solid-state imaging device, includes: a carbon compound layer forming step of forming a carbon compound layer on the surface of a silicon substrate; an epitaxial step of forming a silicon epitaxial layer on the carbon compound layer; and a heat treatment step of subjecting the silicon substrate having the epitaxial layer formed thereon to a heat treatment at a temperature of 600 and 800° C. for 0.25 to 3 hours so as to form gettering sinks that are complexes of carbon and oxygen below the epitaxial layer. This silicon substrate for a solid-state imaging device is manufactured by the above-mentioned method and includes: n epitaxial layer positioned on the surface of a silicon substrate; and a gettering layer which is positioned below the epitaxial layer and includes BMDs having a size of 10 to 100 nm at a concentration of 1.0×106 to 1.0×109 atoms/cm3.

Abstract: In a semiconductor substrate on which are formed an N-type MOS transistor and a P-type MOS transistor, the gate electrode of the N-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the gate electrode of the P-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the concentration of carbon contained in the former tungsten film is less than the concentration of carbon contained in the latter tungsten film.

Abstract: A non-volatile semiconductor storage device having a high-dielectric-constant insulator and a manufacturing method thereof suitable for miniaturization are disclosed. According to one aspect of the present invention, it is provided a semiconductor storage device comprising a semiconductor substrate, a plurality of first conductor layers formed on the semiconductor substrate through a first insulator, an isolation formed between the plurality of first conductor layers, a silicon oxide film formed on the first conductor layer, a high-dielectric-constant insulator formed on the silicon oxide film and the isolation and being diffused silicon and oxygen at least in a surface thereof contacting with the silicon oxide film, and a second conductor film formed above the high-dielectric-constant insulator.

Abstract: Problems in prior art regarding an n-channel TFT in the source/drain gettering method are solved. In the n-channel TFT, its source/drain regions contain only an n-type impurity. Therefore, compared to a p-channel TFT whose source/drain regions contain an n-type impurity and a higher concentration of p-type impurity, the gettering efficiency is inferior in a channel region of the n-channel transistor. Accordingly, the problem of inferior gettering efficiency in the n-channel TFT can be solved by providing at an end of its source/drain regions a highly efficient gettering region that contains an n-type impurity and a p-type impurity both with the concentration of the p-type impurity set higher than the concentration of the n-type impurity.

Abstract: This invention is directed to a process for heat-treating a single crystal silicon segment to influence the profile of minority carrier recombination centers in the segment. The segment is subjected to a heat-treatment to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon. The segment is then cooled at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a segment having the desired vacancy concentration profile. Platinum atoms are then in-diffused into the silicon matrix such that the resulting platinum concentration profile is substantially related to the concentration profile of the crystal lattice vacancies.

Abstract: A method of forming a multi-doped junction on a substrate is disclosed. The method includes providing the substrate doped with boron, the substrate including a first substrate surface with a first surface region and a second surface region. The method also includes depositing a first set of nanoparticles on the first surface region, the first set of nanoparticles including a first dopant. The method further includes heating the substrate in an inert ambient to a first temperature and for a first time period creating a first densified film, and further creating a first diffused region with a first diffusion depth in the substrate beneath the first surface region.

Abstract: A method for removing impurities from at least one semiconductor device layer during manufacturing of a semiconductor device is disclosed. The semiconductor device layer has a compound semiconductor material and/or germanium. Each heating process performed during the manufacturing of the semiconductor device after provision of the semiconductor device layer has a low thermal budget determined by temperatures equal to or lower than about 900° C. and time periods equal to or lower than about 5 minutes. In one aspect, the method includes providing a germanium gettering layer with a higher solubility for the impurities than the semiconductor device layer. The germanium gettering layer is provided at least partly in direct or indirect contact with the at least one semiconductor device layer, such that impurities can diffuse from the at least one semiconductor device layer to the germanium gettering layer.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of forming an insulating material layer. The method includes forming a barrier layer and forming a rare earth element-containing material layer over the barrier layer.

Abstract: A method of reducing the amount of halogenated materials in a halogen-containing environment. The method comprises introducing an aluminum compound into the halogen-containing environment, reacting the aluminum compound with the halogenated material to form a gaseous reaction product, and removing the gaseous reaction product from the environment. The aluminum compound may be a trialkylaluminum compound, an alane, an alkylaluminum hydride, an alkylaluminum halide, an alkylaluminum sesquihalide, or an aluminum sesquihalide. The aluminum compound may alternatively form a solid aluminum product, which is deposited on a surface associated with the halogen-containing environment or onto a semiconductor disposed therewithin. The halogenated material is incorporated into the solid aluminum product, forming an inert film within which the halogenated material is trapped.

Abstract: A device and a device manufacturing process. First, a gettering layer is formed on the bottom surface of a silicon substrate. Gates having a MOS structure are then formed on the principal surface of the silicon substrate, and the gettering layer is removed. According to this manufacturing method, the formation of the gates having a MOS structure is performed such that the gettering layer getters dissolved oxygen present in the silicon substrate. This reduces the concentration of dissolved oxygen in the silicon substrate, resulting in improved device characteristics.

Abstract: A manufacturing method of a semiconductor device comprises a process of doping conductive impurities in a silicon carbide substrate, a process of forming a cap layer on a surface of the silicon carbide substrate, a process of activating the conductive impurities doped in the silicon carbide substrate, a process of oxidizing the cap layer after a first annealing process, and a process of removing the oxidized cap layer. It is preferred that the cap layer is formed from material that includes metal carbide. Since the oxidation onset temperature of metal carbide is comparatively low, the oxidization of the cap layer becomes easy if metal carbide is included in the cap layer. Specifically, it is preferred that the cap layer is formed from metal carbide that has an oxidation onset temperature of 1000 degrees Celsius or below, such as tantalum carbide.

Abstract: A method of manufacturing a thin silicon wafer by slicing a silicon single crystal includes: a thinning step S3 of polishing a rear surface of the silicon wafer to reduce the thickness of the silicon wafer after a device structure is formed on a front surface of the silicon wafer; a mirror surface forming step S4 of processing the rear surface of the silicon wafer into a mirror surface using a chemical mechanical polishing method; and a modifying step S5 of dispersing abrasive grains that are harder than those used to form the mirror surface in the mirror surface forming process and forming a damaged layer, serving as a gettering sink for heavy metal, on the rear surface of the silicon wafer using the chemical mechanical polishing method. The thickness T5b of the damaged layer W5b in a wafer depth direction is set by the chemical mechanical polishing method in the modifying step S5 to control the gettering capability of the damaged layer.