By Layers Which Are Coated, Contacted, Or Diffused Patents (Class 438/476)
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Publication number: 20090218579Abstract: In a substrate heating apparatus, thermoelectrons generated by a filament (132) in a vacuum heating vessel (103) are accelerated to collide against a conductive heater (131) which forms one surface of the vacuum heating vessel (103), thus generating heat. The conductive heater (131) is made of carbon. At least one of the inner and outer surfaces of the conductive heater (131) is coated with tantalum carbide (TaC).Type: ApplicationFiled: February 24, 2009Publication date: September 3, 2009Applicant: CANON ANELVA ENGINEERING CORPORATIONInventor: Masami Shibagaki
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Publication number: 20090209090Abstract: A problem in the conventional technique is that metal contamination on a silicon carbide surface is not sufficiently removed in a manufacturing method of a semiconductor device using a monocrystalline silicon carbide substrate. Accordingly, there is a high possibility that the initial characteristics of a manufactured silicon carbide semiconductor device are deteriorated and the yield rate is decreased. Further, it is conceivable that the metal contamination has an adverse affect even on the long-term reliability of a semiconductor device. In a manufacturing method of a semiconductor device using a monocrystalline silicon carbide substrate, there is applied a metal contamination removal process, on a silicon carbide surface, including a step of oxidizing the silicon carbide surface and a step of removing a film primarily including silicon dioxide formed on the silicon carbide surface by the step.Type: ApplicationFiled: November 11, 2008Publication date: August 20, 2009Inventors: Natsuki YOKOYAMA, Tomoyuki SOMEYA
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Patent number: 7572663Abstract: A method for manufacturing a CMOS image sensor is provided. The method can include forming an interlayer dielectric layer on a semiconductor substrate including a gate electrode, photodiode area, and LDD region; selectively removing the interlayer dielectric layer such that the interlayer dielectric layer remains on the photodiode area; performing a first heat treatment process; sequentially forming a first insulating layer and a second insulating layer on the semiconductor substrate, where the etching selectivity of the first insulating layer is different from the etching selectivity of the second insulating layer; selectively etching the second insulating layer to form spacers on sidewalls of the gate electrode; selectively removing the first insulating layer to expose a source/drain area and forming a high-density N-type diffusion area in the exposed source/drain area; performing a second heat treatment process; and forming a metal silicide layer the high-density N-type diffusion area.Type: GrantFiled: December 22, 2006Date of Patent: August 11, 2009Assignee: Dongbu Electronics, Co., Ltd.Inventor: Chang Hun Han
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Patent number: 7566957Abstract: The specification teaches a system for manufacturing microelectronic, microoptoelectronic or micromechanical devices (microdevices) in which a contaminant absorption layer improves the life and operation of the microdevice. In an embodiment, a system for manufacturing the devices includes efficiently integrating a getter material in multiple microdevices.Type: GrantFiled: October 31, 2007Date of Patent: July 28, 2009Assignee: SAES Getters S.p.A.Inventor: Marco Amiotti
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Publication number: 20090186466Abstract: A method for removing defects from a semiconductor surface is disclosed. The surface of the semiconductor is first coated with a protective layer, which is later thinned to selectively reveal portions of the protruding defects. The defects are then removed by etching. Finally, also the protective layer is removed. According to the method, inadvertent thinning of the surface is prevented and removal of the defects is obtained.Type: ApplicationFiled: March 26, 2009Publication date: July 23, 2009Applicant: HRL LABORATORIES, LLCInventor: Peter D. BREWER
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Publication number: 20090159897Abstract: A semiconductor processing component has an outer surface portion comprised of silicon carbide, the outer surface portion having a skin impurity level and a bulk impurity level.Type: ApplicationFiled: December 15, 2008Publication date: June 25, 2009Applicant: SAINT-GOBAIN CERAMICS & PLASTICS, INC.Inventors: Yeshwanth Narendar, Richard F. Buckley
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Patent number: 7544265Abstract: The invention relates to a method of fabricating a release substrate produced from semiconductor materials, the method comprising creating a reversible connection between two substrate release layers characterized in that the reversible connection is formed by a connecting layer produced using a first material as the basis, the connecting layer further comprising a nanoparticle concentrating zone of a second material disposed to facilitate release of the substrate, the first and second materials being selected to maintain the bonding energy of the reversible connection substantially constant even when the substrate is exposed to heat treatment.Type: GrantFiled: July 5, 2006Date of Patent: June 9, 2009Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Pierre Rayssac, legal representative, Gisele Rayssac, legal representative, Takeshi Akatsu, Olivier Rayssac
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Patent number: 7501330Abstract: A method of forming a high thermal conductivity diamond film and its associated structures comprising selectively nucleating a region of a substrate, and forming a diamond film on the substrate such that the diamond film has large grains, which are at least about 20 microns in size. Thus, the larger grained diamond film has greatly improved thermal management capabilities and improves the efficiency and speed of a microelectronic device.Type: GrantFiled: December 5, 2002Date of Patent: March 10, 2009Assignee: Intel CorporationInventors: Kramadhati V. Ravi, Michael C. Garner
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Patent number: 7494851Abstract: A thin film transistor array substrate and a method for manufacturing the same is disclosed, in which it is possible to prevent mobile ions contained in a substrate from penetrating into a semiconductor layer by the gettering effect or neutralization in case soda lime glass is used for the substrate. The method includes forming a buffer layer on a substrate; doping impurity ions in the buffer layer; and forming a pixel electrode and a thin film transistor including a semiconductor layer on the buffer layer.Type: GrantFiled: December 6, 2004Date of Patent: February 24, 2009Assignee: LG Display Co., Ltd.Inventors: Jae Young Oh, Seung Hee Nam
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Patent number: 7488670Abstract: An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming a strained channel region in semiconductor devices. Embodiments include forming a stressor layer over an amorphous portion of the semiconductor device at an intermediate stage of fabrication. The device is masked and strain in a portion of the stressor layer is relaxed. Recrystallizing the amorphous portion of the intermediate device transfers strain from the stressor to the substrate. At least a portion of the strain remains in the substrate through subsequent device fabrication, thereby improving performance of the completed device. In other embodiments, a tensile stressor layer is formed over a first portion of the device, and a compressive stressor layer is formed over a second portion. A tensile stressor layer forms a compressive channel in a PMOS device, and a compressive stressor forms a tensile channel in an NMOS device.Type: GrantFiled: July 13, 2005Date of Patent: February 10, 2009Assignee: Infineon Technologies AGInventors: Roman Knoefler, Armin Tilke
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Patent number: 7485551Abstract: The present invention relates to a method of fabricating a semiconductor-on-insulator-type heterostructure that includes at least one insulating layer interposed between a receiver substrate of semiconductor material and an active layer derived from a donor substrate of semiconductor material. The method includes the steps of bonding and active layer transfer. Prior to bonding, an atomic species which is identical or isoelectric with the insulating layer material is implanted in the insulating layer. The implantation forms a trapping layer, which can retain gaseous species present in the various interfaces of the heterostructure, thereby limiting formation of defects on the surface of the active layer.Type: GrantFiled: January 5, 2006Date of Patent: February 3, 2009Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventor: Xavier Hebras
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Publication number: 20090029528Abstract: The present invention generally provides apparatus and method for forming a clean and damage free surface on a semiconductor substrate. One embodiment of the present invention provides a system that contains a cleaning chamber that is adapted to expose a surface of substrate to a plasma cleaning process prior to forming an epitaxial layer thereon. In one embodiment, a method is employed to reduce the contamination of a substrate processed in the cleaning chamber by depositing a gettering material on the inner surfaces of the cleaning chamber prior to performing a cleaning process on a substrate. In one embodiment, oxidation and etching steps are repeatedly performed on a substrate in the cleaning chamber to expose or create a clean surface on a substrate that can then have an epitaxial placed thereon. In one embodiment, a low energy plasma is used during the cleaning step.Type: ApplicationFiled: June 25, 2008Publication date: January 29, 2009Inventors: Errol Antonio C. SANCHEZ, Johanes SWENBERG, David K. CARLSON, Roisin L. DOHERTY
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Publication number: 20090023273Abstract: A method of fabricating a semiconductor device comprising forming a transistor on a semiconductor substrate, forming an interlayer insulating film on the semiconductor substrate to cover the transistor, forming a passivation film on the interlayer insulating film, and annealing the semiconductor substrate having the passivation film in a gas atmosphere comprising at least one gas selected from the group of boron, silicon and hydrogen.Type: ApplicationFiled: July 18, 2008Publication date: January 22, 2009Applicant: DONGBU HITEK CO., LTD.Inventor: Han Choon LEE
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Patent number: 7473614Abstract: Embodiments of a silicon-on-insulator (SOI) wafer having an etch stop layer overlying the buried oxide layer, as well as embodiments of a method of making the same, are disclosed. The etch stop layer may comprise silicon nitride, nitrogen-doped silicon dioxide, or silicon oxynitride, as well as some combination of these materials. Other embodiments are described and claimed.Type: GrantFiled: November 12, 2004Date of Patent: January 6, 2009Assignee: Intel CorporationInventors: Peter G. Tolchinsky, Martin D. Giles, Michael L. McSwiney, Mohamad Shaheen, Irwin Yablok
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Publication number: 20080296612Abstract: Method of producing a vertically inhomogeneous platinum or gold distribution in a semiconductor substrate with a first and a second surface opposite the first surface, with diffusing (100) platinum or gold into the semiconductor substrate from one of the first and second surfaces of the semiconductor substrate, removing (102) platinum- or gold-comprising residues remaining on the one of the first and second surfaces after diffusing the platinum or gold, forming (104) a phosphorus- or boron-doped surface barrier layer on the first or second surface, and heating (105) the semiconductor substrate for local gettering of the platinum or gold by the phosphorus- or boron-doped surface barrier layer.Type: ApplicationFiled: April 25, 2008Publication date: December 4, 2008Inventors: Gerhard Schmidt, Josef Bauer
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Patent number: 7459379Abstract: When a semiconductor film is irradiated with laser light, the semiconductor film is instantaneously melted and expand locally. In order to reduce internal stress generated by this expansion, strain is locally generated in the semiconductor film. Accordingly, a variation is caused among portions with strain and portions without strain, and a variation is caused also by a difference in extent of strain. According to the present invention, after laser light irradiation, an oxide film (referred to as a chemical oxide) is formed by using a solution containing ozone (typically, ozone water) to form an oxide film of 1 to 10 nm in total, and further, a heat treatment for reducing strain of a semiconductor film (a heat treatment of heating the semiconductor film instantaneously to approximately 400 to 1000° C.) is performed.Type: GrantFiled: March 25, 2005Date of Patent: December 2, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Chiho Kokubo, Shunpei Yamazaki, Tamae Takano, Hiroaki Irie
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Patent number: 7456084Abstract: There is provided a method of fabricating a wafer, comprising depositing semiconductor material into a recess in a setter, moving the setter through a heating/cooling region to subject the semiconductor material to a temperature profile, and removing a wafer from the recess. The size and shape of the wafer are substantially equal to the size of the wafer when it is used. As a result, the wafer can be fabricated in any desired shape and with any of a variety of surface structural features and/or internal structural features. The temperature profile can be closely controlled, enabling production of wafers having structural features not previously obtainable. There are also provided wafers formed by such methods and setters for use in such methods.Type: GrantFiled: January 28, 2005Date of Patent: November 25, 2008Assignee: Heritage Power LLCInventors: Ralf Jonczyk, Scott L. Kendall, James A. Rand
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Patent number: 7452788Abstract: A linear pulse laser beam to be applied to an illumination surface is so formed as to have, at the focus, an energy profile in the width direction which satisfies inequalities 0.5L1?L2?L1 and 0.5L1?L3?L1 where assuming that a maximum energy is 1, L1 is a beam width of two points having an energy of 0.95 and L1+L2+L3 is a beam width of two points having an energy of 0.70, L2 and L3 occupying two peripheral portions of the beam width. According to another aspect of the invention, a compound-eye-like fly-eye lens for expanding a pulse laser beam in a sectional manner is provided upstream of a cylindrical lens for converging the laser beam into a linear beam.Type: GrantFiled: February 9, 2007Date of Patent: November 18, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Naoto Kusumoto, Koichiro Tanaka
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Publication number: 20080224269Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first insulating layer formed over the semiconductor substrate, and a first semiconductor layer formed over the first insulation layer. At least one gettering region is formed in at least one of the first insulating layer and the first semiconductor layer. The gettering region includes a plurality of gettering sites, and at least one gettering site includes one of a precipitate, a dispersoid, an interface with the dispersoid, a stacking fault and a dislocation.Type: ApplicationFiled: March 11, 2008Publication date: September 18, 2008Inventors: Young-Soo Park, Young-Nam Kim, Young-Sam Lim, Gi-Jung Kim, Pil-Kyu Kang
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Patent number: 7416928Abstract: An amorphous semiconductor film and a semiconductor film including an element selected from Group 15 of the periodic table are formed over a substrate. An island-shaped region including an island-shaped amorphous semiconductor film and an island-shaped semiconductor film is formed. A source electrode and a drain electrode are formed over the island-shaped region. The island-shaped semiconductor film that is not covered by the source electrode and the drain electrode is removed using the source electrode and the drain electrode as a mask. At this time, the thickness of the island-shaped amorphous semiconductor film is reduced, and a portion of the island-shaped amorphous semiconductor film is exposed. A catalytic element promoting crystallization is added into a region in which the island-shaped amorphous semiconductor film is exposed. By a heat treatment, the island-shaped amorphous semiconductor film is crystallized and the catalytic element is gettered.Type: GrantFiled: September 2, 2005Date of Patent: August 26, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tetsuya Kakehata, Yuuichi Takehara, Yasuhiro Jinbo
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Publication number: 20080197454Abstract: Techniques are here disclosed for a solar cell pre-processing. The method and system remove impurities from low-grade crystalline semiconductor wafers and include forming a low-grade semiconductor wafer having a substrate having high impurity content. The process and system damage at least one surface of the semiconductor wafer either in the semiconductor wafer forming step or in a separate step to form a region on the surface that includes a plurality of gettering centers. The gettering centers attract impurities from the substrate during subsequent processing. The subsequent processes include diffusing impurities from the substrate using a phosphorus gettering process that includes impregnating the surface with a phosphorus material for facilitating the formation of impurity clusters associated with the gettering centers.Type: ApplicationFiled: February 16, 2007Publication date: August 21, 2008Applicant: CaliSolar, Inc.Inventors: Jean Patrice Rakotoniana, Matthias Heuer, Fritz Kirscht, Dieter Linke, Kamel Ounadjela
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Patent number: 7407870Abstract: The present invention is a separation method for easy separation of an allover release layer with a large area. Further, the present invention is the separating method that is not subjected to restrictions in the use of substrates, such as a kind of substrate, during forming a release layer. A separation method comprising the steps of forming a metal film, a first oxide, and a semiconductor film containing hydrogen in this order; and bonding a support to a release layer containing the first oxide and the semiconductor film and separating the release layer bonded to the support from a substrate provided with the metal layer by a physical means.Type: GrantFiled: April 25, 2006Date of Patent: August 5, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Junya Maruyama, Yumiko Ohno, Toru Takayama, Yuugo Goto, Shunpei Yamazaki
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Publication number: 20080176384Abstract: Provided according to some embodiments of the present invention are methods of forming an impurity region in a semiconductor device. Such methods may include forming a pad oxide layer on a substrate; providing impurities to the substrate to form a preliminary impurity region in the substrate; performing a heat treatment process on the substrate while providing oxygen gas and an inert gas to the substrate; and removing the pad oxide layer. Methods according to embodiments of the invention may reduce pitting of the silicon substrate upon removal of the pad oxide layer.Type: ApplicationFiled: January 18, 2008Publication date: July 24, 2008Inventor: Kyung-Seok Ko
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Patent number: 7393762Abstract: A method of forming a nanostructure at low temperatures. A substrate that is reactive with one of atomic oxygen and nitrogen is provided. A flux of neutral atoms of at least one of nitrogen and oxygen is generated within a laser-sustained-discharge plasma source and a collimated beam of energetic neutral atoms and molecules is directed from the plasma source onto a surface of the substrate to form the nanostructure. The energetic neutral atoms and molecules in the plasma have an average kinetic energy in a range from about 1 eV to about 5 eV.Type: GrantFiled: November 21, 2006Date of Patent: July 1, 2008Assignee: Los Alamos National Secruity, LLCInventors: Mark Hoffbauer, Alex Mueller
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Patent number: 7393761Abstract: A method for treating a gate stack in the fabrication of a semiconductor device by providing a substrate containing a gate stack having a dielectric layer formed on the substrate and a metal-containing gate electrode layer formed on the high-k dielectric layer, forming low-energy excited dopant species from a process gas in a plasma, and exposing the gate stack to the excited dopant species to incorporate a dopant into the gate stack. The method can be utilized to tune the workfunction of the gate stack.Type: GrantFiled: January 31, 2005Date of Patent: July 1, 2008Assignee: Tokyo Electron LimitedInventors: Cory Wajda, Gert Leusink
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Publication number: 20080121963Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of forming an insulating material layer. The method includes forming a barrier layer and forming a rare earth element-containing material layer over the barrier layer.Type: ApplicationFiled: November 29, 2006Publication date: May 29, 2008Inventor: Shrinivas Govindarajan
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Patent number: 7348188Abstract: Various kinds of metal elements existing on the surface of a wafer are analyzed with higher sensitivity. A high concentration HF solution is dropped onto a surface of a wafer. By providing the droplets of high concentration HF solution, the native oxide film on the surface of the wafer is dissolved into the solution, and the metal elements or compounds thereof existing in vicinity of the surface of the wafer are eliminated from the wafer and are incorporated into the high concentration HF solution. The droplets formed by agglomerating the high concentration HF solution are aggregated at a predetermined position on the surface of the wafer. Then, the recovered droplet of the high concentration HF solution is dried. The aggregated material is irradiated with X-ray at an angle for promoting total reflection, and the total reflection X-ray fluorescence spectrometry is conducted to detect the emitted X-ray.Type: GrantFiled: March 3, 2005Date of Patent: March 25, 2008Assignee: NEC Electronics CorporationInventor: Yoshimi Shiramizu
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Patent number: 7332416Abstract: Methods to manufacture contaminant-gettering materials in the surface of EUV optics are described herein. An optical element is patterned and a contaminant-gettering material is formed on a surface of the optical element. In one embodiment, a photoresist is deposited on an optical coating on the optical element. Trenches are formed in the optical coating. The gettering agent is formed into the trenches over the photoresist. Next, the photoresist is removed from the optical coating to expose the gettering agent in the trenches. For another embodiment, patches of a nanotube forest having a gettering agent are formed in designated areas of an optical element. The gettering agent of the patches may be a plurality of carbon nanotubes. The optical coating is formed on a substrate between patches of the gettering agent.Type: GrantFiled: March 28, 2005Date of Patent: February 19, 2008Assignee: Intel CorporationInventors: Robert L. Bristol, Bruce H. Billett
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Publication number: 20080032491Abstract: An apparatus for removing one or more backside particles from a semiconductor substrate. The apparatus includes a substrate support member adapted to support the semiconductor substrate. The substrate has a substrate diameter, a substrate frontside, and a substrate backside. The apparatus also includes a curing ring having an annular shape and a curing ring support member adapted to position the curing ring at a predetermined distance from the backside of the semiconductor substrate, thereby defining a removal region. The apparatus further includes a phase change material dispense system adapted to provide a phase change material to the removal region and an ultraviolet source adapted to irradiate the phase change material.Type: ApplicationFiled: August 7, 2006Publication date: February 7, 2008Applicant: SOKUDO CO., LTD.Inventor: Harald Herchen
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Patent number: 7326604Abstract: In a semiconductor device using a crystalline semiconductor film on a substrate 106 having an insulating surface, impurities are locally implanted into an active region 102 to form a pinning region 104. The pinning region 104 suppresses the spread of a depletion layer from the drain side to effectively prevent the short channel effect. Also, since a channel forming region 105 is intrinsic or substantially intrinsic, a high mobility is realized.Type: GrantFiled: January 29, 2004Date of Patent: February 5, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hisashi Ohtani, Akiharu Miyanaga, Toru Mitsuki, Takeshi Fukunaga
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Patent number: 7316947Abstract: An object is to reduce the number of high temperature (equal to or greater than 600° C.) heat treatment process steps and achieve lower temperature (equal to or less than 600° C.) processes, and to simplify the process steps and increase throughput in a method of manufacturing a semiconductor device. With the present invention, a barrier layer, a second semiconductor film, and a third semiconductor film containing a noble (rare) gas element are formed on a first semiconductor film having a crystalline structure. Gettering is performed and a metallic element contained in the first semiconductor film passes through the barrier layer and the second semiconductor film by a heat treatment process, and moves to the third semiconductor film. The second semiconductor film and the third semiconductor film are then removed, with the barrier layer used as an etching stopper.Type: GrantFiled: February 12, 2002Date of Patent: January 8, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Osamu Nakamura, Masayuki Kajiwara, Junichi Koezuka, Koji Dairiki, Toru Mitsuki, Toru Takayama, Hideto Ohnuma, Taketomi Asami, Mitsuhiro Ichijo
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Publication number: 20080003782Abstract: In one embodiment, a multi-layer extrinsic gettering structure includes plurality of polycrystalline semiconductor layers each separated by a dielectric layer.Type: ApplicationFiled: July 3, 2006Publication date: January 3, 2008Inventors: David Lysacek, Michal Lorenc, Lukas Valek
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Patent number: 7309865Abstract: An electronic device according to the present invention includes: a cavity, which is surrounded with a cavity wall portion and which has a reduced pressure; a gettering thin film, which is arranged in the cavity and has the function of adsorbing a surrounding substance; and an activating portion, at least a part of which is arranged in the cavity and which has the function of activating the gettering thin film by generating heat.Type: GrantFiled: February 7, 2006Date of Patent: December 18, 2007Assignee: Matsushita Electric industrial Co., Ltd.Inventors: Kimiya Ikushima, Hiroyoshi Komobuchi, Asako Baba
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Patent number: 7306982Abstract: It is intended to achieve the reduction in number of heat treatments carried out at high temperature (at least 600° C.) and the employment of lower temperature processes (600° C. or lower), and to achieve step simplification and throughput improvement. In the present invention, a barrier layer (105), a second semiconductor film (106), and a third semiconductor layer (108) containing an impurity element (phosphorus) that imparts one conductive type are formed on a first semiconductor film (104) having a crystalline structure. Gettering is carried out in which the metal element contained in the first semiconductor film (104) is allowed to pass through the barrier layer (105) and the second semiconductor film (106) by a heat treatment to move into the third semiconductor film (107). Afterward, the second and third semiconductor films (106) and (107) are removed with the barrier layer (105) used as an etching stopper.Type: GrantFiled: September 15, 2004Date of Patent: December 11, 2007Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Osamu Nakamura, Masayuki Kajiwara, Junichi Koezuka, Koji Dairiki, Toru Mitsuki, Toru Takayama, Hideto Ohnuma, Taketomi Asami, Mitsuhiro Ichijo
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Patent number: 7294561Abstract: The present invention provides methods for forming SOI wafers having internal gettering layers for sequestering metallic impurities. More particularly, in one embodiment of the invention, a plurality of sites for sequestering metallic impurities are formed in a silicon substrate by implanting a selected dose of oxygen ions therein. In one embodiment, an epitaxial layer of crystalline silicon is formed over the substrate, and a buried continuous oxide layer is generated in the epitaxial layer, for example, by employing a SIMOX process.Type: GrantFiled: August 14, 2003Date of Patent: November 13, 2007Assignee: Ibis Technology CorporationInventors: Yuri Erokhin, Kevin J. Dempsey
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Patent number: 7291523Abstract: After crystallization of a semiconductor film is performed by irradiating first laser light (energy density of 400 to 500 mJ/cm2) in an atmosphere containing oxygen, an oxide film formed by irradiating the first laser light is removed. It is next performed to irradiate second laser light under an atmosphere that does not contain oxygen (at a higher energy density than that of the first laser light irradiation), thus to increase the flatness of the semiconductor film.Type: GrantFiled: January 3, 2006Date of Patent: November 6, 2007Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Setsuo Nakajima, Hidekazu Miyairi
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Patent number: 7250356Abstract: A method for forming a metal silicide region in a silicon region of a semiconductor substrate. The method comprises forming a metal layer over the silicon region, then in succession forming a titanium and a titanium nitride layer thereover. As the substrate is heated to form the silicide, the titanium getters silicon dioxide on the surface of the silicon region and the titanium nitride promotes the formation of a smooth surface at the interface between the silicide layer and the underlying silicon region.Type: GrantFiled: September 17, 2002Date of Patent: July 31, 2007Assignee: Agere Systems Inc.Inventors: Yuanning Chen, Maxwell Walthour Lippitt, III, William M. Moller
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Patent number: 7247561Abstract: A method of reducing the amount of halogenated materials in a halogen-containing environment. The method comprises introducing an aluminum compound into the halogen-containing environment, reacting the aluminum compound with the halogenated material to form a gaseous reaction product, and removing the gaseous reaction product from the environment. The aluminum compound may be a trialkylaluminum compound, an alane, an alkylaluminum hydride, an alkylaluminum halide, an alkylaluminum sesquihalide, or an aluminum sesquihalide. The aluminum compound may alternatively form a solid aluminum product, which is deposited on a surface associated with the halogen-containing environment or onto a semiconductor disposed therewithin. The halogenated material is incorporated into the solid aluminum product, forming an inert film within which the halogenated material is trapped.Type: GrantFiled: December 11, 2003Date of Patent: July 24, 2007Assignee: Micron Technology, Inc.Inventors: Demetrius Sarigiannis, Cem Basceri, Christopher W. Hill, Garo J. Derderian
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Patent number: 7235427Abstract: An embodiment of a multilayer wafer according to the invention includes a base substrate, a first layer associated with the base substrate, and a second layer on the first layer on side opposite from the base substrate in an axial direction and having a lateral edge. The first layer includes a ridge that protrudes axially and is disposed laterally adjacent the second layer measured in a direction normal to the axial direction for protecting the lateral edge. This ridge can surround portion the lateral edge in an axial cross-section for preventing edge falls. Also, the ridge can have an axial height greater than the axial thickness of the second layer. In one embodiment, the second layer includes an oxydizable semiconductor and the first layer includes an oxidized insulator.Type: GrantFiled: February 24, 2005Date of Patent: June 26, 2007Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Thierry Barge, Bruno Ghyselen, Toshiaki Iwamatsu, Hideki Naruoka, Junichiro Furihata, Kiyoshi Mitani
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Patent number: 7232742Abstract: In a method of crystallizing a semiconductor film by introducing a metallic element that promotes crystallization, a gettering thereafter is effectively performed. A material film having a high tensile stress, typically a silicon nitride film, is formed in contact with the semiconductor film or heated after the formation thereof, thereby the metallic element in a crystalline semiconductor film is gettered to the material film having a high tensile stress. Thus, the metallic Interstitial silicon density element is removed or reduced to thereby form a gettered region.Type: GrantFiled: November 27, 2000Date of Patent: June 19, 2007Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shinji Maekawa
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Patent number: 7208380Abstract: The present invention provides, in one aspect, a method of fabricating a gate oxide layer on a microelectronics substrate. This embodiment comprises forming a stress inducing pattern on a backside of a microelectronics wafer and growing a gate oxide layer on a front side of the microelectronics wafer in the presence of a tensile stress caused by the stress inducing pattern.Type: GrantFiled: March 18, 2005Date of Patent: April 24, 2007Assignee: Texas Instruments IncorporatedInventors: Anand T. Krishnan, Srinivasan Chakravarthi, Haowen Bu
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Patent number: 7199027Abstract: There is provided a technique for effectively removing a metallic element for promoting crystallization in a semiconductor film with a crystalline structure after the semiconductor film is obtained using the metallic element, to reduce a variation between elements. In a step of forming a gettering site, a plasma CVD method is used and a film formation is conducted using raw gas including monosilane, noble gas, and nitrogen to obtain a semiconductor film which includes the noble gas element at a high concentration, specifically, a concentration of 1×1020/cm3 to 1×1021/cm3 and has an amorphous structure, typically, an amorphous silicon film.Type: GrantFiled: July 9, 2002Date of Patent: April 3, 2007Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Mitsuhiro Ichijo, Taketomi Asami, Noriyoshi Suzuki, Shunpei Yamazaki
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Patent number: 7199057Abstract: A method by which a silicon wafer is prevented from increasing boron concentration near the surface and difference in the boron concentration does not arise between the surface of the annealed wafer and the silicon bulk to eliminate boron contamination in the silicon wafer caused by an annealing treatment is provided. The method includes, when annealing a silicon wafer having a surface on which a native oxide film has formed and boron of environmental origin or from chemical treatment prior to annealing has deposited, steps of carrying out temperature heat-up in a mixed gas atmosphere having a mixing ratio of hydrogen gas to inert gas of 5% to 100% so as to remove the boron-containing native oxide film, followed by annealing in an inert gas atmosphere.Type: GrantFiled: August 28, 2003Date of Patent: April 3, 2007Assignee: Sumco CorporationInventors: So Ik Bae, Yoshinobu Nakada, Kenichi Kaneko
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Patent number: 7084048Abstract: A process for removing a contaminant selected from among copper, nickel, and a combination thereof from a silicon wafer having a surface and an interior. The process comprises cooling the silicon wafer in a controlled atmosphere from a temperature at or above an oxidation initiation temperature and initiating a flow of an oxygen-containing atmosphere at said oxidation initiation temperature to create an oxidizing ambient around the silicon wafer surface to form an oxide layer on the silicon wafer surface and a strain layer at an interface between the oxide layer and the silicon wafer interior. The cooling of the wafer is also controlled to permit diffusion of atoms of the contaminant from the silicon wafer interior to the strain layer. Then the silicon wafer is then cleaned to remove the oxide layer and the strain layer, thereby removing said contaminant having diffused to the strain layer.Type: GrantFiled: May 7, 2004Date of Patent: August 1, 2006Assignee: MEMC Electronic Materials, Inc.Inventors: Larry W. Shive, Brian L. Gilmore
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Patent number: 7075002Abstract: A method of manufacturing a thin-film solar cell, comprising the steps of: forming an amorphous silicon film on a substrate; placing a metal element that accelerates the crystallization of silicon in contact with the surface of the amorphous silicon film; subjecting the amorphous silicon film to a heat treatment to obtain a crystalline silicon film; depositing a silicon film to which phosphorus has been added in contact with the crystalline silicon film; and subjecting the crystalline silicon film and the silicon film to which phosphorus has been added to a heat treatment to getter the metal element from the crystalline film.Type: GrantFiled: August 6, 1997Date of Patent: July 11, 2006Assignee: Semiconductor Energy Laboratory Company, Ltd.Inventors: Shunpei Yamazaki, Yasuyuki Arai
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Patent number: 7052943Abstract: A technique of using a metal element that has a catalytic action over crystallization of a semiconductor film to obtain a crystalline semiconductor film and then effectively removing the metal element remaining in the film is provided. A first semiconductor film (104) having a crystal structure is formed on a substrate. A barrier layer (105) and a second semiconductor film (106) containing a rare gas element are formed on the first semiconductor film (104). A metal element contained in the first semiconductor film (104) is moved to the second semiconductor film (106) through the barrier layer (105) by heat treatment for gettering.Type: GrantFiled: March 15, 2002Date of Patent: May 30, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideto Ohnuma, Koji Dairiki, Toru Mitsuki, Toru Takayama, Kengo Akimoto
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Patent number: 7045442Abstract: The present invention is a separation method for easy separation of an allover release layer with a large area. Further, the present invention is the separating method that is not subjected to restrictions in the use of substrates, such as a kind of substrate, during forming a release layer. A separation method comprising the steps of forming a metal film, a first oxide, and a semiconductor film containing hydrogen in this order; and bonding a support to a release layer containing the first oxide and the semiconductor film and separating the release layer bonded to the support from a substrate provided with the metal layer by a physical means.Type: GrantFiled: December 22, 2003Date of Patent: May 16, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Junya Maruyama, Yumiko Ohno, Toru Takayama, Yuugo Goto, Shunpei Yamazaki
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Patent number: 7037808Abstract: The invention includes a semiconductor construction. The construction has a semiconductor material die with a front surface, a back surface in opposing relation to the front surface, and a thickness of less than 400 microns between the front and back surfaces. The construction also has circuitry associated with the die and over the front surface of the die, and a layer touching the back surface of the die. The layer can correspond to getter-inducing material and/or to a stress-inducing material. The layer can have a composition which includes silicon dioxide and/or silicon nitride. The composition can include one or more hydrogen isotopes, and the hydrogen isotopes can have a higher abundance of deuterium than the natural abundance of deuterium.Type: GrantFiled: August 3, 2005Date of Patent: May 2, 2006Assignee: Micron Technology, Inc.Inventors: Tongbi Jiang, Zhiping Yin
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Patent number: 7026197Abstract: There is disclosed a method of fabricating TFTs using a silicon film crystallized with the aid of nickel. The nickel is removed from the crystallized silicon film. The method starts with maintaining nickel in contact with the surface of an amorphous silicon film. Then, a heat treatment is performed to form a crystalline silicon film. At this time, nickel promotes the crystallization greatly, and nickel diffuses into the film. A mask is formed. A silicon film heavily doped with phosphorus is formed. Thereafter, a heat treatment is performed to move the nickel from the crystalline silicon film into the phosphorus-rich silicon film. This reduces the concentration of nickel in the crystalline silicon film.Type: GrantFiled: November 14, 2003Date of Patent: April 11, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Setsuo Nakajima, Hisashi Ohtani
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Patent number: 7022589Abstract: The invention provides a method for activating impurity element added to a semiconductor and performing gettering process in shirt time, and a thermal treatment equipment enabling to perform such the heat-treating.Type: GrantFiled: November 12, 2003Date of Patent: April 4, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki