Abstract: After crystallization of a semiconductor film is performed by irradiating first laser light (energy density of 400 to 500 mJ/cm2) in an atmosphere containing oxygen, an oxide film formed by irradiating the first laser light is removed. It is next performed to irradiate second laser light under an atmosphere that does not contain oxygen (at a higher energy density than that of the first laser light irradiation), thus to increase the flatness of the semiconductor film.

Abstract: A method for forming a strained silicon layer device with improved wafer throughput and low defect density including providing a silicon substrate; epitaxially growing a first silicon layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; epitaxially growing a step-grade SiGe buffer layer over and contacting the first silicon layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; epitaxially growing a SiGe capping layer over and contacting the step-grade SiGe buffer layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; and, epitaxially growing a second silicon layer using at least one deposition precursor selected from the group consisting of disilane and silane.

Abstract: A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing.

Abstract: The present invention provides a silicon wafer having a DZ layer near a surface and an oxide precipitate layer in a bulk portion, wherein interstitial oxygen concentrations of the DZ layer, the oxide precipitate layer and a transition region between the DZ layer and the oxide precipitate layer are all 8 ppma or less, and an epitaxial silicon wafer, wherein an epitaxial layer is formed on a surface of the silicon wafer, as well as a method for producing a silicon wafer, which comprises growing a silicon single crystal ingot having an initial interstitial oxygen concentration of 10 to 25 ppma by the Czochralski method, processing the silicon single crystal ingot into a wafer, and subjecting the wafer to a first heat treatment at 950 to 1050° C. for 2 to 5 hours, a second heat treatment at 450 to 550° C. for 4 to 10 hours, a third heat treatment at 750 to 850° C. for 2 to 8 hours, and a fourth heat treatment at 950 to 1100° C. for 8 to 24 hours.

Abstract: After crystallization of a semiconductor film is performed by irradiating first laser light (energy density of 400 to 500 mJ/cm2) in an atmosphere containing oxygen, an oxide film formed by irradiating the first laser light is removed. It is next performed to irradiate second laser light under an atmosphere that does not contain oxygen (at a higher energy density than that of the first laser light irradiation), thus to increase the flatness of the semiconductor film.

Abstract: A method is provided for gettering impurities from silicon wafers and devices to improve the quality of the material and the device performance. The wafer or the device is coated on the back-side with a layer of aluminum and is illuminated form the other side with light having a significant portion of energy in the IR region. This process leads to formation of a Si—Al melt on the backside, at temperature below 550° C. Dissolved impurities in the Si diffuse toward the Al melt and are trapped there. At higher illuminations and concomitant higher temperatures, the Al interface serves as a source of point defect injection. This mode of processing causes dissolution of precipitated impurities at greatly reduced temperatures and in short periods of time.

Abstract: A gettering layer for capturing heavy metal impurities is formed on a wafer back surface. Immediately before formation of a metal wiring layer, a semiconductor device is subjected to first heat treatment at a predetermined temperature so that the heavy metal impurities are heat-diffused and captured in the gettering layer. The gettering layer with the heavy metal impurities captured therein is removed before second heat treatment following the first heat treatment. After removing the gettering layer, a first amorphous silicon layer as a filler for filling a contact hole is deposited on a wafer device surface including a device active region while a second amorphous silicon layer having an impurity concentration equal to that of the first amorphous silicon layer is simultaneously deposited on the wafer back surface.

Abstract: An indium-containing wafer from which removal of mercury can be reliably performed and a method of manufacturing such a wafer are provided in order to make the mercury C-V method, allowing characteristics of a the indium-containing wafer to be measured with high precision and being a non-destructive test, viable.

Abstract: A process for heat-treating a single crystal silicon segment to influence the profile of minority carrier recombination centers in the segment. The segment has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the segment is subjected to a heat-treatment to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon. The segment is then cooled from the temperature of said heat treatment at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a segment having a vacancy concentration profile in which the peak density is at or near the central plane with the concentration generally decreasing in the direction of the front surface of the segment. Platinum atoms are then in-diffused into the silicon matrix such that the resulting platinum concentration profile is substantially related to the concentration profile of the crystal lattice vacancies.

Abstract: One aspect of this disclosure relates to a method for creating proximity gettering sites in a silicon on insulator (SOI) wafer. In various embodiments of this method, a relaxed silicon germanium region is formed over an insulator region of the SOI to be proximate to a device region. The relaxed silicon germanium region generates defects to getter impurities from the device region. Other aspects are provided herein.

Abstract: The invention relates to a method for generating defect profiles in a crystal or crystalline structure of a substrate, preferably a semiconductor, during a thermal treatment in a process chamber. According to the inventive method, a concentration and/or a density distribution of defects is controlled with at least one reactive component each depending on at least two process gases that differ in their composition. At least two of the process gases independently act upon at least two different surfaces of the substrate.

Abstract: A method for treating a semiconductor processing component, including: exposing the component to a halogen gas at an elevated temperature, oxidizing the component to form an oxide layer, and removing the oxide layer

Abstract: In a conventional evaluation method of IG effectivity on Cu in semiconductor silicon substrates, it is required to actually conduct the device process, or a great deal of time, manpower and expenses for manufacturing a MOS device for dielectric breakdown estimation and the like are needed, but in the present invention, the problem was solved by experimentally finding in advance the optimum ranges of the diagonal length and density of oxygen precipitates which make the IG effectivity on Cu favorable, and conducting a heat treatment for the addition of IG effectivity based on a simulation by calculations using Fokker-Planck equations so that the diagonal length and density of plate-like precipitates fall within the optimum ranges.

Abstract: The invention includes methods of forming metal-containing layers. The layers can, in particular aspects, consist essentially of metal, or consist of metal. The desired layers can be formed by initially depositing a metal-containing layer which comprises metal and halogen atoms. Subsequently, trialkylaluminum is utilized to remove the halogen atoms from the layer. The layer remaining after removal of the halogen atoms can comprise, consist essentially, or consist of any suitable metal, and in particular aspects can consist essentially of, or consist of, titanium or titanium/aluminum.

Abstract: The method for fabricating a semiconductor device including a step of forming a gate insulation film on a semiconductor substrate 10, the method further comprises, before the step of forming the gate insulation film, the step of forming an insulation film 12, covering a first side (upper side) and a second side (underside) of the semiconductor substrate 10, the step of etching off the insulation film 12 on the first side of the semiconductor substrate 10, and the step of annealing the semiconductor substrate 10 with the insulation film 12 present on the second side of the semiconductor substrate 10.

Abstract: Charge-up damages to a substrate are reduced in a manufacturing process using plasma, and the reliability of a semiconductor device is improved. By forming an insulating film on the back of a substrate before a step of forming a first wiring layer, even if a plasma CVD method, a sputtering method, or a dry-etching method is used in a wiring-forming step executed later, then it is possible to suppress electric charges which are generated on the substrate and which flow to the ground potential through the substrate, and to prevent damages to the substrate due to charge-up.

Abstract: A catalyst element remaining in a first semiconductor film subjected to a first heat treatment (crystallization) is moved and concentrated/collected by subjecting a second semiconductor film which is formed on the first semiconductor film and contains a rare gas element to a second heat treatment. That is, the rare gas element is incorporated into the second semiconductor film to generate a strain field as a gettering site.

Abstract: The invention relates to a process for the treatment of substrates (1) for microelectronics or optoelectronics comprising a working layer (6) at least partially composed of an oxidizable material on at least one of their faces, this process comprising:

Abstract: White defects caused by a dark-current of a solid-state imaging device is reduced by effectively bringing out gettering capability of a buried getter sink layer. A buried getter sink layer is formed by introducing to the semiconductor substrate a substance of a second element which is a congener of a first element composing a semiconductor substrate, a crystal growth layer is formed by crystal growing a substance of the first element on a surface of the semiconductor substrate, and a solid-state imaging element is formed inside and on the crystal growth layer at a lower temperature than that in the case of forming an extrinsic getter sink layer by introducing a substance of a third element of a different group from the first element on a back surface of the semiconductor substrate.

Abstract: A partially-depleted Silicon-on-Insulator (SOI) substrate with minimal charge build up and suppressed floating body effect is disclosed, as well as a simple method for its fabrication. A thin Si/Ge epitaxial layer is grown between two adjacent epitaxial silicon layers of a SOI substrate, and as part of the silicon epitaxial growth. The thin Si/Ge epitaxial layer introduces misfit dislocations at the interface between the thin Si/Ge epitaxial layer and the adjacent epitaxial silicon layers, which removes undesired charge build up within the substrate.

Abstract: A semiconductor film having a crystalline structure is formed by using a metal element that assists the crystallization of the semiconductor film, and the metal element remaining in the film is effectively removed to decrease the dispersion among the elements. The semiconductor film or, typically, an amorphous silicon film having an amorphous structure is obtained based on the plasma CVD method as a step of forming a gettering site, by using a monosilane, a rare gas element and hydrogen as starting gases, the film containing the rare gas element at a high concentration or, concretely, at a concentration of 1×1020/cm3 to 1×1021/cm3 and containing fluorine at a concentration of 1×1015/cm3 to 1×1017/cm3.

Abstract: When a gettering sink is removed by using alkaline solution of etchant having a high selectivity to the gettering sink and a barrier film functioning as an etching stopper, residue of gettering is left. However, according to the present invention, a semiconductor film that serves as a gettering sink contains nitrogen concentration is 1×1018 atoms/cm3 or lower, oxygen concentration is 8×1019 atoms/cm3 or lower, and noble gas concentration is 1×1020 atoms/cm3 or higher. In order to achieve the above-described impurity concentrations, a concentration of oxygen that is an impurity element in a chamber is reduced by using a flammable gas for heating and exhausting oxygen.

Abstract: A technique for forming a gettering layer in a wafer made using a controlled cleaving process. The gettering layer can be made by implanting using beam line or plasma immersion ion implantaion, or made by forming a film of material such as polysilicon by way of chemical vapor deposition. A controlled cleaving process is used to form the wafer, which is a multilayered silicon on insulator substrate. The gettering layer removes and/or attracts impurities in the wafer, which can be detrimental to the functionality and reliability of an integrated circuit device made on the wafer.

Abstract: A method for fabricating an insulator on a semiconductor substrate such that the insulator has a low dielectric constant. A first interconnect and a second interconnect are configured on a semiconductor substrate. A conductive silicon is formed between the first interconnect and the second interconnect. The conductive silicon is anodically etched in a hydrofluoric-acid-containing electrolyte to convert the conductive silicon into porous silicon. The porous silicon is subsequently oxidized to form porous silicon oxide. With a dielectric constant of between 1.1 and 4, the porous silicon oxide has a lower dielectric constant than customary silicon oxide with 4.

Abstract: A method for forming a metal suicide region in a silicon region of a semiconductor substrate. The method comprises forming a metal layer over the silicon region, then in succession forming a titanium and a titanium nitride layer thereover. As the substrate is heated to form the silicide, the titanium getters silicon dioxide on the surface of the silicon region and the titanium nitride promotes the formation of a smooth surface at the interface between the suicide layer and the underlying silicon region.

Abstract: The specification teaches a device for use in the manufacturing of microelectronic, microoptoelectronic or micromechanical devices (microdevices) in which a contaminant absorption layer improves the life and operation of the microdevice. In a preferred embodiment the invention includes a mechanical supporting base, and a layer of a gas absorbing or purifier material is deposited on the base by a variety of techniques and a layer for temporary protection of the purification material is placed on top of the purification material. The temporary protection material is compatible for use in the microdevice and can be removed during the manufacture of the microdevice.

Abstract: In a method for manufacturing a solid state image pick up device capable of improving gettering efficiency a semiconductor substrate having a front side on which a solid state image pick-up device may be formed, and a rear side opposite to the front side is provided. Subsequently, a polysilicon layer including impurities for gettering having a predetermined concentration is formed on the rear side of the semiconductor substrate. Next, a predetermined thickness of the polysilicon layer including the impurities for gettering is oxidized, and the impurities for gettering are condensed into the reduced polysilicon layer.

Abstract: Ultra-low leakage current backside-illuminated semiconductor photodiode arrays are fabricated using a method of formation of a transparent, conducting bias electrode layer that avoids high-temperature processing of the substrate after the wafer has been gettered. As a consequence, the component of the reverse-bias leakage current associated with strain, crystallographic defects or impurities introduced during elevated temperature processing subsequent to gettering can be kept extremely low. An optically transparent, conductive bias electrode layer, serving as both an optical window and an ohmic backside equipotential contact surface for the photodiodes, is fabricated by etching through the polysilicon gettering layer and a portion of the thickness of heavily-doped crystalline silicon layer formed within, and near the back of, the substrate during the gettering process.

Abstract: A technique, where a semiconductor film having a crystal structure is obtained using a metal element that helps crystallization of the semiconductor film, then that metal element remained in the film is effectively removed, as a result variation among elements is reduced, is provided. In a process for forming a gettering site, a semiconductor film containing a rare-gas element is formed, then an anti-diffusion film for preventing diffusion of the rare-gas element is formed, thereby the metal element in another semiconductor film is effectively removed, particularly in a gettering that is a heating treatment at a high temperature of 600° C. or more.

Abstract: One aspect of the invention relates to a method of removing contaminants from a low-k film. The method involves forming a sacrificial layer over the contaminated film. The contaminants combine with the sacrificial layer and are removed by etching away the sacrificial layer. An effective material for the sacrificial layer is, for example, a silicon carbide. The method can be used to prevent the occurrence of pattern defects in chemically amplified photoresists formed over low-k films.

Abstract: A method for non-destructively evaluating the concentration of impurities in an epitaxial susceptor used in the processing of a semiconductor substrate. The method includes processing a semiconductor substrate of known impurity levels on the epitaxial susceptor, and measuring the impurity levels after epitaxial processing by drawing together at least a portion of the impurities and measuring the concentration of impurities that were drawn together. In one embodiment of the invention, a gettering layer is formed adjacent one or more surfaces of the substrate to getter impurities from the substrate into the gettering layer. The impurity concentration of the gettering layer is then measured and the results are used to determine at least a range of impurity concentrations that were transferred to the substrate from the epitaxial susceptor.

Abstract: A method for evaluating the concentration of impurities in gases used in depositing an epitaxial layer on a semiconductor substrate. The method includes processing a semiconductor substrate of known impurity levels in an epitaxial reactor, and measuring the impurity levels after epitaxial processing by drawing together at least a portion of the impurities and measuring the concentration of impurities that were drawn together. In one embodiment of the invention, a gettering layer is formed adjacent one or more surfaces of the substrate to getter impurities from the substrate into the gettering layer. The impurity concentration of the gettering layer is then measured and the results are used to determine at least a range of impurity concentrations that were transferred to the substrate from the epitaxial susceptor.

Abstract: A method for evaluating the concentration of impurities in as-grown monocrystalline semiconductor ingots is provided. The method includes growing a monocrystalline semiconductor ingot, and measuring the bulk impurity levels of the ingot by drawing together at least a portion of the impurities and measuring the concentration of impurities that were drawn together. In one embodiment of the invention, a gettering layer is formed adjacent one or more surfaces of a sample of the monocrystalline semiconductor ingot to getter impurities from the sample into the gettering layer. The impurity concentration of the gettering layer is then measured and the results are used to determine at least a range of impurity concentrations that were grown into the monocrystalline semiconductor ingot.

Abstract: A semiconductor device comprising organic semiconductor material (14) has one or more barrier layers (16) disposed at least partially thereabout to protect the organic semiconductor material (14) from environment-driven changes that typically lead to inoperability of a corresponding device. If desired, the barrier layer can be comprised of partially permeable material that allows some substances therethrough to thereby effect disabling of the encapsulated organic semiconductor device after a substantially predetermined period of time. Getterers (141) may also be used to protect, at least for a period of time, such organic semiconductor material.

Abstract: Catalytic elements such as Ni are intentionally combined with defects that remain inside of a semiconductor substrate or thin film so that the energy state of the defects comes to a stable state. In this state, a heat treatment is conducted in an atmosphere containing halogen element or XV element, and gettering is conducted in such a manner that the catalytic element is taken in an oxide film. The bonds which are divided by separating the catalytic element are recombined through a heat treatment, thereby being capable of improving crystalline property of the semiconductor substrate or thin film remarkably.

Abstract: A method for evaluating the concentration of impurities in a semiconductor substrate. The method includes drawing together at least a portion of the impurities and measuring the concentration of impurities that were drawn together. In one embodiment of the invention, a gettering layer is formed adjacent one or more surfaces of the substrate to getter impurities from the substrate to the gettering layer. The impurity concentration of the gettering layer is then measured and the results are used to determine at least a range of impurity concentrations that were in the substrate prior to the drawing together.

Abstract: By removing halogen atoms existing on the surface of the silicon layer and in the subsurface thereof so that the concentration of halogen atoms becomes 100 ppm or lower and forming an electrode on the resulting silicon layer, the electrode which has a low resistance can be produced, and a highly reliable semiconductor device can be produces as well.

Abstract: The invention describes a method for gettering silicon on insulator wafers without forming regions of heavy doping. Silicon germanium layers (201, 304) are formed beneath silicon layers (200, 305) such that dislocations will form in the silicon germanium layers. These dislocations will serve to getter impurities.

Abstract: A method for evaluating the concentration of impurities in a semiconductor substrate. The method includes drawing together at least a portion of the impurities and measuring the concentration of impurities that were drawn together. In one embodiment of the invention, a gettering layer is formed adjacent one or more surfaces of the substrate to getter impurities from the substrate to the gettering layer. The impurity concentration of the gettering layer is then measured and the results are used to determine at least a range of impurity concentrations that were in the substrate prior to the drawing together.

Abstract: The invention relates to improvements in a process and annealing device for cleaving a wafer layer along a weakened zone in a donor wafer using a thermal anneal. In one improvement, at least one donor wafer is provided in a substantially horizontal position during the thermal anneal to prepare a wafer layer which, after detachment, has a cleaved surface with reduced surface roughness irregularities. The donor wafer can be preferably placed inside a chamber between two heating electrodes during the thermal anneal. The thermal anneal can be conducted to detach the wafer layer or the donor wafer to mechanical action to detach the wafer layer after the thermal anneal is conducted. Either way, a cleaved surface is provided on the detached wafer layer that does not include isolated dense areas adjacent the wafer layer periphery.

Abstract: An electronic device that is sealed under vacuum includes a substrate, a transistor formed on the substrate, and a dielectric layer covering at least a portion of the transistor. The electronic device further includes a layer of non-evaporable getter material disposed on a portion of the dielectric layer; and a vacuum device disposed on a portion of the substrate. Electrical power pulses activate the non-evaporable getter material.

Abstract: A gettering unit encompasses a silicon substrate, a thin film heater disposed on the silicon substrate, and a gettering layer disposed selectively on the thin film heater. Here, the thin film heater is made of metallic film such as platinum (Pt) or chromium (Cr) film. The area of the gettering layer is smaller than the area for the thin film heater so as to expose first and second end terminals of the thin film heater. The first and second end terminals of the thin film heater serves as the bonding pads in the assembling process.

Abstract: The present invention teaches a sawn wafer with ultra clean bonding pads on die which enhance the strength of wire bond and results in higher yield and improved reliability of packaged semiconductor die. Clean wafers ready for dicing are coated with a removable insulating water soluble non-ionic film which enhances clean saw cuts and reduces buildup. The protective film is hardened by heat and resists removal by cooling water used in dicing saws. However, after dicing the protective film is removable in a wafer washer using high pressure warm D.I. water. After removal of the protective film the electrode pads are virtually as clean as before dicing. The film may be used as a protective layer until the sawn wafer is ready for use.

Abstract: A semiconductor wafer manufacturing process is disclosed wherein a double side polished wafer having oxygen induced stacking faults to provide extrinsic gettering on the back surface of the wafer. The process includes polishing the back surface of the wafer, and depositing a thin polysilicon film on the polished back surface. The wafer is then subjected to a thermal oxidation step, wherein the polysilicon film is consumed by the thermal oxidation step. The oxide layer is then stripped from the back surface, leaving oxygen induced stacking faults on the back surface of the wafer. The front surface of the wafer is then polished, thereby producing a double side polished wafer containing extrinsic gettering sites on the polished back surface.

Abstract: A novel contact structure and method for a multilayer gettering contact metallization is provided utilizing a thin layer of a pure metal as the initial layer formed on a semiconductor cap layer. During formation of the contact structure, this thin metal layer reacts with the cap layer and the resulting reacted layer traps mobile impurities and self-interstitials diffusing within the cap layer and in nearby metal layers, preventing further migration into active areas of the semiconductor device. The contact metallization is formed of pure metal layers compatible with each other and with the underlying semiconductor cap layer such that depth of reaction is minimized and controllable by the thickness of the metal layers applied. Thin semiconductor cap layers, such as InGaAs cap layers less than 200 nm thick, may be used in the present invention with extremely thin pure metal layers of thickness 10 nm or less, thus enabling an increased level of integration for semiconductor optoelectronic devices.

Abstract: Disclosed is a simplified technique of introducing a metal element capable of promoting the crystallization of silicon into an amorphous silicon film to be crystallized, and of removing the metal element from the film. An amorphous silicon film 102 is formed on a substrate, a mask 103 is formed thereon, and a nickel-containing PSG film is further formed thereover. This is heated at 560° C. to thereby make nickel diffused in the direction 106, and the film is crystallized. Next, this is further heated at 850° C. to thereby make phosphorus diffused into the region 107, in which nickel is gettered by the thus-diffused phosphorus. Thus, the crystallization of silicon is promoted by the metal element nickel, and the nickel is then removed from the crystallized silicon film.

Abstract: There is provided a process for manufacturing a silicon epitaxial wafer capable of manufacturing an epitaxial wafer, which exerts a stable IG capability without being affected by a thermal history of a substrate for epitaxial growth and has the IG capability excellent from an early stage of a device process, and particularly, canceling an IG shortage in an N/N+ epitaxial wafer caused by a problem that oxygen precipitation is hard to proceed in an N+ substrate with a simple and easy way. RTA (rapid heating and rapid cooling heat treatment) is performed at a temperature of 1200° C. to 1350° C. for 1 to 120 seconds on a silicon substrate for epitaxial growth; further heat treatment is performed at a temperature of 900° C. to 1050° C. for 2 to 20 hours on the silicon substrate for epitaxial growth; and thereafter, an epitaxial layer is formed on a surface of the silicon substrate.

Abstract: A method for processing a monocrystalline Si-semiconductor wafer includes a tempering step at a temperature of over 550° C. A protective layer for protecting against the penetration of metal and/or rare earth metal substances into the Si-semiconductor wafer during the tempering step is applied to the back of the Si-semiconductor wafer before the tempering step.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer (24) on a silicon wafer (22). The accommodating buffer layer (24) is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide (28). The amorphous interface layer (28) dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Light-assisted deposition techniques are used to form the accommodating buffer layer (24).

Abstract: A gettering layer for capturing heavy metal impurities is formed on a wafer back surface. Immediately before formation of a metal wiring layer, a semiconductor device is subjected to first heat treatment at a predetermined temperature so that the heavy metal impurities are heat-diffused and captured in the gettering layer. The gettering layer with the heavy metal impurities captured therein is removed before second heat treatment following the first heat treatment. After removing the gettering layer, a first amorphous silicon layer as a filler for filling a contact hole is deposited on a wafer device surface including a device active region while a second amorphous silicon layer having an impurity concentration equal to that of the first amorphous silicon layer is simultaneously deposited on the wafer back surface.