Compound Semiconductor Patents (Class 438/483)
  • Patent number: 10516076
    Abstract: A dislocation filter for a semiconductor device has a buffer layer comprising a short-period superlattice (SPSL) layer. The SPSL layer has first sub-layers of a first material that alternate with second sub-layers of a second material, the first material and the second material being group III-N binary materials that are different from each other. Each of the first sub-layers and each of the second sub-layers has a sub-layer thickness less than or equal to 12 monolayers. The buffer layer also includes a third layer of a third material, the third material being a group III-N material. The SPSL forms a sandwich structure with the third layer. The buffer layer bends dislocations away from a growth direction of the buffer layer.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: December 24, 2019
    Assignee: Silanna UV Technologies Pte Ltd
    Inventors: Liam Anderson, William Lee, William Schaff, Johnny Cai Tang
  • Patent number: 10483141
    Abstract: A substrate transport system is disclosed and includes a chamber having an interior wall, a planar motor disposed on the interior wall, and a substrate carrier magnetically coupled to the planar motor. The substrate carrier comprises a base and a substrate supporting surface coupled to a support member extending from the base in a cantilevered orientation.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: November 19, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Karthik Janakiraman, Hari K. Ponnekanti, Juan Carlos Rocha-Alvarez
  • Patent number: 10461155
    Abstract: A semiconductor structure including a source/drain region is disclosed. The source/drain region may include a first epitaxial region along at least one sidewall of the source/drain region having a substantially uniform sidewall thickness. The semiconductor structure may further include a gate structure adjacent and above the source/drain region wherein at least a portion of the first epitaxial region is positioned below a sidewall spacer of the gate structure. A method of forming a source/drain region including a first epitaxial region having a substantially uniform sidewall thickness is disclosed. The method may include forming a trench in a substrate adjacent to a gate structure, forming the first epitaxial region in the trench, forming a spacer material layer on the gate structure and on a portion of the first epitaxial region, and removing a portion of the first epitaxial region using the spacer material layer as a mask.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: October 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yoong Hooi Yong, Yanping Shen, Hsien-Ching Lo, Xusheng Wu, Joo Tat Ong, Wei Hong, Yi Qi, Dongil Choi, Yongjun Shi, Alina Vinslava, James Psillas, Hui Zang
  • Patent number: 10438796
    Abstract: Native oxides and residue are removed from surfaces of a substrate by performing a multiple-stage native oxide cleaning process. In one example, the method for removing native oxides from a substrate includes supplying a first gas mixture including an inert gas onto a surface of a material layer disposed on a substrate into a first processing chamber, wherein the material layer is a III-V group containing layer for a first period of time, supplying a second gas mixture including an inert gas and a hydrogen containing gas onto the surface of the material layer for a second period of time, and supplying a third gas mixture including a hydrogen containing gas to the surface of the material layer while maintaining the substrate at a temperature less than 550 degrees Celsius.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: October 8, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chun Yan, Xinyu Bao
  • Patent number: 10355115
    Abstract: The present invention discloses an electronic device formed of a group III nitride. In one embodiment, a substrate is fabricated by the ammonothermal method and a drift layer is fabricated by hydride vapor phase epitaxy. After etching a trench, p-type contact pads are made by pulsed laser deposition followed by n-type contact pads by pulsed laser deposition. The bandgap of the p-type contact pad is designed larger than that of the drift layer. Upon forward bias between p-type contact pads (gate) and n-type contact pads (source), holes and electrons are injected into the drift layer from the p-type contact pads and n-type contact pads. Injected electrons drift to the backside of the substrate (drain).
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: July 16, 2019
    Assignee: SixPoint Materials, Inc.
    Inventors: Tadao Hashimoto, Daisuke Ueda
  • Patent number: 10276688
    Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: April 30, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xinyu Bao, Zhiyuan Ye, Flora Fong-Song Chang, Abhishek Dube, Xuebin Li, Errol Antonio C. Sanchez, Hua Chung, Schubert S. Chu
  • Patent number: 10256322
    Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: April 9, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xinyu Bao, Zhiyuan Ye, Hua Chung
  • Patent number: 10014399
    Abstract: This hetero-junction bipolar transistor includes a first n-type GaN layer, an AlxGa1-xN layer (0.1?x?0.5), an undoped GaN layer having a thickness of not less than 20 nm, a Mg-doped p-type GaN layer having a thickness of not less than 100 nm, and a second n-type GaN layer which are sequentially stacked. The first n-type GaN layer and the AlxGa1-xN layer form an emitter, the undoped GaN layer and the p-type GaN layer form a base, and the second n-type GaN layer forms a collector. During non-operation, two-dimensional hole gas is formed in a part of the undoped GaN layer near the hetero interface between the AlxGa1-xN layer and the undoped GaN layer. When the thickness of the p-type GaN layer is b [nm], the hole concentration of the p-type GaN layer is p [cm?3], and the concentration of the two-dimensional hole gas is Ps [cm?2], p×b×10?7+Ps?1×1013 [cm?2] is satisfied.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: July 3, 2018
    Assignee: Powdec K.K.
    Inventor: Hiroji Kawai
  • Patent number: 9985162
    Abstract: A solar cell includes a substrate containing a first impurity of a first conductivity type and made of a crystalline semiconductor, an emitter region positioned on the substrate and containing a second impurity of a second conductivity type different from the first conductivity type, the emitter region being made of a non-crystalline semiconductor, a surface field region positioned on the substrate and containing a third impurity of the first conductivity type, the surface field region being made of non-crystalline semiconductor, a first electrode connected to the emitter region, and a second electrode connected to the surface field region, wherein at least one of the emitter region and the surface field region is made of amorphous metal silicide containing a metal material.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: May 29, 2018
    Assignee: LG ELECTRONICS INC.
    Inventors: Wonseok Choi, Heonmin Lee, Junghoon Choi
  • Patent number: 9926647
    Abstract: Provided are: a method for producing a ?-Ga2O3 substrate of which changes in donor concentration in a reducing atmosphere or an inert gas atmosphere are suppressed; and a method for producing a crystal laminate structure that can epitaxially grow a high-quality crystal film having low variability of quality in a reducing atmosphere or an inert gas atmosphere. The method for producing a ?-Ga2O3 substrate includes a step for cutting out a ?-Ga2O3 substrate from a ?-Ga2O3 crystal containing a group IV element; annealing processing in an atmosphere containing a reducing atmosphere and/or an inert gas atmosphere is performed on the ?-Ga2O3 crystal before cutting out the ?-Ga2O3 substrate, or on the cut-out ?-Ga2O3 substrate.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: March 27, 2018
    Assignees: TAMURA CORPORATION, KOHA CO., LTD.
    Inventors: Takekazu Masui, Yu Yamaoka
  • Patent number: 9773812
    Abstract: A structure includes an off-axis Si substrate with an overlying s-Si1?xGex layer and a BOX between the off-axis Si substrate and the s-Si1?xGex layer. The structure further includes pFET fins formed in the s-Si1?xGex layer and a trench formed through the s-Si1?xGex layer, the BOX and partially into the off-axis Si substrate. The trench contains a buffer layer in contact with the off-axis Si substrate, a first Group III-V layer disposed on the buffer layer, a semi-insulating Group III-V layer disposed on the first Group III-V layer and a second Group III-V layer disposed on the semi-insulating Group III-V layer, as well as nFET fins formed in the second Group III-V layer. The s-Si1?xGex layer has a value of x that results from a condensation process that merges an initial s-Si1?xGex layer with an initial underlying on-axis <100> Si layer. A method to fabricate the structure is also disclosed.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: September 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Pouya Hashemi, Effendi Leobandung, Alexander Reznicek
  • Patent number: 9735175
    Abstract: A structure includes an off-axis Si substrate with an overlying s-Si1-xGex layer and a BOX between the off-axis Si substrate and the s-Si1-xGex layer. The structure further includes pFET fins formed in the s-Si1-xGex layer and a trench formed through the s-Si1-xGex layer, the BOX and partially into the off-axis Si substrate. The trench contains a buffer layer in contact with the off-axis Si substrate, a first Group III-V layer disposed on the buffer layer, a semi-insulating Group III-V layer disposed on the first Group III-V layer and a second Group III-V layer disposed on the semi-insulating Group III-V layer, as well as nFET fins formed in the second Group III-V layer. The s-Si1-xGex layer has a value of x that results from a condensation process that merges an initial s-Si1-xGex layer with an initial underlying on-axis <100> Si layer. A method to fabricate the structure is also disclosed.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: August 15, 2017
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Pouya Hashemi, Effendi Leobandung, Alexander Reznicek
  • Patent number: 9691712
    Abstract: Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: June 27, 2017
    Assignee: The Regents of the University of California
    Inventors: Hugues Marchand, Brendan J. Moran, Umesh K. Mishra, James S. Speck
  • Patent number: 9460921
    Abstract: A nanowire article includes a substrate; a plurality of nanowires disposed on the substrate, the nanowires comprising a semiconductor nitride, the semiconductor comprising an element selected from group 3 of the periodic table; and a superlattice layer interposed between the substrate and the plurality of gallium nitride nanowires. A process for producing a nanowire article includes disposing a superlattice layer on a substrate; disposing a first buffer layer on the superlattice layer; contacting the first buffer layer with a precursor; and forming a plurality of nanowires from the precursor on the first buffer layer to form the nanowire article, the nanowires comprising a semiconductor nitride, the semiconductor comprising an element selected from group 3 of the periodic table.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: October 4, 2016
    Assignees: THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCE, REGENTS OF THE UNIVERISTY OF COLORADO
    Inventors: Kristine A. Bertness, Matthew D. Brubaker, William M. Old
  • Patent number: 9443737
    Abstract: Metal contact openings are etched in the barrier layer of a group III-N HEMT with a first gas combination that etches down into the barrier layer, and a second gas combination that etches further down into the barrier layer to a depth that lies above the top surface of a channel layer that touches and lies below the barrier layer.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: September 13, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yoshikazu Kondo, Shoji Wada, Hiroshi Yamasaki, Masahiro Iwamoto
  • Patent number: 9425400
    Abstract: An apparatus and method for coating an organic film are disclosed. The apparatus comprises an evaporation device, an electron emission device and a spray device; wherein the evaporation device comprises an evaporation container, the evaporation container is a linear evaporation container, in which a uniform organic gas is generated; the electron emission device is horizontally arranged over the evaporation container such that the organic gas evaporated in the evaporation container is uniformly charged and becomes charged organic gas; the spray device is provided with an electric field, under which the charged organic gas is moved toward a substrate so as to deposit the organic film on the substrate.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: August 23, 2016
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wulin Shen, Chunsheng Jiang, Qing Dai, Haijing Chen, Guangcai Yuan, Jingang Fang
  • Patent number: 9406538
    Abstract: In some embodiments, an indexed inline substrate processing tool may include a substrate carrier having a base and pair of opposing substrate supports having respective substrate support surfaces that extend upwardly and outwardly from the base; and a plurality of modules coupled to one another in a linear arrangement, wherein each module of the plurality of modules comprises an enclosure having a first end, a second end, and a lower surface to support the substrate carrier and to provide a path for the substrate carrier to move linearly through the plurality of modules, and wherein at least one module of the plurality of modules comprises: a window disposed in a side of the enclosure; a heating lamp coupled to the side of the enclosure; a gas inlet disposed proximate a top of the enclosure; and an exhaust disposed opposite the gas inlet.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: August 2, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventor: David K. Carlson
  • Patent number: 9312487
    Abstract: An apparatus and method for coating an organic film are disclosed. The apparatus comprises an evaporation device, an electron emission device and a spray device; wherein the evaporation device comprises an evaporation container, the evaporation container is a linear evaporation container, in which a uniform organic gas is generated; the electron emission device is horizontally arranged over the evaporation container such that the organic gas evaporated in the evaporation container is uniformly charged and becomes charged organic gas; the spray device is provided with an electric field, under which the charged organic gas is moved toward a substrate so as to deposit the organic film on the substrate.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: April 12, 2016
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wulin Shen, Chunsheng Jiang, Qing Dai, Haijing Chen, Guangcai Yuan, Jingang Fang
  • Patent number: 9312440
    Abstract: An epitaxy structure of a light emitting element includes a gallium nitride substrate, an N-type gallium nitride layer, a quantum well unit, and a P-type gallium nitride layer. The gallium nitride substrate includes a gallium nitride buffer layer, a gallium nitride hexagonal prism, and a gallium nitride hexagonal pyramid. The gallium nitride hexagonal prism extends from the gallium nitride buffer layer along an axis. The gallium nitride hexagonal pyramid extends from the gallium nitride hexagonal prism along the axis and gradually expands to form a hexagonal frustum. The N-type gallium nitride layer is located on the gallium nitride hexagonal pyramid. The quantum well unit includes an indium gallium nitride layer located on the N-type gallium nitride layer and a gallium nitride layer located on the indium gallium nitride layer. The P-type gallium nitride layer is located on the gallium nitride layer.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: April 12, 2016
    Assignee: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventors: I-Kai Lo, Yu-Chi Hsu, Cheng-Hung Shih, Wen-Yuan Pang
  • Patent number: 9209018
    Abstract: A method for forming a substrate includes forming a base layer comprising a Group III-V material on a substrate, cooling the base layer and inducing cracks in the base layer, and forming a bulk layer comprising a Group III-V material on the base layer after cooling.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: December 8, 2015
    Assignee: SAINT-GOBAIN CRISTAUX ET DETECTEURS
    Inventors: Bernard Beaumont, Jean-Pierre Faurie
  • Patent number: 9093478
    Abstract: The present disclosure generally provides for an integrated circuit (IC) structure with a bulk silicon finFET and methods of forming the same.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: July 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Qizhi Liu, Edward J. Nowak, Jed H. Rankin
  • Patent number: 9029244
    Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: May 12, 2015
    Assignees: Samsung Electronics Co., Ltd., Genitech, Inc.
    Inventors: Seok-jun Won, Yong-min Yoo, Dae-youn Kim, Young-hoon Kim, Dae-jin Kwon, Weon-hong Kim
  • Patent number: 9023673
    Abstract: A method to grow single phase group III-nitride articles including films, templates, free-standing substrates, and bulk crystals grown in semi-polar and non-polar orientations is disclosed. One or more steps in the growth process includes the use of additional free hydrogen chloride to eliminate undesirable phases, reduce surface roughness, and increase crystalline quality. The invention is particularly well-suited to the production of single crystal (11.2) GaN articles that have particular use in visible light emitting devices.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: May 5, 2015
    Assignee: Ostendo Technologies, Inc.
    Inventors: Lisa Shapovalov, Oleg Kovalenkov, Vladimir Ivantsov, Vitali Soukhoveev, Alexander Syrkin, Alexander Usikov
  • Patent number: 9012308
    Abstract: A method for pseudomorphic growth and integration of an in-situ doped, strain-compensated metastable compound base into an electronic device, such as, for example, a SiGe NPN HBT, by substitutional placement of strain-compensating atomic species. The invention also applies to strained layers in other electronic devices such as strained SiGe, Si in MOS applications, vertical thin film transistors (VTFT), and a variety of other electronic device types. Devices formed from compound semiconductors other than SiGe, such as, for example, GaAs, InP, and AlGaAs are also amenable to beneficial processes described herein.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: April 21, 2015
    Assignee: Atmel Corporation
    Inventors: Darwin Gene Enicks, John Chaffee, Damian A. Carver
  • Patent number: 9012887
    Abstract: The present invention relates to growth of III-V semiconductor nanowires (2) on a Si substrate (3). Controlled vertical nanowire growth is achieved by a step, to be taken prior to the growing of the nanowire, of providing group III or group V atoms to a (111) surface of the Si substrate to provide a group III or group V 5 surface termination (4). A nanostructured device including a plurality of aligned III-V semiconductor nanowires (2) grown on, and protruding from, a (111) surface of a Si substrate (3) in an ordered pattern in compliance with a predetermined device layout is also presented.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: April 21, 2015
    Assignee: Qunano AB
    Inventors: Lars Samuelson, Jonas Ohlsson, Thomas Mårtensson, Patrik Svensson
  • Patent number: 9006865
    Abstract: In heteroepitaxially growing a group-III nitride semiconductor on a Si single crystal substrate, the occurrence of cracks initiating in the wafer edge portion can be suppressed. Region A is an outermost peripheral portion outside the principal surface, being a bevel portion tapered. Regions B and C are on the same plane (the principal surface), region B (mirror-surface portion) being the center portion of the principal surface, and region C a region in the principal surface edge portion surrounding region B. The principal surface has a plane orientation, and in region B, is mirror-surface-finished. Region B occupies most of the principal surface of this Si single crystal substrate, and a semiconductor device is manufactured therein. Region C (surface-roughened portion) has a plane orientation as with region B, however, region B is mirror-surface-finished, whereas region C is surface-roughened.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: April 14, 2015
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Tetsuya Ikuta, Daisuke Hino, Tomohiko Shibata
  • Patent number: 8993999
    Abstract: According to an embodiment, a semiconductor light emitting device is configured to emit light by energy relaxation of an electron between subbands of a plurality of quantum wells. The device includes an active layer and at least a pair of cladding layers. The active layer is provided in a stripe shape extending in a direction parallel to an emission direction of the light, and includes the plurality of quantum wells; and the active layer emits the light with a wavelength of 10 ?m or more. Each of the cladding layers is provided both on and under the active layer respectively and have a lower refractive index than the active layer. At least one portion of the cladding layers contains a material having a different lattice constant from the active layer and has a lower optical absorption at a wavelength of the light than the other portion.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeyuki Takagi, Hidehiko Yabuhara
  • Patent number: 8993441
    Abstract: A method of forming a thin layer and a method of manufacturing a phase change memory device, the method of forming a thin layer including providing a first deposition source onto a substrate, the first deposition source not including tellurium; and providing a second deposition source onto the substrate, the second deposition source including a first tellurium precursor represented by the following Formula 1 and a second tellurium precursor represented by following the Formula 2: Te(CH(CH3)2)2??Formula 1 Ten(CH(CH3)2)2??Formula 2 wherein, in Formula 2, n is an integer greater than or equal to 2.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: March 31, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Do-Hyung Kim, Eun-Tae Kim, Sung-Lae Cho
  • Patent number: 8975728
    Abstract: A second epitaxial layer is grown epitaxially over a first epitaxial layer. The first epitaxial layer includes an epitaxially grown layer and a defect layer. The defect layer is disposed over the epitaxially grown layer and serves as a surface layer of the first epitaxial layer. The defect density of the defect layer is 5×1017 cm?2 or more. Defects penetrating through the defect layer form loops in the second epitaxial layer.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Ikarashi, Masayasu Tanaka
  • Patent number: 8956929
    Abstract: In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer. Then, parts of the interlayer insulating layer and the conductive layer over the gate electrode layer are removed by a chemical mechanical polishing method, so that a source electrode layer and a drain electrode layer are formed. Before formation of the gate insulating layer, cleaning treatment is performed on the oxide semiconductor layer.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: February 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuji Egi, Hideomi Suzawa, Shinya Sasagawa
  • Patent number: 8940579
    Abstract: Disclosed are new methods of fabricating metal oxide thin films and nanomaterial-derived metal composite thin films via solution processes at low temperatures (<400° C.). The present thin films are useful as thin film semiconductors, thin film dielectrics, or thin film conductors, and can be implemented into semiconductor devices such as thin film transistors and thin film photovoltaic devices.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 27, 2015
    Assignees: Northwestern University, Polyera Corporation
    Inventors: Antonio Facchetti, Tobin J. Marks, Mercouri G. Kanatzidis, Myung-Gil Kim, William Christopher Sheets, He Yan, Yu Xia
  • Patent number: 8940622
    Abstract: A method for manufacturing a compound semiconductor device, the method includes: forming a compound semiconductor laminated structure; removing a part of the compound semiconductor laminated structure, so as to form a concave portion; and cleaning the inside of the concave portion by using a detergent, wherein the detergent contains a base resin compatible with residues present in the concave portion and a solvent.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: January 27, 2015
    Assignee: Fujitsu Limited
    Inventor: Junichi Kon
  • Patent number: 8927398
    Abstract: A patterned substrate is provided having at least two mesa surface portions, and a recessed surface located beneath and positioned between the at least two mesa surface portions. A Group III nitride material is grown atop the mesa surface portions of the patterned substrate and atop the recessed surface. Growth of the Group III nitride material is continued merging the Group III nitride material that is grown atop the mesa surface portions. When the Group III nitride material located atop the mesa surface portions merge, the Group III nitride material growth on the recessed surface ceases. The merged Group III nitride material forms a first Group III nitride material structure, and the Group III nitride material formed in the recessed surface forms a second material structure. The first and second material structures are disjoined from each other and are separated by an air gap.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Can Bayram, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 8921147
    Abstract: A multi-stage method and apparatus for vaporizing and depositing a tellurium containing semiconductor material on a substrate.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: December 30, 2014
    Assignee: First Solar, Inc.
    Inventors: Arnold Allenic, Zhigang Ban, John Barden, Benjamin Milliron, Rick C. Powell
  • Patent number: 8916456
    Abstract: A substrate including a body comprising a Group III-V material and having an upper surface, the body comprising an offcut angle defined between the upper surface and a crystallographic reference plane, and the body further having an offcut angle variation of not greater than about 0.6 degrees.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: December 23, 2014
    Assignee: Saint-Gobain Cristaux et Detecteurs
    Inventors: Jean-Pierre Faurie, Bernard Beaumont
  • Patent number: 8912081
    Abstract: The present invention relates to a method for relaxing a strained material layer by providing a strained material layer and a low-viscosity layer formed on a first face of the strained material layer; forming a stiffening layer on at least one part of a second face of the strained material layer opposite to the first face thereby forming a multilayer stack; and subjecting the multilayer stack to a heat treatment thereby at least partially relaxing the strained material layer.
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: December 16, 2014
    Assignee: SOITEC
    Inventor: Bruce Faure
  • Patent number: 8895414
    Abstract: A method of forming an amorphous silicon film includes: forming a seed layer on a surface of a base by heating the base and supplying an amino silane-based gas to the heated base, forming the amorphous silicon film with thickness for layer growth on the seed layer by heating the base and supplying a silane-based gas containing no amino group to the seed layer on the surface of the heated base, and decreasing a film thickness of the amorphous silicon film by etching the amorphous silicon film formed with thickness for layer growth.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: November 25, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Akinobu Kakimoto, Satoshi Takagi, Kazumasa Igarashi
  • Patent number: 8895335
    Abstract: A method for impurity-induced disordering in III-nitride materials comprises growing a III-nitride heterostructure at a growth temperature and doping the heterostructure layers with a dopant during or after the growth of the heterostructure and post-growth annealing of the heterostructure. The post-growth annealing temperature can be sufficiently high to induce disorder of the heterostructure layer interfaces.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: November 25, 2014
    Assignee: Sandia Corporation
    Inventors: Jonathan J. Wierer, Jr., Andrew A. Allerman
  • Patent number: 8890212
    Abstract: According to example embodiments, a normally-off high electron mobility transistor (HEMT) includes: a channel layer having a first nitride semiconductor, a channel supply layer on the channel layer, a source electrode and a drain electrode at sides of the channel supply layer, a depletion-forming layer on the channel supply layer, a gate insulating layer on the depletion-forming layer, and a gate electrode on the gate insulation layer. The channel supply layer includes a second nitride semiconductor and is configured to induce a two-dimensional electron gas (2DEG) in the channel layer. The depletion-forming layer is configured has at least two thicknesses and is configured to form a depletion region in at least a partial region of the 2DEG. The gate electrode contacts the depletion-forming layer.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: November 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-chul Jeon, Young-hwan Park, Jae-joon Oh, Kyoung-yeon Kim, Joon-yong Kim, Ki-yeol Park, Jai-kwang Shin, Sun-kyu Hwang
  • Patent number: 8889530
    Abstract: A highly dislocation free compound semiconductor, e.g. AlxInyGa1-x-yN (0?x, y?1), is formed on a lattice mismatched substrate, e.g. Si, by first depositing a polycrystalline buffer layer on the substrate. A defective layer is then created at or near the interface of the substrate and the polycrystalline buffer layer, e.g. through ion implantation. A monocrystalline template layer of the compound semiconductor is then created on the buffer layer, and an epilayer of the compound semiconductor is grown on the template layer. A compound semiconductor based device structure may be formed in the epilayer.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: November 18, 2014
    Assignee: The Research Foundation of State University of New York
    Inventors: Fatemeh Shahedipour-Sandvik, Di Wu, Jamil Kahn Muhammad
  • Patent number: 8877599
    Abstract: A semiconductor device having dislocations and a method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having an isolation feature therein and two gate stacks overlying the substrate, wherein one of the gate stacks is atop the isolation feature. The method further includes performing a pre-amorphous implantation process on the substrate. The method further includes forming a stress film over the substrate. The method also includes performing an annealing process on the substrate and the stress film.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: November 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ziwei Fang, Tsan-Chun Wang, De-Wei Yu
  • Publication number: 20140322837
    Abstract: A method of forming nanocrystals includes loading a substrate into a chamber, applying a first voltage to a first target to form a thin film including a first metal compound on the substrate by sputtering, and applying a second voltage to a second target and forming nanocrystals in the thin film by sputtering.
    Type: Application
    Filed: August 23, 2013
    Publication date: October 30, 2014
    Applicant: Samsung Display Co., Ltd.
    Inventors: Myung-Soo Huh, Suk-Won Jung, Tae-Wook Kang
  • Patent number: 8871581
    Abstract: A III-nitride switch includes a recessed gate contact to produce a nominally off, or an enhancement mode, device. By providing a recessed gate contact, a conduction channel formed at the interface of two III-nitride materials is interrupted when the gate electrode is inactive to prevent current flow in the device. The gate electrode can be a schottky contact or an insulated metal contact. Two gate electrodes can be provided to form a bi-directional switch with nominally off characteristics. The recesses formed with the gate electrode can have sloped sides. The gate electrodes can be formed in a number of geometries in conjunction with current carrying electrodes of the device.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: October 28, 2014
    Assignee: International Rectifier Corporation
    Inventor: Robert Beach
  • Publication number: 20140308802
    Abstract: Described herein is a method and precursor composition for depositing a multicomponent film. In one embodiment, the method and composition described herein is used to deposit a germanium-containing film such as Germanium Tellurium, Antimony Germanium, and Germanium Antimony Tellurium (GST) films via an atomic layer deposition (ALD) and/or other germanium, tellurium and selenium based metal compounds for phase change memory and photovoltaic devices. In this or other embodiments, the Ge precursor used comprises trichlorogermane.
    Type: Application
    Filed: April 4, 2014
    Publication date: October 16, 2014
    Applicant: AIR PRODUCTS AND CHEMICALS, INC.
    Inventors: Manchao Xiao, Iain Buchanan, MOO-SUNG KIM, Sergei Vladimirovich Ivanov, Xinjian Lei, Cheol Seong Hwang, TAEHONG GWON
  • Patent number: 8859319
    Abstract: Methods of forming photo detectors are provided. The method includes providing a semiconductor layer on a substrate, forming a trench in the semiconductor layer, forming a first single crystalline layer and a second single crystalline layer using a selective single crystalline growth process in the trench, and patterning the first and second single crystalline layers and the semiconductor layer to form a first single crystalline pattern, a second single crystalline pattern and an optical waveguide.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: October 14, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sang Hoon Kim, Gyungock Kim, In Gyoo Kim, JiHo Joo, Ki Seok Jang
  • Patent number: 8853828
    Abstract: An epitaxial substrate, in which a group of group-III nitride layers is formed on a single-crystal silicon substrate so that a crystal plane is approximately parallel to a substrate surface, comprises: a first group-III nitride layer formed of AlN on the base substrate; a second group-III nitride layer formed of InxxAlyyGazzN (xx+yy+zz=1, 0?xx?1, 0<yy?1 and 0<zz?1) on the first group-III nitride layer; and at least one third group-III nitride layer epitaxially-formed on the second group-III nitride layer, wherein: the first group-III nitride layer is a layer containing multiple defects including at least one type of a columnar crystal, a granular crystal, a columnar domain and a granular domain; and an interface between the first group-III nitride layer and the second group-III nitride layer is a three-dimensional asperity surface.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: October 7, 2014
    Assignee: NGK Insulators, Ltd.
    Inventors: Shigeaki Sumiya, Makoto Miyoshi, Tomohiko Sugiyama, Mikiya Ichimura, Yoshitaka Kuraoka, Mitsuhiro Tanaka
  • Publication number: 20140295651
    Abstract: A method includes forming a stress compensation layer over a first side of a semiconductor substrate and forming a Group III-nitride layer over a second side of the substrate. Stress created on the substrate by the Group III-nitride layer is at least partially reduced by stress created on the substrate by the stress compensation layer. Forming the stress compensation layer could include forming a stress compensation layer from amorphous or microcrystalline material. Also, the method could include crystallizing the amorphous or microcrystalline material during subsequent formation of one or more layers over the second side of the substrate. Crystallizing the amorphous or microcrystalline material could occur during subsequent formation of the Group III-nitride layer and/or during an annealing process. The amorphous or microcrystalline material could create no or a smaller amount of stress on the substrate, and the crystallized material could create a larger amount of stress on the substrate.
    Type: Application
    Filed: June 11, 2014
    Publication date: October 2, 2014
    Inventor: Jamal RAMDANI
  • Patent number: 8846502
    Abstract: Atomic layer deposition (ALD) processes for forming thin films comprising GaN are provided. In some embodiments, ALD processes for forming doped GaN thin films are provided. The thin films may find use, for example, in light-emitting diodes.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: September 30, 2014
    Assignee: ASM IP Holding B.V.
    Inventors: Suvi Haukka, Viljami J. Pore, Antti Niskanen
  • Patent number: 8841177
    Abstract: First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one dielectric bonding material layer is deposited, and a handle substrate is bonded to the at least one dielectric bonding material layer. The single crystalline substrate, the dielectric template material layer, and the first and second template epitaxial semiconductor material portions are subsequently removed. Elemental semiconductor devices and compound semiconductor devices can be formed on the first and second semiconductor portions, which are embedded within the at least one dielectric bonding material layer on the handle substrate.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Tze-Chiang Chen, Cheng-Wei Cheng, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 8802547
    Abstract: A method of forming an amorphous silicon film includes: forming a seed layer on a surface of a base by heating the base and supplying an amino silane-based gas to the heated base, forming the amorphous silicon film with thickness for layer growth on the seed layer by heating the base and supplying a silane-based gas containing no amino group to the seed layer on the surface of the heated base, and decreasing a film thickness of the amorphous silicon film by etching the amorphous silicon film formed with thickness for layer growth.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: August 12, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Akinobu Kakimoto, Satoshi Takagi, Kazumasa Igarashi