Abstract: Disclosed are a semiconductor structure and a manufacturing method therefor, solving the problem that it is difficult for an existing semiconductor structure to deplete a carrier concentration of a channel under a gate so as to achieve an enhancement-mode device. The semiconductor structure comprises: a channel layer and a barrier layer stacked in sequence. A gate region is defined on a surface of the barrier layer; a plurality of trenches formed in the gate region. The plurality of trenches are extended into the channel layer; and a stress applying material filled in the plurality of trenches. A lattice constant of the stress applying material is greater than that of the channel layer.

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistor arrangements that may reduce nonlinearity of off-state capacitance of the III-N transistors. In various aspects, III-N transistor arrangements limit the extent of access regions of the transistors, compared to conventional implementations, which may limit the depletion of the access regions. Due to the limited extent of the depletion regions of a transistor, the off-state capacitance may exhibit less variability in values across different gate-source voltages and, hence, exhibit a more linear behavior during operation.

Abstract: To provide a gallium oxide-based semiconductor with its bandgap being sufficiently reduced, and a manufacturing method thereof. A gallium oxide-based semiconductor containing a mixed crystal having a composition represented by (Ga(1-x)Fex)2yO3, wherein 0.10?x?0.40 and 0.85?y?1.2, wherein the mixed crystal has a beta-gallia structure, is provided. Also, a method for manufacturing the gallium oxide-based semiconductor, including depositing a mixed crystal having a composition represented by (Ga(1-x)Fex)2yO3, wherein 0.10?x?0.40 and 0.85?y?1.2 on a substrate surface by a pulsed laser deposition method, wherein denoting the temperature of the substrate as T° C., x and T satisfy the relationship represented by 500x+800?T<1,000, is provided.

Abstract: A transistor that is to be provided has such a structure that a source electrode layer and a drain electrode layer between which a channel formation region is sandwiched has regions projecting in a channel length direction at lower end portions, and an insulating layer is provided, in addition to a gate insulating layer, between the source and drain electrode layers and a gate electrode layer. In the transistor, the width of the source and drain electrode layers is smaller than that of an oxide semiconductor layer in the channel width direction, so that an area where the gate electrode layer overlaps with the source and drain electrode layers can be made small. Further, the source and drain electrode layers have regions projecting in the channel length direction at lower end portions.

Abstract: A second semiconductor layer is oxidized through a groove and a fourth semiconductor layer is oxidized, a first oxide layer is formed, and a second oxide layer is formed. By oxidizing the entire second semiconductor layer and the fourth semiconductor layer, the first oxide layer and the second oxide layer in an amorphous state are formed.

Abstract: A method for manufacturing an III-nitride semiconductor structure is provided.

Abstract: The present invention relates to a silicon carbide (SiC) substrate with improved mechanical and electrical characteristics. Furthermore, the invention relates to a method for producing a bulk SiC crystal in a physical vapor transport growth system. The silicon carbide substrate comprises an inner region (102) which constitutes at least 30% of a total surface area of said substrate (100), a ring shaped peripheral region (104) radially surrounding the inner region (102), wherein a mean concentration of a dopant in the inner region (102) differs by at least 1-1018 cm-3 from the mean concentration of this dopant in the peripheral region (104).

Abstract: A nitride semiconductor device is disclosed. The semiconductor device is formed by a process that first deposits a silicon nitride (SiN) film on a semiconductor layer by the lower pressure chemical vapor deposition (LPCVD) technique at a temperature, then, forming an opening in the SiN film for an ohmic electrode. Preparing a photoresist on the SiN film, where the photoresist provides an opening that fully covers the opening in the SiN film, the process exposes a peripheral area around the opening of the SiN film to chlorine (Cl) plasma that may etch the semiconductor layer to form a recess therein. Metals for the ohmic electrode are filled within the recess in the semiconductor layer and the peripheral area of the SiN film. Finally, the metals are alloyed at a temperature lower than the deposition temperature of the SiN film.

Abstract: A memory device including a first conductive line on a substrate and extending in a first horizontal direction; a second conductive line on the first conductive line and extending in a second horizontal direction that is perpendicular to the first horizontal direction; and a memory cell between the first conductive line and the second conductive line, the memory cell including a variable resistance memory layer, a buffer resistance layer, and a switch material pattern, extending in a vertical direction that is perpendicular to the first horizontal direction and the second horizontal direction, and having a tapered shape with a decreasing horizontal width along the vertical direction, wherein at least a part of the variable resistance memory layer and at least a part of the buffer resistance layer of the memory cell are at a same vertical level.

Abstract: Disclosed is a method for making interconnected solar cells, including: a) providing a continuous layer stack on a substrate, including a top electrode layer, a bottom electrode layer adjacent to the substrate, a photovoltaic active layer and a barrier layer adjacent to the bottom electrode layer between the top and bottom electrode layers; b) selectively removing the top electrode layer and the photo-voltaic layer for obtaining a first trench exposing the barrier layer using a first laser beam with a first wavelength; c) selectively removing the barrier layer and the bottom electrode layer within the first trench for obtaining a second trench exposing the substrate using a second laser beam with a second wavelength, d) filling the first trench and the second trench with electrical insulating member. The first wavelength of the first laser beam is larger than a wavelength corresponding with a bandgap energy of the photo-voltaic layer.

Abstract: A group III nitride laminate having monocrystalline n-type AlxGa1-xN (0.7?X?1.0) and an electrode is provided. The group III nitride laminate is characterized in that an n-type contact layer made of (AlYGa1-Y)2O3 (0.0?Y<0.3) is provided between the monocrystalline n-type AlxGa1-xN (0.7?X?1.0) and the electrode. Furthermore, a vertical semiconductor device including the above-described group III nitride laminate is provided.

Abstract: Embodiments of the invention are directed to a biosensing integrated circuit (IC). A non-limiting example of the biosensing IC includes a plurality of semiconductor substrate layers. A sensor element is formed over a first one of the plurality of semiconductor substrate layers, wherein the sensor element is configured to, based at least in part on the sensor element interacting with a predetermined material, generate data representing a measurable electrical parameter. An adhesion enhancement region is configured to physically couple the sensor element to the first one of the plurality of semiconductor substrate layers. In some embodiments of the invention, the biosensing IC further includes an electrically conductive interconnect network configured to communicatively couple the data representing the measurable electrical parameter to computer elements.

Abstract: Semiconductor structures formed with annealing for use in the fabrication of optoelectronic devices. The semiconductor structures can include a substrate, a nucleation layer and a buffer layer. The nucleation layer and the buffer layer can be epitaxially grown and then annealed. The temperature of the annealing of the nucleation layer and the buffer layer is greater than the temperature of the epitaxial growth of the layers. The annealing reduces the dislocation density in any subsequent layers that are added to the semiconductor structures. A desorption minimizing layer epitaxially grown on the buffer layer can be used to minimize desorption during the annealing of the layer which also aids in curtailing dislocation density and cracks in the semiconductor structures.

Abstract: Embodiments of the invention are directed to a biosensing integrated circuit (IC). A non-limiting example of the biosensing IC includes a plurality of semiconductor substrate layers. A sensor element is formed over a first one of the plurality of semiconductor substrate layers, wherein the sensor element is configured to, based at least in part on the sensor element interacting with a predetermined material, generate data representing a measureable electrical parameter. An adhesion enhancement region is configured to physically couple the sensor element to the first one of the plurality of semiconductor substrate layers. In some embodiments of the invention, the biosensing IC further includes an electrically conductive interconnect network configured to communicatively couple the data representing the measureable electrical parameter to computer elements.

Abstract: A dislocation filter for a semiconductor device has a buffer layer comprising a short-period superlattice (SPSL) layer. The SPSL layer has first sub-layers of a first material that alternate with second sub-layers of a second material, the first material and the second material being group III-N binary materials that are different from each other. Each of the first sub-layers and each of the second sub-layers has a sub-layer thickness less than or equal to 12 monolayers. The buffer layer also includes a third layer of a third material, the third material being a group III-N material. The SPSL forms a sandwich structure with the third layer. The buffer layer bends dislocations away from a growth direction of the buffer layer.

Abstract: A substrate transport system is disclosed and includes a chamber having an interior wall, a planar motor disposed on the interior wall, and a substrate carrier magnetically coupled to the planar motor. The substrate carrier comprises a base and a substrate supporting surface coupled to a support member extending from the base in a cantilevered orientation.

Abstract: A semiconductor structure including a source/drain region is disclosed. The source/drain region may include a first epitaxial region along at least one sidewall of the source/drain region having a substantially uniform sidewall thickness. The semiconductor structure may further include a gate structure adjacent and above the source/drain region wherein at least a portion of the first epitaxial region is positioned below a sidewall spacer of the gate structure. A method of forming a source/drain region including a first epitaxial region having a substantially uniform sidewall thickness is disclosed. The method may include forming a trench in a substrate adjacent to a gate structure, forming the first epitaxial region in the trench, forming a spacer material layer on the gate structure and on a portion of the first epitaxial region, and removing a portion of the first epitaxial region using the spacer material layer as a mask.

Abstract: Native oxides and residue are removed from surfaces of a substrate by performing a multiple-stage native oxide cleaning process. In one example, the method for removing native oxides from a substrate includes supplying a first gas mixture including an inert gas onto a surface of a material layer disposed on a substrate into a first processing chamber, wherein the material layer is a III-V group containing layer for a first period of time, supplying a second gas mixture including an inert gas and a hydrogen containing gas onto the surface of the material layer for a second period of time, and supplying a third gas mixture including a hydrogen containing gas to the surface of the material layer while maintaining the substrate at a temperature less than 550 degrees Celsius.

Abstract: The present invention discloses an electronic device formed of a group III nitride. In one embodiment, a substrate is fabricated by the ammonothermal method and a drift layer is fabricated by hydride vapor phase epitaxy. After etching a trench, p-type contact pads are made by pulsed laser deposition followed by n-type contact pads by pulsed laser deposition. The bandgap of the p-type contact pad is designed larger than that of the drift layer. Upon forward bias between p-type contact pads (gate) and n-type contact pads (source), holes and electrons are injected into the drift layer from the p-type contact pads and n-type contact pads. Injected electrons drift to the backside of the substrate (drain).

Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.

Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.

Abstract: This hetero-junction bipolar transistor includes a first n-type GaN layer, an AlxGa1-xN layer (0.1?x?0.5), an undoped GaN layer having a thickness of not less than 20 nm, a Mg-doped p-type GaN layer having a thickness of not less than 100 nm, and a second n-type GaN layer which are sequentially stacked. The first n-type GaN layer and the AlxGa1-xN layer form an emitter, the undoped GaN layer and the p-type GaN layer form a base, and the second n-type GaN layer forms a collector. During non-operation, two-dimensional hole gas is formed in a part of the undoped GaN layer near the hetero interface between the AlxGa1-xN layer and the undoped GaN layer. When the thickness of the p-type GaN layer is b [nm], the hole concentration of the p-type GaN layer is p [cm?3], and the concentration of the two-dimensional hole gas is Ps [cm?2], p×b×10?7+Ps?1×1013 [cm?2] is satisfied.

Abstract: A solar cell includes a substrate containing a first impurity of a first conductivity type and made of a crystalline semiconductor, an emitter region positioned on the substrate and containing a second impurity of a second conductivity type different from the first conductivity type, the emitter region being made of a non-crystalline semiconductor, a surface field region positioned on the substrate and containing a third impurity of the first conductivity type, the surface field region being made of non-crystalline semiconductor, a first electrode connected to the emitter region, and a second electrode connected to the surface field region, wherein at least one of the emitter region and the surface field region is made of amorphous metal silicide containing a metal material.

Abstract: Provided are: a method for producing a ?-Ga2O3 substrate of which changes in donor concentration in a reducing atmosphere or an inert gas atmosphere are suppressed; and a method for producing a crystal laminate structure that can epitaxially grow a high-quality crystal film having low variability of quality in a reducing atmosphere or an inert gas atmosphere. The method for producing a ?-Ga2O3 substrate includes a step for cutting out a ?-Ga2O3 substrate from a ?-Ga2O3 crystal containing a group IV element; annealing processing in an atmosphere containing a reducing atmosphere and/or an inert gas atmosphere is performed on the ?-Ga2O3 crystal before cutting out the ?-Ga2O3 substrate, or on the cut-out ?-Ga2O3 substrate.

Abstract: A structure includes an off-axis Si substrate with an overlying s-Si1?xGex layer and a BOX between the off-axis Si substrate and the s-Si1?xGex layer. The structure further includes pFET fins formed in the s-Si1?xGex layer and a trench formed through the s-Si1?xGex layer, the BOX and partially into the off-axis Si substrate. The trench contains a buffer layer in contact with the off-axis Si substrate, a first Group III-V layer disposed on the buffer layer, a semi-insulating Group III-V layer disposed on the first Group III-V layer and a second Group III-V layer disposed on the semi-insulating Group III-V layer, as well as nFET fins formed in the second Group III-V layer. The s-Si1?xGex layer has a value of x that results from a condensation process that merges an initial s-Si1?xGex layer with an initial underlying on-axis <100> Si layer. A method to fabricate the structure is also disclosed.

Abstract: A structure includes an off-axis Si substrate with an overlying s-Si1-xGex layer and a BOX between the off-axis Si substrate and the s-Si1-xGex layer. The structure further includes pFET fins formed in the s-Si1-xGex layer and a trench formed through the s-Si1-xGex layer, the BOX and partially into the off-axis Si substrate. The trench contains a buffer layer in contact with the off-axis Si substrate, a first Group III-V layer disposed on the buffer layer, a semi-insulating Group III-V layer disposed on the first Group III-V layer and a second Group III-V layer disposed on the semi-insulating Group III-V layer, as well as nFET fins formed in the second Group III-V layer. The s-Si1-xGex layer has a value of x that results from a condensation process that merges an initial s-Si1-xGex layer with an initial underlying on-axis <100> Si layer. A method to fabricate the structure is also disclosed.

Abstract: Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply.

Abstract: A nanowire article includes a substrate; a plurality of nanowires disposed on the substrate, the nanowires comprising a semiconductor nitride, the semiconductor comprising an element selected from group 3 of the periodic table; and a superlattice layer interposed between the substrate and the plurality of gallium nitride nanowires. A process for producing a nanowire article includes disposing a superlattice layer on a substrate; disposing a first buffer layer on the superlattice layer; contacting the first buffer layer with a precursor; and forming a plurality of nanowires from the precursor on the first buffer layer to form the nanowire article, the nanowires comprising a semiconductor nitride, the semiconductor comprising an element selected from group 3 of the periodic table.

Abstract: Metal contact openings are etched in the barrier layer of a group III-N HEMT with a first gas combination that etches down into the barrier layer, and a second gas combination that etches further down into the barrier layer to a depth that lies above the top surface of a channel layer that touches and lies below the barrier layer.

Abstract: An apparatus and method for coating an organic film are disclosed. The apparatus comprises an evaporation device, an electron emission device and a spray device; wherein the evaporation device comprises an evaporation container, the evaporation container is a linear evaporation container, in which a uniform organic gas is generated; the electron emission device is horizontally arranged over the evaporation container such that the organic gas evaporated in the evaporation container is uniformly charged and becomes charged organic gas; the spray device is provided with an electric field, under which the charged organic gas is moved toward a substrate so as to deposit the organic film on the substrate.

Abstract: In some embodiments, an indexed inline substrate processing tool may include a substrate carrier having a base and pair of opposing substrate supports having respective substrate support surfaces that extend upwardly and outwardly from the base; and a plurality of modules coupled to one another in a linear arrangement, wherein each module of the plurality of modules comprises an enclosure having a first end, a second end, and a lower surface to support the substrate carrier and to provide a path for the substrate carrier to move linearly through the plurality of modules, and wherein at least one module of the plurality of modules comprises: a window disposed in a side of the enclosure; a heating lamp coupled to the side of the enclosure; a gas inlet disposed proximate a top of the enclosure; and an exhaust disposed opposite the gas inlet.

Abstract: An apparatus and method for coating an organic film are disclosed. The apparatus comprises an evaporation device, an electron emission device and a spray device; wherein the evaporation device comprises an evaporation container, the evaporation container is a linear evaporation container, in which a uniform organic gas is generated; the electron emission device is horizontally arranged over the evaporation container such that the organic gas evaporated in the evaporation container is uniformly charged and becomes charged organic gas; the spray device is provided with an electric field, under which the charged organic gas is moved toward a substrate so as to deposit the organic film on the substrate.

Abstract: An epitaxy structure of a light emitting element includes a gallium nitride substrate, an N-type gallium nitride layer, a quantum well unit, and a P-type gallium nitride layer. The gallium nitride substrate includes a gallium nitride buffer layer, a gallium nitride hexagonal prism, and a gallium nitride hexagonal pyramid. The gallium nitride hexagonal prism extends from the gallium nitride buffer layer along an axis. The gallium nitride hexagonal pyramid extends from the gallium nitride hexagonal prism along the axis and gradually expands to form a hexagonal frustum. The N-type gallium nitride layer is located on the gallium nitride hexagonal pyramid. The quantum well unit includes an indium gallium nitride layer located on the N-type gallium nitride layer and a gallium nitride layer located on the indium gallium nitride layer. The P-type gallium nitride layer is located on the gallium nitride layer.

Abstract: A method for forming a substrate includes forming a base layer comprising a Group III-V material on a substrate, cooling the base layer and inducing cracks in the base layer, and forming a bulk layer comprising a Group III-V material on the base layer after cooling.

Abstract: The present disclosure generally provides for an integrated circuit (IC) structure with a bulk silicon finFET and methods of forming the same.

Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.

Abstract: A method to grow single phase group III-nitride articles including films, templates, free-standing substrates, and bulk crystals grown in semi-polar and non-polar orientations is disclosed. One or more steps in the growth process includes the use of additional free hydrogen chloride to eliminate undesirable phases, reduce surface roughness, and increase crystalline quality. The invention is particularly well-suited to the production of single crystal (11.2) GaN articles that have particular use in visible light emitting devices.

Abstract: A method for pseudomorphic growth and integration of an in-situ doped, strain-compensated metastable compound base into an electronic device, such as, for example, a SiGe NPN HBT, by substitutional placement of strain-compensating atomic species. The invention also applies to strained layers in other electronic devices such as strained SiGe, Si in MOS applications, vertical thin film transistors (VTFT), and a variety of other electronic device types. Devices formed from compound semiconductors other than SiGe, such as, for example, GaAs, InP, and AlGaAs are also amenable to beneficial processes described herein.

Abstract: The present invention relates to growth of III-V semiconductor nanowires (2) on a Si substrate (3). Controlled vertical nanowire growth is achieved by a step, to be taken prior to the growing of the nanowire, of providing group III or group V atoms to a (111) surface of the Si substrate to provide a group III or group V 5 surface termination (4). A nanostructured device including a plurality of aligned III-V semiconductor nanowires (2) grown on, and protruding from, a (111) surface of a Si substrate (3) in an ordered pattern in compliance with a predetermined device layout is also presented.

Abstract: In heteroepitaxially growing a group-III nitride semiconductor on a Si single crystal substrate, the occurrence of cracks initiating in the wafer edge portion can be suppressed. Region A is an outermost peripheral portion outside the principal surface, being a bevel portion tapered. Regions B and C are on the same plane (the principal surface), region B (mirror-surface portion) being the center portion of the principal surface, and region C a region in the principal surface edge portion surrounding region B. The principal surface has a plane orientation, and in region B, is mirror-surface-finished. Region B occupies most of the principal surface of this Si single crystal substrate, and a semiconductor device is manufactured therein. Region C (surface-roughened portion) has a plane orientation as with region B, however, region B is mirror-surface-finished, whereas region C is surface-roughened.

Abstract: A method of forming a thin layer and a method of manufacturing a phase change memory device, the method of forming a thin layer including providing a first deposition source onto a substrate, the first deposition source not including tellurium; and providing a second deposition source onto the substrate, the second deposition source including a first tellurium precursor represented by the following Formula 1 and a second tellurium precursor represented by following the Formula 2: Te(CH(CH3)2)2??Formula 1 Ten(CH(CH3)2)2??Formula 2 wherein, in Formula 2, n is an integer greater than or equal to 2.

Abstract: According to an embodiment, a semiconductor light emitting device is configured to emit light by energy relaxation of an electron between subbands of a plurality of quantum wells. The device includes an active layer and at least a pair of cladding layers. The active layer is provided in a stripe shape extending in a direction parallel to an emission direction of the light, and includes the plurality of quantum wells; and the active layer emits the light with a wavelength of 10 ?m or more. Each of the cladding layers is provided both on and under the active layer respectively and have a lower refractive index than the active layer. At least one portion of the cladding layers contains a material having a different lattice constant from the active layer and has a lower optical absorption at a wavelength of the light than the other portion.

Abstract: A second epitaxial layer is grown epitaxially over a first epitaxial layer. The first epitaxial layer includes an epitaxially grown layer and a defect layer. The defect layer is disposed over the epitaxially grown layer and serves as a surface layer of the first epitaxial layer. The defect density of the defect layer is 5×1017 cm?2 or more. Defects penetrating through the defect layer form loops in the second epitaxial layer.

Abstract: In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer. Then, parts of the interlayer insulating layer and the conductive layer over the gate electrode layer are removed by a chemical mechanical polishing method, so that a source electrode layer and a drain electrode layer are formed. Before formation of the gate insulating layer, cleaning treatment is performed on the oxide semiconductor layer.

Abstract: A method for manufacturing a compound semiconductor device, the method includes: forming a compound semiconductor laminated structure; removing a part of the compound semiconductor laminated structure, so as to form a concave portion; and cleaning the inside of the concave portion by using a detergent, wherein the detergent contains a base resin compatible with residues present in the concave portion and a solvent.

Abstract: Disclosed are new methods of fabricating metal oxide thin films and nanomaterial-derived metal composite thin films via solution processes at low temperatures (<400° C.). The present thin films are useful as thin film semiconductors, thin film dielectrics, or thin film conductors, and can be implemented into semiconductor devices such as thin film transistors and thin film photovoltaic devices.

Abstract: A patterned substrate is provided having at least two mesa surface portions, and a recessed surface located beneath and positioned between the at least two mesa surface portions. A Group III nitride material is grown atop the mesa surface portions of the patterned substrate and atop the recessed surface. Growth of the Group III nitride material is continued merging the Group III nitride material that is grown atop the mesa surface portions. When the Group III nitride material located atop the mesa surface portions merge, the Group III nitride material growth on the recessed surface ceases. The merged Group III nitride material forms a first Group III nitride material structure, and the Group III nitride material formed in the recessed surface forms a second material structure. The first and second material structures are disjoined from each other and are separated by an air gap.

Abstract: A multi-stage method and apparatus for vaporizing and depositing a tellurium containing semiconductor material on a substrate.

Abstract: A substrate including a body comprising a Group III-V material and having an upper surface, the body comprising an offcut angle defined between the upper surface and a crystallographic reference plane, and the body further having an offcut angle variation of not greater than about 0.6 degrees.

Abstract: The present invention relates to a method for relaxing a strained material layer by providing a strained material layer and a low-viscosity layer formed on a first face of the strained material layer; forming a stiffening layer on at least one part of a second face of the strained material layer opposite to the first face thereby forming a multilayer stack; and subjecting the multilayer stack to a heat treatment thereby at least partially relaxing the strained material layer.