Abstract: A method of manufacturing a vertical light emitting diode includes: providing a first substrate; forming a lapping stop layer on the first substrate, the lapping stop layer being harder than the first substrate; depositing an epitaxial layer on the lapping stop layer; bonding a second substrate on the epitaxial layer; and removing the first substrate from the lapping stop layer.

Abstract: Nitride-based film is grown using multiple precursor fluxes. Each precursor flux is pulsed one or more times to add a desired element to the nitride-based film at a desired time. The quantity, duration, timing, and/or shape of the pulses is customized for each element to assist in generating a high quality nitride-based film.

Abstract: A semiconductor device (1a) which is constituted by organic semiconductors with excellent transistor characteristics and includes: a p-type organic transistor (P1) having a gate electrode (12), a source electrode (14), a drain electrode (15), and a p-type organic semiconductor layer (16); an n-type organic transistor (N1) electrically connected with the p-type organic transistor (P1) and having a gate electrode (22), a source electrode (24), a drain electrode (25), and an n-type organic semiconductor layer (26); first layers for enhancing electric charge transfer, one of the first layers being provided between the source electrode (14) and the organic semiconductor layer (16), the other of the first layers being provided between the drain electrode (25) and the organic semiconductor (26); and second layers for enhancing electric charge transfer and made from a different material from that of the first layers, one of the second layers being provided between the drain electrode (15) and the organic semiconducto

Abstract: A manufacturing method of a group III nitride semiconductor includes the steps of: depositing a metal layer on an AlN template substrate or an AlN single crystal substrate formed by depositing an AlN single crystal layer with a thickness of not less than 0.1 ?m nor more than 10 ?m on a substrate made of either one of sapphire, SiC, and Si; forming a metal nitride layer having a plurality of substantially triangular-pyramid-shaped or triangular-trapezoid-shaped microcrystals by performing a heating nitridation process on the metal layer under a mixed gas atmosphere of ammonia; and depositing a group III nitride semiconductor layer on the metal nitride layer.

Abstract: According to the present invention, an AlN crystal film seed layer having high crystallinity is combined with selective/lateral growth, whereby a Group III nitride semiconductor multilayer structure more enhanced in crystallinity can be obtained. The Group III nitride semiconductor multilayer structure of the present invention is a Group III nitride semiconductor multilayer structure where an AlN crystal film having a crystal grain boundary interval of 200 nm or more is formed as a seed layer on a C-plane sapphire substrate surface by a sputtering method and an underlying layer, an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer, each composed of a Group III nitride semiconductor, are further stacked, wherein regions in which the seed layer is present and is absent are formed on the C-plane sapphire substrate surface and/or regions capable of epitaxial growth and incapable of epitaxial growth are formed in the underlying layer.

Abstract: A method for producing a group III nitride semiconductor light-emitting device including: an intermediate layer formation step in which an intermediate layer containing group III nitride is formed on a substrate by sputtering, and a laminate semiconductor formation step in which an n-type semiconductor layer having a base layer, a light-emitting layer, and a p-type semiconductor layer are laminated on the intermediate layer in this order, wherein the method includes a pretreatment step in which the intermediate layer is treated using plasma between the intermediate layer formation step and the laminate semiconductor formation step, and a formation step for the base layer which is included in the laminate semiconductor formation step is a step for laminating the base layer by sputtering.

Abstract: Methods for the heteroepitaxial growth of smooth, high quality films of N-face GaN film grown by MOCVD are disclosed. Use of a misoriented substrate and possibly nitridizing the substrate allow for the growth of smooth N-face GaN and other Group III nitride films as disclosed herein. The present invention also avoids the typical large (?m sized) hexagonal features which make N-face GaN material unacceptable for device applications. The present invention allows for the growth of smooth, high quality films which makes the development of N-face devices possible.

Abstract: The invention provides methods and structures for reducing surface dislocations of a semiconductor layer, and can be employed during the epitaxial growth of semiconductor structures and layers comprising III-nitride materials. Embodiments involve the formation of a plurality of dislocation pit plugs to prevent propagation of dislocations from an underlying layer of material into a following semiconductor layer of material.

Abstract: A deposition process to form a conformal phase change material film on the surface of a substrate to produce a memory device wafer comprises providing a substrate to a chamber of a deposition system; providing an activation region; introducing one or more precursors into the chamber upstream of the substrate; optionally introducing one or more co-reactants upstream of the substrate; activating the one or more precursors; heating the substrate; and depositing the phase change material film on the substrate from the one or more precursors by chemical vapor deposition. The deposited phase change material film comprises GexSbyTezAm in which A is a dopant selected from the group of N, C, In, Sn, and Se. In one implementation, the process is carried out to form GST films doped with carbon and nitrogen, to impart beneficial film growth and performance properties to the film.

Abstract: Germanium, tellurium, and/or antimony precursors are usefully employed to form germanium-, tellurium- and/or antimony-containing films, such as films of GeTe, GST, and thermoelectric germanium-containing films. Processes for using these precursors to form amorphous films are also described. Further described is the use of [{nBuC(iPrN)2}2Ge] or Ge butyl amidinate to form GeTe smooth amorphous films for phase change memory applications.

Abstract: A method of fabricating a single crystal gallium nitride substrate the step of cutting an ingot of single crystal gallium nitride along predetermined planes to make one or more single crystal gallium nitride substrates. The ingot of single crystal gallium nitride is grown by vapor phase epitaxy in a direction of a predetermined axis. Each predetermined plane is inclined to the predetermined axis. Each substrate has a mirror polished primary surface. The primary surface has a first area and a second area. The first area is between an edge of the substrate and a line 3 millimeter away from the edge. The first area surrounds the second area. An axis perpendicular to the primary surface forms an off-angle with c-axis of the substrate. The off-angle takes a minimum value at a first position in the first area of the primary surface.

Abstract: Provided is a method for preparing a compound semiconductor substrate. The method includes coating a plurality of spherical balls on a substrate, growing a compound semiconductor epitaxial layer on the substrate coated with the spherical balls while allowing voids to be formed under the spherical balls, and cooling the substrate on which the compound semiconductor epitaxial layer is grown so that the substrate and the compound semiconductor epitaxial layer are self-separated along the voids. The spherical ball treatment can reduce dislocation generations. In addition, because the substrate and the compound semiconductor epitaxial layer are separated through the self-separation, there is no need for laser lift-off process.

Abstract: An amorphous oxide semiconductor contains at least one element selected from In, Ga, and Zn at an atomic ratio of InxGayZnz, wherein the density M of the amorphous oxide semiconductor is represented by the relational expression (1) below: M?0.94×(7.121x+5.941y+5.675z)/(x+y+z)??(1) where 0?x?1, 0?y?1, 0?z?1, and x+y+z?0.

Abstract: There is provided a method for producing an a-IGZO oxide thin film by sputtering, which can control the carrier density of the film to a given value with high reproducibility. The method is an amorphous In—Ga—Zn—O based oxide thin film production method including: providing a sintered oxide material consisting essentially of indium (In), gallium (Ga), zinc (Zn), and oxygen (O) as constituent elements, wherein the ratio [In]/([In]+[Ga]) of the number of indium atoms to the total number of indium and gallium atoms is from 20% to 80%, the ratio [Zn]/([In]+[Ga]+[Zn]) of the number of zinc atoms to the total number of indium, gallium and zinc atoms is from 10% to 50%, and the sintered oxide material has a specific resistance of 1.0×10?1 ?cm or less; and producing a film on a substrate by direct current sputtering at a sputtering power density of 2.5 to 5.5 W/cm2 using the sintered oxide material as a sputtering target.

Abstract: One embodiment of depositing a gallium nitride (GaN) film on a substrate comprises providing a source of indium (In) and gallium (Ga) and depositing a monolayer of indium (In) on the surface of the gallium nitride (GaN) film. The monolayer of indium (In) acts as a surfactant to modify the surface energy and facilitate the epitaxial growth of the film by suppressing three dimensional growth and enhancing or facilitating two dimensional growth. The deposition temperature is kept sufficiently high to enable the indium (In) to undergo absorption and desorption on the gallium nitride (GaN) film without being incorporated into the solid phase gallium nitride (GaN) film. The gallium (Ga) and indium (In) can be provided by a single source or separate sources.

Abstract: A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films.

Abstract: It is an object of the invention to provide a lightweight semiconductor device having a highly reliable sealing structure which can prevent ingress of impurities such as moisture that deteriorate element characteristics, and a method of manufacturing thereof. A protective film having superior gas barrier properties (which is a protective film that is likely to damage an element if the protective film is formed on the element directly) is previously formed on a heat-resistant substrate other than a substrate with the element formed thereon. The protective film is peeled off from the heat-resistant substrate, and transferred over the substrate with the element formed thereon so as to seal the element.

Abstract: Provided are a manufacturing method of a GaN single crystal in which the film thickness of the GaN single crystal can be controlled accurately, even when a hydride vapor phase epitaxy is applied; a GaN thin film template substrate which is suitable for growing a GaN thick film with a fine property; and a GaN single crystal growing apparatus. Provided is a manufacturing method of a GaN single crystal by a hydride vapor phase epitaxy, wherein the hydride vapor phase epitaxy comprises: spraying HCl (hydrogen chloride) onto Ga (gallium) which is heated and fused in a predetermined temperature to generate GaCl (gallium chloride); and forming a GaN thin film by a reaction of the generated GaCl (gallium chloride) with NH3 (ammonia) gas which is hydroxide gas on a substrate, the manufacturing method comprising supplying the NH3 gas in a vicinity of the substrate (for example, at a position which is separated from the substrate by a distance of 0.7-4.

Abstract: A thin film transistor array substrate includes a substrate, a gate layer, a gate insulating layer, a source/drain layer, a patterned protective layer, an oxide semiconductor layer, a resin layer and a pixel electrode. The gate layer is disposed on the substrate. The gate insulating layer is disposed on the gate layer and the substrate. The source/drain layer is disposed on the gate insulating layer. The patterned protective layer is disposed on the source/drain layer and exposes a portion of the source/drain layer. The oxide semiconductor layer is disposed on the patterned protective layer and electrically connected to the source/drain layer. The resin layer is disposed on the oxide semiconductor layer and covers the oxide semiconductor layer. The pixel electrode is disposed on the resin layer and connects to the source/drain layer. The present invention also provides a method for making the thin film transistor array substrate. The thin film transistor array substrate can prevent leakage current.

Abstract: A linear cluster deposition system includes a plurality of reaction chambers positioned in a linear horizontal arrangement. First and second reactant gas manifolds are coupled to respective process gas input port of each of the reaction chambers. An exhaust gas manifold having a plurality of exhaust gas inputs is coupled to the exhaust gas output port of each of the plurality of reaction chambers. A substrate transport vehicle transports at least one of a substrate and a substrate carrier that supports at least one substrate into and out of substrate transfer ports of each of the reaction chambers. At least one of a flow rate of process gas into the process gas input port of each of the reaction chambers and a pressure in each of the reaction chambers being chosen so that process conditions are substantially the same in at least two of the reaction chambers.

Abstract: A two stage plasma etching technique is described that allows the fabrication of an enhancement mode GaN HFET/HEMT. A gate recess area is formed in the Aluminum Gallium Nitride barrier layer of an GaN HFET/HEMT. The gate recess is formed by a two stage etching process. The first stage of the technique uses oxygen to oxidize the surface of the Aluminum Gallium Nitride barrier layer below the gate. Then the second stage uses Boron tricloride to remove the oxidized layer. The result is a self limiting etch process that uniformly thins the Aluminum Gallium Nitride layer below the HFET's gate region such that the two dimensional electron gas is not formed below the gate, thus creating an enhancement mode HFET.

Abstract: A selenium/Group 3a ink, comprising (a) a selenium/Group 3a complex which comprises a combination of, as initial components: a selenium component comprising selenium; an organic chalcogenide component having a formula selected from RZ—Z?R? and R2—SH; wherein Z and Z? are each independently selected from sulfur, selenium and tellurium; wherein R is selected from H, C1-20 alkyl group, a C6-20 aryl group, a C1-20 hydroxyalkyl group, an arylether group and an alkylether group; wherein R? and R2 are selected from a C1-20 alkyl group, a C6-20 aryl group, a C1-20 hydroxyalkyl group, an arylether group and an alkylether group; and, a Group 3a complex, comprising at least one Group 3a material selected from aluminum, indium, gallium and thallium complexed with a multidentate ligand; and, (b) a liquid carrier; wherein the selenium/Group 3a complex is stably dispersed in the liquid carrier.

Abstract: Disclosed is a method of manufacturing a multilayered thin film including a crystalline small molecular organic semiconductor layer and an insulating polymer layer for use in an organic thin film transistor through phase separation and annealing. The method includes applying a blend solution of organic semiconductor and insulating polymer on a substrate thus forming a vertically phase-separated thin film, which is then annealed so that the organic semiconductor contained in the insulating polymer layer is crystallized while being transferred to the surface layer. A high-performance organic thin film transistor fabricated using the same is also provided. The multilayered thin film in which the crystalline organic semiconductor layer is located on the insulating polymer layer through transfer and crystallization of the organic semiconductor can be used to fabricate the high-performance organic thin film transistor.

Abstract: Methods of fabricating semiconductor structures and devices include bonding a seed structure to a substrate using a glass. The seed structure may comprise a crystal of semiconductor material. Thermal treatment of the seed structure bonded to the substrate using the glass may be utilized to control a strain state within the seed structure. The seed structure may be placed in a state of compressive strain at room temperature. The seed structure bonded to the substrate using the glass may be used for growth of semiconductor material, or, in additional methods, a seed structure may be bonded to a first substrate using a glass, thermally treated to control a strain state within the seed structure and a second substrate may be bonded to an opposite side of the seed structure using a non-glassy material.

Abstract: A III-nitride light emitting diode (LED) and method of fabricating the same, wherein at least one surface of a semipolar or nonpolar plane of a III-nitride layer of the LED is textured, thereby forming a textured surface in order to increase light extraction. The texturing may be performed by plasma assisted chemical etching, photolithography followed by etching, or nano-imprinting followed by etching.

Abstract: The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.

Abstract: A method for growing reduced defect density planar gallium nitride (GaN) films is disclosed. The method includes the steps of (a) growing at least one silicon nitride (SiNx) nanomask layer over a GaN template, and (b) growing a thickness of a GaN film on top of the SiNx nanomask layer.

Abstract: Disclosed are organic semiconductor thin films using aromatic enediyne derivatives, manufacturing methods thereof, and methods of fabricating electronic devices incorporating such organic semiconductor thin films. Aromatic enediyne derivatives according to example embodiments provide improved chemical and/or electrical stability which may improve the reliability of the resulting semiconductor devices. Aromatic enediyne derivatives according to example embodiments may also be suitable for deposition on various substrates via solution-based processes, for example, spin coating, at temperatures at or near room temperature to form a coating film that is then heated to form an organic semiconductor thin film. The availability of this reduced temperature processing allows the use of the aromatic enediynes derivatives on large substrate surfaces and/or on substrates not suitable for higher temperature processing.

Abstract: Dibenzorylenetetracarboximides of the general formula I in which the variables are each defined as follows: R? are identical or different radicals: hydrogen; optionally substituted aryloxy, arylthio, hetaryloxy or hetarylthio; R are identical or different radicals: hydrogen; optionally substituted C1-C30-alkyl, C3-C8-cycloalkyl, aryl or hetaryl; m, n are each independently 0 or 1.

Abstract: The present invention provides a method of forming an electrode having reduced corrosion and water decomposition on a surface thereof. A conductive layer is deposited on a substrate. The conductive layer is partially oxidized by an oxygen plasma process to convert a portion thereof to an oxide layer thereby forming the electrode. The oxide layer is free of surface defects and the thickness of the oxide layer is from about 0.09 nm to about 10 nm and ranges therebetween, controllable with 0.2 nm precision.

Abstract: There is provided a process for forming a layer of electroactive material having a substantially flat profile. The process includes: providing a workpiece having at least one active area; depositing a liquid composition including the electroactive material onto the workpiece in the active area, to form a wet layer; treating the wet layer on the workpiece at a controlled temperature in the range of ?25 to 80° C. and under a vacuum in the range of 10?6 to 1,000 Torr, for a first period of 1-100 minutes, to form a partially dried layer; heating the partially dried layer to a temperature above 100° C. for a second period of 1-50 minutes to form a dried layer.

Abstract: The present invention is to provide a method of forming a vertical structure light emitting diode with a heat exhaustion structure. The method includes steps of: a) providing a sapphire substrate; b) depositing a number of protrusions on the sapphire substrate, each of which has a height of p; c) forming a buffer layer having a number of recesses, each of which has a depth of q smaller than p so that when the protrusions are accommodated within the recesses of the buffer layer, a number of gaps are formed therebetween for heat exhaustion; d) growing a number of luminescent layers on the buffer layer, having a medium layer formed between the luminescent layers and the buffer layer; e) etching through the luminescent layers and the buffer layer to form a duct for heat exhaustion; f) removing the sapphire substrate and the protrusions by excimer laser lift-off (LLO); g) roughening the medium layer; and h) depositing electrodes on the roughened medium layer.

Abstract: A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.

Abstract: A selenium/Group 3a ink, comprising (a) a selenium/Group 3a complex which comprises a combination of, as initial components: a selenium component comprising selenium; an organic chalcogenide component having a formula selected from RZ—Z?R? and R2—SH; wherein Z and Z? are each independently selected from sulfur, selenium and tellurium; wherein R is selected from H, C1-20 alkyl group, a C6-20 aryl group, a C1-20 hydroxyalkyl group, an arylether group and an alkylether group; wherein R? and R2 are selected from a C1-20 alkyl group, a C6-20 aryl group, a C1-20 hydroxyalkyl group, an arylether group and an alkylether group; and, a Group 3a complex, comprising at least one Group 3a material selected from aluminum, indium, gallium and thallium complexed with a multidentate ligand; and, (b) a liquid carrier; wherein the selenium/Group 3a complex is stably dispersed in the liquid carrier.

Abstract: The invention relates to a method for producing semiconductor components, wherein a layer composite (6) containing a semiconductor material is formed on a growth substrate (1), a flexible carrier layer is applied to the layer composite (6), the flexible carrier layer is cured to form a self-supporting carrier layer (2), and the growth substrate (1) is stripped away. As an alternative, the carrier layer (2) may have a base layer (2b) and an adhesion layer (2a) adhering on the layer composite.

Abstract: In a method of forming a phase-change memory unit, a conductive layer is formed on a substrate having a trench. The conductive layer is planarized until the substrate is exposed to form a first electrode. A spacer partially covering the first electrode is formed. A phase-change material layer is formed on the first electrode and the second spacer. A second electrode is formed on the phase-change material layer. Reset/set currents of the phase-change memory unit may be reduced and deterioration of the phase-change material layer may be reduced and/or prevented.

Abstract: In formation of a quantum dot structure in a light emitting layer, a matrix region (an n-type conductive layer and matrix layers) is formed on a growth underlying layer of AlN whose abundance ratio of Al is higher (or whose lattice constant is smaller) than that in the matrix region by an MBE technique, thereby to realize conditions where compression stress is caused in an in-plane direction perpendicular to the direction of growth of the matrix region, and then to form island crystals by self-organization in the presence of this compression stress. The compression stress inhibits an increase in lattice constant caused by the reduced abundance ratio of Al in the matrix region, i.e., to compensate for a difference in lattice constant between the island crystals and the matrix region. The compression stress functions to enlarge compositional limits for formation of the island crystals by self-organization to the Ga-rich side.

Abstract: A semiconductor-on-insulator hetero-structure and a method for fabricating the semiconductor -on-insulator hetero-structure include a crystalline substrate and a dielectric layer located thereupon having an aperture that exposes the crystalline substrate. The semiconductor-on -insulator hetero-structure and the method for fabricating the semiconductor-on-insulator hetero-structure also include a semiconductor layer of composition different than the crystalline substrate located within the aperture and upon the dielectric layer. A portion of the semiconductor layer located aligned over the aperture includes a defect. A portion of the semiconductor layer located aligned over the dielectric layer does not include a defect. Upon removing the portion of the semiconductor layer located aligned over the aperture a reduced defect semiconductor-on-insulator hetero-structure is formed.

Abstract: Monolithic electronic devices are providing including a high bandgap layer. A first type of nitride device is provided on a first portion of the high bandgap layer, the first nitride device including first and second implanted regions respectively defining source and drain regions of the first type of nitride device. A second type of nitride device, different from the first type of nitride device, is provided on a second portion of the high bandgap layer, the second type of nitride device including an implanted highly conductive region. At least a portion of the implanted highly conductive region of the second type of nitride device is coplanar with at least a portion of both the first and second implanted regions of the first type of nitride device.

Abstract: Provided is a method of forming a compound semiconductor device. In the method, a dopant element layer is formed on an undoped compound semiconductor layer. An annealing process is performed to diffuse dopants in the dopant element layer into the undoped compound semiconductor layer, thereby forming a dopant diffusion region. A rapid cooling process is performed using liquid nitrogen with respect to the substrate having the dopant diffusion region.

Abstract: A thin film transistor (TFT) and a method of manufacturing the same are provided. The TFT includes a transparent substrate, an insulating layer on a region of the transparent substrate, a monocrystalline silicon layer, which includes source, drain, and channel regions, on the insulating layer and a gate insulating film and a gate electrode on the channel region of the monocrystalline silicon layer.

Abstract: The present teachings provide novel organic semiconductor compounds and their soluble precursors, methods for preparing these compounds and precursors, as well as compositions, materials, articles, structures, and devices that incorporate such compounds.

Abstract: In a manufacturing flow for adapting the band gap of the semiconductor material with respect to the work function of a metal-containing gate electrode material, a strain-inducing material may be deposited to provide an additional strain component in the channel region. For instance, a layer stack with silicon/carbon, silicon and silicon/germanium may be used for providing the desired threshold voltage for a metal gate while also providing compressive strain in the channel region.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device, wherein an amorphous semiconductor film comprising a microcrystal is annealed using a microwave, to crystallize the amorphous semiconductor film comprising the microcrystal using the microcrystal as a nucleus.

Abstract: A process for coating a substrate heated to a temperature below the condensation temperature of a semiconductor material at atmospheric pressure is disclosed, the process including the steps of mixing a mass of semiconductor material and a heated inert gas stream, vaporizing the controlled mass of semiconductor material within the inert gas to generate a sub-saturated fluid mixture, directing the sub-saturated fluid mixture at the substrate, wherein the substrate is at substantially atmospheric pressure, depositing a layer of the semiconductor material onto a surface of the substrate, extracting undeposited semiconductor material, and repeating the steps of generating, directing, depositing, and extracting, to minimize an amount of undeposited semiconductor material.

Abstract: A nitride semiconductor includes: a substrate having a major surface including a first crystal polarity surface and a second crystal polarity surface different from the first crystal polarity surface; and a single polarity layer provided above the major surface and having a single crystal polarity.

Abstract: Semiconductor process technology and devices are provided, including a method for forming a high quality group III nitride layer on a silicon substrate and to a device obtainable therefrom. According to the method, a pre-dosing step is applied to a silicon substrate, wherein the substrate is exposed to at least 0.01 ?mol/cm2 of one or more organometallic compounds containing Al, in a flow of less than 5 ?mol/min. The preferred embodiments are equally related to the semiconductor structure obtained by the method, and to a device comprising said structure.

Abstract: Mono- and diimide perylene and naphthalene compounds, N- and/or core-substituted with electron-withdrawing groups, for use in the fabrication of various device structures.

Abstract: According to a method of fabricating an oxide thin-film transistor, when a thin-film transistor is fabricated by using an amorphous zinc oxide (ZnO)-based semiconductor as an active layer, it may be possible to reduce a tact time as well as attain an enhanced element characteristic by depositing an insulation layer having an oxide characteristic in-situ through controlling oxygen (O2) flow subsequent to depositing an oxide semiconductor using a sputter, and the method may include the steps of forming a gate electrode on a substrate; forming a gate insulation layer on the substrate; depositing an amorphous zinc oxide-based semiconductor layer made of an amorphous zinc oxide-based semiconductor and an amorphous zinc oxide-based insulation layer having an oxide characteristic in-situ on the gate insulation layer; forming an active layer made of the amorphous zinc oxide-based semiconductor over the gate electrode while at the same time forming a channel protection layer made of the amorphous zinc oxide-based insu

Abstract: In one embodiment the present invention is a method of conducting multiple step multiple chamber chemical vapor deposition while avoiding reactant memory in the relevant reaction chambers. The method includes depositing a layer of semiconductor material on a substrate using vapor deposition in a first deposition chamber followed by evacuation of the growth chamber to reduce vapor deposition source gases remaining in the first deposition chamber after the deposition growth and prior to opening the chamber. The substrate is transferred to a second deposition chamber while isolating the first deposition chamber from the second deposition chamber to prevent reactants present in the first chamber from affecting deposition in the second chamber and while maintaining an ambient that minimizes or eliminates growth stop effects. After the transferring step, an additional layer of a different semiconductor material is deposited on the first deposited layer in the second chamber using vapor deposition.