Abstract: The invention provides a method for activating impurity element added to a semiconductor and performing gettering process in shirt time, and a thermal treatment equipment enabling to perform such the heat-treating.

Abstract: A method and device structure are disclosed for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET. The ESD protection module has a low temperature oxide (LTO) bottom layer whose patterning process is found to cause the gate oxide damage. The method includes: a) Fabricate numerous trench MOSFETs on a wafer. b) Add a Si3N4 isolation layer, capable of preventing the LTO patterning process from damaging the gate oxide, atop the wafer. c) Add numerous ESD protection modules atop the Si3N4 isolation layer. d) Remove those portions of the Si3N4 isolation layer that are not beneath the ESD protection modules. In one embodiment, hydrofluoric acid is used as a first etchant for patterning the LTO while hot phosphoric acid is used as a second etchant for removing portions of the Si3N4 isolation layer.

Abstract: LED epitaxial layers (n-type, p-type, and active layers) are grown on a substrate. For each die, the n and p layers are electrically bonded to a package substrate that extends beyond the boundaries of the LED die such that the LED layers are between the package substrate and the growth substrate. The package substrate provides electrical contacts and conductors leading to solderable package connections. The growth substrate is then removed. Because the delicate LED layers were bonded to the package substrate while attached to the growth substrate, no intermediate support substrate for the LED layers is needed. The relatively thick LED epitaxial layer that was adjacent the removed growth substrate is then thinned and its top surface processed to incorporate light extraction features.

Abstract: A method of depositing a high quality low defect single crystalline Group III-Nitride film. A patterned substrate having a plurality of features with inclined sidewalls separated by spaces is provided. A Group III-Nitride film is deposited by a hydride vapor phase epitaxy (HVPE) process over the patterned substrate. The HVPE deposition process forms a Group III-Nitride film having a first crystal orientation in the spaces between features and a second different crystal orientation on the inclined sidewalls. The first crystal orientation in the spaces subsequently overgrows the second crystal orientation on the sidewalls and in the process turns over and terminates treading dislocations formed in the first crystal orientation.

Abstract: Disclosed is a method for growing a microcrystalline silicon film on a substrate. The method includes the step of disposing the substrate in a chamber, the step of vacuuming the chamber and heating the substrate, the step of introducing reacting gas into the chamber as a precursor and keeping the pressure in the chamber at a predetermined value and the step of using RF energy in the chamber to dissociate the reacting gas to form plasma for growing the microcrystalline silicon film on the substrate. The reacting gas includes SiH4/Ar mixture and H2. The ratio of SiH4/Ar mixture over H2 is 1:1 to 1:20.

Abstract: A method of making a crystalline semiconductor structure provides a photonic device by employing low thermal budget annealing process. The method includes annealing a non-single crystal semiconductor film formed on a substrate to form a polycrystalline layer that includes a transition region adjacent to a surface of the film and a relatively thicker columnar region between the transition region and the substrate. The transition region includes small grains with random grain boundaries. The columnar region includes relatively larger columnar grains with substantially parallel grain boundaries that are substantially perpendicular to the substrate. The method further includes etching the surface to expose the columnar region having an irregular serrated surface.

Abstract: Hybrid semiconductor devices including a PIN diode portion and a Schottky diode portion are provided. The PIN diode portion is provided on a semiconductor substrate and has an anode contact on a first surface of the semiconductor substrate. The Schottky diode portion is also provided on the semiconductor substrate and includes a polysilicon layer on the semiconductor substrate and a ohmic contact on the polysilicon layer. Related Schottky diodes are also provided herein.

Abstract: A method of forming a semiconductor structure includes providing a substrate and providing a detach region which is carried by the substrate. A device structure which includes a stack of crystalline semiconductor layers is provided, wherein the detach region is positioned between the device structure and substrate. The stack is processed to form a vertically oriented semiconductor device.

Abstract: Exact alignment of a recrystallized region, which is to be formed in an amorphous or polycrystalline film, is facilitated. An alignment mark is formed, which is usable in a step of forming an electronic device, such as a thin-film transistor, in the recrystallized region. In addition, in a step of obtaining a large-grain-sized crystal-phase semiconductor from a semiconductor film, a mark structure that is usable as an alignment mark in a subsequent step is formed on the semiconductor film in the same exposure step. Thus, the invention includes a light intensity modulation structure that modulates light and forms a light intensity distribution for crystallization, and a mark forming structure that modulates light and forms a light intensity distribution including a pattern with a predetermined shape, and also forms a mark indicative of a predetermined position on a crystallized region.

Abstract: A method for fabricating a copper-indium-gallium-diselenide (CIGS) compound thin film is provided. In this method, a substrate is first provided. An adhesive layer is formed over the substrate. A metal electrode layer is formed over the adhesive layer. A precursor stacked layer is formed over the metal electrode layer, wherein the precursor stacked layer includes a plurality of copper-gallium (CuGa) alloy layers and at least one copper-indium (CuIn) alloy layer sandwiched between the plurality of CuGa alloy layers. An annealing process is performed to convert the precursor stacked layer into a copper-indium-gallium (CuInGa) alloy layer. A selenization process is performed to convert the CuInGa alloy layer into a copper-indium-gallium-diselenide (CuInGaSe) compound thin film.

Abstract: The invention provides a memory cell based on variable resistance material memory element that includes an access device having a pillar structure that may also include a protective sidewall layer. The pillar access device selects and isolates the memory cell from other memory array cells and is adapted to both self-align any memory element formed thereon, and to deliver suitable programming current to the memory element. The pillar structure is formed from one or more access device layers stacked above a wordline and below the memory element. Optional resistive layers may be selectively formed within the pillar structure to minimize resistance in the access device layer and the memory element. The pillar access device may be a diode, transistor, Ovonic threshold switch or other device capable of regulating current flow to an overlying programmable memory material.

Abstract: The invention relates to a method for simultaneous recrystallization and doping of semiconductor layers, in particular for the production of crystalline silicon thin layer solar cells. In this method, in a first step a substrate base layer 1 is produced, in a step subsequent thereto, on the latter an intermediate layer system 2 which has at least one doped partial layer is deposited, in a step subsequent thereto, an absorber layer 3 which is undoped or likewise doped is deposited on the intermediate layer system 2, and in a recrystallization step, the absorber layer 3 is heated, melted, cooled and tempered. In an advantageous method modification, instead of an undoped capping layer, a capping layer system 4 which has at least one partial layer can also be applied on the absorber layer 3.

Abstract: In embodiments of the invention, a method of forming a monolithic three-dimensional memory array is provided, the method including forming a first memory level that includes a plurality of memory cells, each memory cell comprising a plurality of conductors comprising aluminum or copper, and forming a silicon diode in each memory cell, wherein the silicon diode is formed at temperatures compatible with the conductors. The silicon diode may be formed using a hot wire chemical vapor deposition technique, for example. Other aspects are also described.

Abstract: The present invention in one preferred embodiment discloses a new design of HVPE reactor, which can grow gallium nitride for more than one day without interruption. To avoid clogging in the exhaust system, a second reactor chamber is added after a main reactor where GaN is produced. The second reactor chamber may be configured to enhance ammonium chloride formation, and the powder may be collected efficiently in it. To avoid ammonium chloride formation in the main reactor, the connection between the main reactor and the second reaction chamber can be maintained at elevated temperature. In addition, the second reactor chamber may have two or more exhaust lines. If one exhaust line becomes clogged with powder, the valve for an alternative exhaust line may open and the valve for the clogged line may be closed to avoid overpressuring the system. The quartz-made main reactor may have e.g. a pyrolytic boron nitride liner to collect polycrystalline gallium nitride efficiently.

Abstract: Chemical vapor deposition methods use trisilane and a halogen-containing etchant source (such as chlorine) to selectively deposit Si-containing films over selected regions of mixed substrates. Dopant sources may be intermixed with the trisilane and the etchant source to selectively deposit doped Si-containing films. The selective deposition methods are useful in a variety of applications, such as semiconductor manufacturing.

Abstract: A method for an intrinsic type microcrystalline silicon layer is provided. In one embodiment, the microcrystalline silicon layer is fabricated by providing a substrate into a processing chamber, supplying a gas mixture into the processing chamber, applying a RF power at a first mode in the gas mixture, pulsing the gas mixture into the processing chamber, and applying the RF power at a second mode in the pulsed gas mixture.

Abstract: A layer including a semiconductor film is formed over a glass substrate and is heated. A thermal expansion coefficient of the glass substrate is greater than 6×10?7/° C. and less than or equal to 38×10?7/° C. The heated layer including the semiconductor film is irradiated with a pulsed ultraviolet laser beam having a width of less than or equal to 100 ?m, a ratio of width to length of 1:500 or more, and a full width at half maximum of the laser beam profile of less than or equal to 50 ?m, so that a crystalline semiconductor film is formed. As the layer including the semiconductor film formed over the glass substrate, a layer whose total stress after heating is ?500 N/m to +50 N/m, inclusive is formed.

Abstract: In crystallization of a silicon film by annealing using a linear-shaped laser beam having a width of the short axis of the beam is ununiform, the profile (intensity distribution) of the laser beam is evaluated and the results are fed back to a condition of oscillating the laser beam or an optical condition for projecting the laser beam onto the silicon film, whereby a display device comprising a high-quality crystalline silicon film is manufactured.

Abstract: A number of methods are provided for semiconductor processing. One such method includes depositing a first precursor material on a surface at a particular temperature to form an undoped polysilicon. The method also includes depositing a second precursor material on a surface of the undoped polysilicon at substantially the same temperature, wherein the undoped polysilicon serves as a seed to accelerate forming a doped polysilicon.

Abstract: A switching element for a memory device includes a base layer including a plurality of line-type trenches. First insulation patterns are formed on the base layer excluding the trenches. First diode portions are formed on the bottoms of the trenches in the form of a thin film. Second insulation patterns are formed on the first diode portions and are spaced apart from each other to form holes in the trenches having the first diode portions provided therein. Square pillar-shaped second diode portions are formed in the holes over the first diode portions.

Abstract: The invention relates to an electronic device comprising a sequence of a first thin film transistor (TFT) and a second TFT, the first TFT comprising a first set of electrodes separated by a first insulator, the second TFT comprising a second set of electrodes separated by a second insulator, wherein the first set of electrodes and the second set of electrodes are formed from a first shared conductive layer and a second shared conductive layer, the first insulator and the second insulator being formed by a shared dielectric layer. The invention further relates to a method of manufacturing an electronic device.

Abstract: A semiconductor component is provided having a substrate and at least one semiconductor layer realized to be polycrystalline on one side of the substrate. The polycrystalline semiconductor layer contains the crystal nuclei.

Abstract: A crystalline semiconductor film is manufactured by a first step in which a crystalline semiconductor film is formed on and in contact with an insulating film and a second step in which the crystalline semiconductor film is grown in a condition where a generation frequency of nuclei is lower than in the first step. The second step is conducted in a condition where a flow ratio of a semiconductor material gas to a deposition gas is lower than in the first step. Thus, a crystalline semiconductor film whose crystal grains are large and uniform can be obtained and plasma damage to a base film of the crystalline semiconductor film can be reduced compared with a crystalline semiconductor film in a conventional method.

Abstract: In a photovoltaic cell, an i-type amorphous silicon film and an n-type amorphous silicon film are formed in a region excluding a predetermined width of an outer periphery on a main surface of an n-type single crystalline silicon substrate. A front electrode is formed so as to cover the i-type amorphous silicon film and the n-type amorphous silicon film on a main surface of the n-type single crystalline silicon substrate. An i-type amorphous silicon film and a p-type amorphous silicon film are formed on the entire area of a back surface of the n-type single crystalline silicon substrate. A back electrode is formed in a region excluding a predetermined width of an outer periphery on the p-type amorphous silicon film. A surface, on the side of the front electrode, of the photovoltaic cell is a primary light incidence surface.

Abstract: In the method for forming a silicon-based thin film by the plasma CVD method using high-frequency excitation, a polycrystalline silicon-based thin film having high degree of crystallization is formed relatively at a low temperature, economically, and productively. The polycrystalline silicon-based thin film is formed in such a state that the pressure of gas during formation of the film is selected and determined from the range of 0.0095 Pa to 64 Pa; the ratio (Md/Ms) of a supply flow rate Md of a diluting gas to a supply flow rate Ms of a film-forming material gas introduced into a deposition chamber is selected and determined from the range of 0 to 1200; the high-frequency power density is selected and determined from the range of 0.

Abstract: A method for reclaiming a surface of a substrate, wherein the surface, in particular a silicon surface, comprises a protruding residual topography, comprising at least the layer of a first material. By providing a filling material in the non-protruding areas of the surface of the substrate and the subsequent polishing, the reclaiming can be carried out such that the material consuming double-sided polishing step used in the prior art is no longer necessary.

Abstract: The semiconductor device, which provides reduced electric current leakage and parasitic resistance to achieve stable current gain, is provided. A first polycrystalline semiconductor layer is grown on a p-type polycrystalline silicon film exposed in a lower surface of a visor section composed of a multiple-layered film containing a p-type polycrystalline silicon film and a silicon nitride film, while growing the first semiconductor layer on a n-type collector layer, and then the first polycrystalline semiconductor layer is selectively removed.

Abstract: A method of crystallizing amorphous silicon includes forming an amorphous silicon film over a substrate, crystallizing the amorphous silicon film to form a polycrystalline silicon film using a sequential lateral solidification crystallization method, and performing a surface treatment to the polycrystalline silicon film, wherein the sequential lateral solidification crystallization method includes at least a first application of a first laser beam having a first energy density that completely melts a first uncrystallized portion of the amorphous silicon film and melts a first crystallized portion of the amorphous silicon film, and the surface treatment includes application of a second laser beam having a second energy density that partially melts an entire surface of the polycrystalline silicon film.

Abstract: A polycrystalline silicon thin film to be used in display devices, the thin film having adjacent primary grain boundaries that are not parallel to each other, wherein an area surrounded by the primary grain boundaries is larger than 1 ?m2, a fabrication method of the polycrystalline silicon thin film, and a thin film transistor fabricated using the method.

Abstract: A low temperature polycrystalline silicon device and techniques to manufacture thereof with excellent performance. Employing doped poly-Si lines which we called a bridged-grain structure (BG), the intrinsic or lightly doped channel is separated into multiple regions. A single gate covering the entire active channel including the doped lines is still used to control the current flow. Using this BG poly-Si as an active layer and making sure the TFT is designed so that the current flows perpendicularly to the parallel lines of grains, grain boundary effects can be reduced. Reliability, uniformity and the electrical performance of the BG poly-Si TFT are significantly improved compared with the conventional low temperature poly-Si TFT.

Abstract: In a vertical diode, an N+-type layer, an N?-type layer, and a P+-type layer are stacked in this order on a lower electrode film, and an upper electrode film is provided thereon. The effective impurity concentration of the N?-type layer is lower than the effective impurity concentrations of the N+-type layer and the P+-type layer. At least one of the N+-type layer, the N?-type layer, and the P+-type layer is formed from a small grain size polycrystalline semiconductor whose each crystal grain does not penetrate each layer through its thickness.

Abstract: A solid-phase sheet growing substrate (100) includes a main surface (1) and a side surface (2A, 2B) surrounding the main surface (1). The main surface (1) is divided by a peripheral groove (10A) into a surrounding portion (12) located at the outer side of the peripheral groove (10A) and an inner portion (11) located at the inner side of the peripheral groove (10A), and a slit groove (2) separated from the peripheral groove (10A) is formed on the side surface (2A) of the surrounding portion (12).

Abstract: The invention provides compounds of, and methods for the preparation of compounds of, the molecular formula, SixGeyHz—aXa; wherein X is halogen, and x, y, z, and a are defined herein, and methods for the deposition of high-Ge content Si films on silicon substrates using compounds of the invention.

Abstract: Affords GaN epitaxial wafers designed to improve production yields, as well as semiconductor devices utilizing such GaN epitaxial wafers, and methods of manufacturing such GaN epitaxial wafers and semiconductor devices. A GaN epitaxial wafer manufacturing method involving the present invention includes a first GaN layer formation step of epitaxially growing a first GaN layer onto a substrate, a pit formation step, following the first GaN layer formation step, of forming pits in the front side of the substrate, and a second GaN layer formation step, following the pit-formation step, of epitaxially growing a second GaN layer onto the first GaN layer, and therefore controls cracking to a minimum and improves production yields.

Abstract: A method for forming a semiconductor device includes providing a substrate having at least a gate positioned thereon, forming at least a recess in the substrate adjacent to the gate, performing a first selective epitaxial growth (SEG) process to form a first epitaxial layer in the recess, performing an etching process to remove a portion of the first epitaxial layer to expose the substrate, and performing a second SEG process to form a second epitaxial layer on the first epitaxial layer.

Abstract: Disclosed is a method of manufacturing crystalline Si by using plasma. According to the disclosed method, silicon (Si) deposition and reduction processes using plasma are cyclically performed in order to completely remove an a-Si layer so as to form crystalline Si on a substrate early in the process.

Abstract: The present invention relates to an optical device and to a method of fabricating the same. In embodiments, the invention relates to a photovoltaic device or solar cell. The optical device comprises a first electrode and a second electrode and an active element disposed between the first and second electrodes. The active element comprising a plurality of semiconducting structures extending in a lengthwise direction from the first electrode and being in contact with the first and second electrodes; the active element comprises an np-junction. For the semiconducting structures, at least a part of the structures is of a general plate or flake shape. In embodiments, the semiconducting structures have at least one characteristic dimension in the nanometer range.

Abstract: A method of programming a carbon nanotube memory cell is provided, wherein the memory cell comprises a first conductor, a steering element, a carbon nanotube fabric, and a second conductor, wherein the steering element and the carbon nanotube fabric are arranged electrically in series between the first conductor and the second conductor, and wherein the entire carbon nanotube memory cell is formed above a substrate, the carbon nanotube fabric having a first resistivity, the method including applying a first electrical set pulse between the first conductor and the second conductor, wherein, after application of the first electrical set pulse, the carbon nanotube fabric has a second resistivity, the second resistivity less than the first resistivity. Other aspects are also provided.

Abstract: In a first aspect, a method of forming an epitaxial film on a substrate is provided. The method includes (a) providing a substrate; (b) exposing the substrate to a silicon source and a carbon source so as to form a carbon-containing silicon epitaxial film; (c) encapsulating the carbon-containing silicon epitaxial film with an encapsulating film; and (d) exposing the substrate to Cl2 so as to etch the encapsulating film. Numerous other aspects are provided.

Abstract: A method of preventing the escape of nitrogen during the activation of ion implanted dopants in a Group III-nitride semiconductor compound without damaging the Group III-nitride semiconductor comprising: depositing a first layer of another Group III-nitride that acts as an adhesion layer; depositing a second layer of a Group III-nitride that acts as a mechanical supporting layer; said first and second layers forming an annealing cap to prevent the escape of the nitrogen component of the Group III-nitride semiconductor; annealing the Group III-nitride semiconductor at a temperature in the range of approximately 1100-1250° C.; and removing the first and second layers from the Group III-nitride semiconductor.

Abstract: A method of surface treatment for silicon material. The method includes providing a first silicon material having a surface region. The first silicon material has a first purity characteristics and a first surface roughness characteristics. A chemical polishing process is perform to the surface region to cause the surface region to have a second roughness characteristics. Thereafter, a chemical leaching process is performed to the surface region to cause the first silicon material in a depth within a vicinity of the surface region to have a second purity characteristics. A polysilicon material characterized by a grain size greater than about 0.1 mm is formed using a deposition process overlying the surface region.

Abstract: An integrated circuit with stacked devices. One embodiment provides a surface of a first semiconductor structure of a first crystalline semiconductor material including first and second portions. First structures are formed on the first portions. The second portions remain uncovered. Sacrificial structures of a second, different crystalline material are formed on the second portions. A second semiconductor structure of the first crystalline semiconductor material is formed over the sacrificial structures and over the first structures.

Abstract: A doped silicon layer is formed in a batch process chamber at low temperatures. The silicon precursor for the silicon layer formation is a polysilane, such as trisilane, and the dopant precursor is an n-type dopant, such as phosphine. The silicon precursor can be flowed into the process chamber with the flow of the dopant precursor or separately from the flow of the dopant precursor. Surprisingly, deposition rate is independent of dopant precursor flow, while dopant incorporation linearly increases with the dopant precursor flow.

Abstract: A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor plug having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn junction between the first and second regions.

Abstract: A gate electrode structure of a transistor may be formed so as to exhibit a high crystalline quality at the interface formed with a gate dielectric material, while upper portions of the gate electrode may have an inferior crystalline quality. In a later manufacturing stage after implementing one or more strain-inducing mechanisms, the gate electrode may be re-crystallized, thereby providing increased stress transfer efficiency, which in turn results in an enhanced transistor performance.

Abstract: The invention relates to a method and device for depositing at least one layer, particularly a semiconductor layer, onto at least one substrate, which is situated inside a process chamber of a reactor while being supported by a substrate holder. The layer is comprised of at least two material components provided in a fixed stoichiometric ratio, which are each introduced into the reactor in the form of a first and a second reaction gas, and a portion of the decomposition products form the layer, whereby the supply of the first reaction gas, which has a low thermal activation energy, determines the growth rate of the layer, and the second reaction gas, which has a high thermal activation energy, is supplied in excess and is preconditioned, in particular, by an independent supply of energy. The first reaction gas flows in a direction toward the substrate holder through a multitude of openings, which are distributed over a surface of a gas inlet element, said surface being located opposite the substrate holder.

Abstract: A method of forming a crystalline silicon layer on a microrough face of a substrate by reducing the microroughness of the face and then performing a metal induced crystallization process on the face is disclosed. The method further comprises, after metal induced crystallization and before removing the metal layer, removing silicon islands using the metal layer as a mask.

Abstract: A bottom-gate thin film transistor includes a gate electrode, a gate insulating layer and a microcrystalline silicon layer. The gate electrode is disposed on a substrate. The gate insulating layer is made up of silicon nitride and disposed on the gate electrode and the substrate. The microcrystalline silicon layer is disposed on the gate insulating layer and corresponds to the gate electrode, in which a contact interface between the gate insulating layer and the microcrystalline silicon layer has a plurality of oxygen atoms, and concentration of the oxygen atoms ranges between 1020 atoms/cm3 and 1025 atoms/cm3. A method of fabricating a bottom-gate thin film transistor is also disclosed herein.

Abstract: A metallic element is effectively removed from a semiconductor film crystallized by using the metallic element. The concentration distribution of phosphorous or antimony in the depth direction of at least one of a source and a drain of a TFT semiconductor film has: a region in which the concentration is 1×1020 atoms/cm3 or less is 5 nm or greater in thickness, and 5×1019 atoms/cm3 or greater in the maximum value. By creating this concentration distribution, and by thermal annealing at about between 500 and 650° C., the metallic element within a channel forming region diffuses to the source or the drain, and at the same time as gettering is accomplished, the region in which the concentration is 1×1020 atoms/cm3 or less is made into a nucleus and the source region/drain region is recrystallized.

Abstract: A method of manufacturing a silicon layer includes pretreating a surface of a silicon nitride layer formed on a substrate through a plasma enhanced chemical vapor deposition method using a first reaction gas including at least one of silicone tetrafluoride (SiF4) gas, a nitrogen trifluoride (NF3) gas, SiF4—H2 gas and a mixture thereof. Then, a silicon layer is formed on the pretreated silicon nitride layer through the plasma enhanced chemical vapor deposition method using a second reaction gas including a mixture of gas including silicon tetrafluoride (SiF4), hydrogen (H2) and argon (Ar).