Abstract: A process for reconditioning a multi-component electrode comprising a silicon electrode bonded to an electrically conductive backing plate is provided. The process comprises: (i) removing metal ions from the multi-component electrode by soaking the multi-component electrode in a substantially alcohol-free DSP solution comprising sulfuric acid, hydrogen peroxide, and water and rinsing the multi-component electrode with de-ionized water; (ii) polishing one or more surfaces of the multi-component electrode following removal of metal ions there from; and (iii) removing contaminants from silicon surfaces of the multi-component electrode by treating the polished multi-component electrode with a mixed acid solution comprising hydrofluoric acid, nitric acid, acetic acid, and water and by rinsing the treated multi-component electrode with de-ionized water. Additional embodiments of broader and narrower scope are contemplated.

Abstract: A semiconductor device includes a wafer having a first surface opposite a second surface, and at least one laser irradiated region between the first and second surfaces. The laser irradiated region includes a laser-induced stress that is configured to minimize curvature of at least one of the first and second surfaces.

Abstract: An apparatus and a method for packaging semiconductor devices. The apparatus is a three-dimensional electronic package comprising one or more electronic components, a plurality of electrical contact pads, and a plurality of electrically conductive three-dimensional plugs formed through an encapsulant. Specific ones of the plurality of electrical contact pads are electrically coupled to the one or more electronic components on an uppermost surface of the plurality of electrical contact pads. The encapsulant is formed over and covers the one or more electronic devices. The plurality of three-dimensional plugs have a first end extending from at least the uppermost portion of one or more of the plurality of electrical contact pads and a second end extending substantially to an uppermost surface of the encapsulant.

Abstract: Method for conversion of a Flash memory cell on a first semiconductor device to a ROM memory cell in a second semiconductor device, the first and second semiconductor device each being arranged on a semiconductor substrate and each comprising an identical device portion and an identical wiring scheme for wiring the device portion to the Flash memory cell and to the ROM memory cell, respectively; the Flash memory cell being made in non-volatile memory technology and comprising an access transistor and a floating transistor, the floating transistor comprising a floating gate and a control gate; the ROM memory cell being made in a baseline technology and comprising a single gate transistor, which method includes manipulating a layout of at least one baseline mask as used in the baseline technology; the manipulation including: incorporating into the layout of the at least one baseline mask a layout of the Flash memory cell, and converting the layout of the Flash memory cell to a layout of one ROM memory cell by e

Abstract: A method of reworking a chip includes providing a first chip and a second chip. The first and second chips have at least one first module and at least one second module, respectively. The first and second modules electrically connect with each other. The first module of the first chip has a defect. The second module of the second chip has a defect. The first module having a defect of the first chip is opened with the second module of the first chip, and the second module having a defect of the second chip is opened with the first module of the second chip. The first and second chips are stacked, and the second module of the first chip is electrically connects with the first module of the second chip.

Abstract: A method of reversing Shockley stacking fault expansion includes providing a bipolar or a unipolar SiC device exhibiting forward voltage drift caused by Shockley stacking fault nucleation and expansion. The SiC device is heated to a temperature above 150° C. A current is passed via forward bias operation through the SiC device sufficient to induce at least a partial recovery of the forward bias drift.

Abstract: A fuse part in a semiconductor device has a plurality of fuse lines extended along a first direction with a given width along a second direction. The fuse part includes a first conductive pattern having a space part formed in a fuse line region over a substrate, wherein portions of the first conductive pattern are spaced apart by the space part along the first direction. The fuse part includes a first insulation pattern formed over the space part, the first insulation pattern having a width smaller than a width of the first conductive pattern along the second direction and a thickness greater than a thickness of the first conductive pattern, and a second conductive pattern formed over the first insulation pattern, the second conductive pattern having a width greater than the width of the first insulation pattern along the second direction.

Abstract: A thin-film transistor substrate includes; gate lines which extend in a first direction, the gate lines including a first gate line and a second gate line, the first gate line disposed adjacent to and previous to the second gate line, data lines which are insulated from the gate lines and extend in a second direction perpendicular to the first direction, a pixel electrode formed in a region where the first gate line and the second gate lines cross the data lines and connected to the second gate line, and a repair pattern which at least partially overlaps the first gate line, the repair pattern comprising a plurality of connection patterns, wherein the connection patterns extend from the pixel electrode in the second direction toward the first gate line, have a predetermined width measured in the first direction, and are arranged at predetermined intervals along the first direction.

Abstract: Disclosed herein are methods and systems for testing the electrical characteristics of reflective displays, including interferometric modulator displays. In one embodiment, a controlled voltage is applied to conductive leads in the display and the resulting current is measured. The voltage may be controlled so as to ensure that interferometric modulators do not actuate during the resistance measurements. Also disclosed are methods for conditioning interferometric modulator display by applying a voltage waveform that causes actuation of interferometric modulators in the display.

Abstract: A thin film transistor substrate includes: a substrate; a thin film transistor and a capacitor formed on the substrate; and a protective film for protecting an electrode on a back surface side of the capacitor when an electrode on a front surface side of the capacitor is cut by irradiation with laser light, the protective film being disposed at such a position as to enclose a corner part of the electrode on the front surface side between the electrode on the front surface side and the electrode on the back surface side of the capacitor.

Abstract: A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is injected from a substrate to a gate region to neutralize charge in the gate region. The method is applicable to CMOS devices. Repair circuits are disclosed for implementing the repairs.

Abstract: Methods and reworked intermediate and resultant electronic modules made thereby, whereby a component in need of rework is located and removed from the module to reveal encapsulated solder connections residing within an underfill matrix. Heights of both the solder connections and underfill matrix are reduced, followed by etching the solder out of the solder connections to form openings within the underfill matrix. The underfill material is then removed to expose metallurgy of the substrate. A blank having a release layer with an array of solder connections is aligned with the exposed metallurgy, and this solder array is transferred from the blank onto the metallurgy. The transferred solder connections are then flattened using heat and pressure, followed by attaching solder connections of a new component to the flattened solder connections and underfilling these reworked solder connections residing between the new chip and substrate.

Abstract: Disclosed are embodiments of a semiconductor chip structure and a method that incorporate a localized, on-chip, repair scheme for devices that exhibit performance degradation as a result of negative bias temperature instability (NBTI). The repair scheme utilizes a heating element above each device. The heating element is configured so that it can receive transmission line pulses and, thereby generate enough heat to raise the adjacent device to a temperature sufficient to allow for performance recovery. Specifically, high temperatures (e.g., between approximately 300-400° C. or greater) in the absence of bias can accelerate the recovery process to a matter of seconds as opposed to days or months. The heating element can be activated, for example, on demand, according to a pre-set service schedule, and/or in response to feedback from a device performance monitor.

Abstract: A damaged layer repairing method repairs a damaged layer formed in a surface of a SiOCH film having a low dielectric constant film, containing silicon, carbon, oxygen and hydrogen and formed on a substrate through the elimination of carbon atoms by the decarbonizing effect of plasmas used in an etching process and an ashing process. CH3 radicals are produced through the thermal decomposition of C8H18O2 gas represented by a structural formula: (CH3)3COOH(CH3)3. CH3 radicals are brought into contact with the damaged layer in the SiOCH film and are made to bond to the damaged layer to repair the damaged layer.

Abstract: The present invention provides a method of manufacturing an organic light-emitting device which is applicable to a large-screen display device. The method includes the steps of: forming, over a drive substrate, an element region including a drive transistor, and an organic electroluminescence element in which, an anode, an organic layer and a cathode are stacked in this order; and after the formation of the element region, repairing a short circuit area while setting at least the element region in an atmosphere in which an oxygen concentration is 0.1% or higher and less than 1% and a dew point is ?50 degrees or less, and applying a voltage across the anode and the cathode.

Abstract: Method for recovering treated metal silicide surfaces or layers are provided. In at least one embodiment, a substrate having an at least partially oxidized metal silicide surface disposed thereon is cleaned to remove the oxidized regions to provide an altered metal silicide surface. The altered metal silicide surface is then exposed to one or more silicon-containing compounds at conditions sufficient to recover the metal silicide surface.

Abstract: A pixel structure disposed on a substrate and including a common line, a reserved line, a dielectric layer, two repair lines, an active device, and a pixel electrode is provided. The reserved line and the common line are disposed on the substrate and are covered by the dielectric layer. The repair lines are disposed on the dielectric layer, and each repair line has a first repairing region overlapped with the common line and a second repairing region overlapped with the reserved line. When the common line is open, the repair lines in the first and second repairing regions are connected with the common line and the reserved line, such that the common line, the repair lines, and the reserved line are electrically connected. After the common line, the repair lines, and the reserved line are connected, the above-mentioned pixel structure is effectively repaired.

Abstract: A method for improving semiconductor yield by in-line repair of defects during manufacturing comprises inspecting dies on a wafer after a selected layer is formed on the dies, identifying defects in each of the dies, classifying the identified defects as killer or non-critical, for each killer defect determining an action to correct the defect, repairing the defect and returning the wafer to a next process step. Also disclosed is a method for determining an efficient repair process by dividing the die into a grid and using analysis of the grid to find a least invasive repair.

Abstract: An advanced process control (APC) architecture comprising a process model that incorporates a target offset term is provided. The APC architecture may be applied to a so-called develop inspect critical dimension (DICD) model using the target offset term to correct at least one exposure parameter on the occurrence of an abrupt event. A corresponding event may, for example, concern a modified reflectivity of processed substrates, for example due to a rework of substrates covered by amorphous carbon material.

Abstract: A method for applying a heat insulation layer (11, 12, 13) or a metallic protective layer to a thermally stressed component (200) having a basic material (10) in order to eliminate local damage (14) or an untreated place in the coating, includes, in a first step, pretreating the local damage (14) or untreated place, and, in a second step, applying layers (17, 18) necessary for eliminating the local damage (14) or untreated place. A markedly improved lifetime of the processed component can be achieved in that, within the first step, the edge regions (15) of the layers (11, 12, 13) ending at the local damage (14) or untreated place are processed so that they form uniformly sloped and terrace-shaped edge regions (16). Furthermore, a precharacterization of the entire coated region of the operationally stressed component or critical places by FSECT makes it possible to reduce the risk in terms of otherwise overlooked layer regions, the remaining lifetime of which would not persist for the following operating time.

Abstract: In a semiconductor integrated circuit device comprising a semiconductor chip having a number of conductor layers and a number of via layers between the conductor layers, a routing matrix is provided in a small area of the chip to act as a revision number register. The routing matrix includes a matrix block having, in each metal layer of the chip, conductor tracks, the tracks in each metal layer running in a respective direction different from the direction of the tracks in the adjacent metal layers so that the tracks of each consecutive pair of metal layers cross over each other. In each via layer between consecutive metal layers, the matrix block includes selectively placed vias interconnecting the tracks in the adjacent metal layers on each side of the respective via layer.

Abstract: As to an electromagnetic radiation detecting apparatus, a radiation detecting apparatus, a radiation detecting system and a laser processing method, a TFT is disposed on an insulating substrate. A conversion element converting electromagnetic radiation into an electric signal is disposed over the TFT. A member for marking the position of the switching element is disposed on the conversion element. The position of a switching element having a defect can be located by means of the member on the conversion element. By radiating laser light to be focused on the member, it becomes possible to perform repair accurately.

Abstract: The present invention provides methods of repairing damage to low-k dielectric film that is incurred by commonly used processes in IC fabrication. The methods may be integrated into an IC fabrication process flow at various stages. According to various embodiments, the methods of involve performing an IC fabrication process on a wafer on which a low-k film is deposited, and subsequently treating the film with a silylating agent to repair the damage done to the film during the process. Damage repair may be performed after one or more of the damaging process steps.

Abstract: An image sensor capable of repairing column readout circuits includes a pixel array, a column readout circuit array, an addressing unit and a repairing unit. The column readout circuit array includes a plurality of column readout circuit group and a redundant column readout circuit group, which is placed on a side of the plurality of column readout circuit groups and consists of a specific number of redundant column readout circuits. The repairing unit is utilized for shifting in order pixel column groups, which are originally coupled to column readout circuit groups starting from a first column readout circuit group having defects, to couple to the column readout circuit groups next to the first column readout circuit group and the redundant column readout circuit group.

Abstract: A process for replacing a semiconductor chip of such a flip-chip module and a suitable flip-chip module and an apparatus for implementing the method are disclosed. The flip-chip module comprises at least one semiconductor chip and a substrate. The semiconductor chip comprises contact posts on a surface that are disposed at right angles to the surface. With these contact posts it is connected with contact points of the substrate via a soldered connection. The contact posts completely cover the contact points with their end faces. Due to this it is possible to completely press the solder between the contact posts and contact points out of the intermediate area between the contact points and the contact posts after a renewed heating. This permits a renewed attachment of a further semiconductor chip.

Abstract: The size of a foreign substance which is present between a cathode and an anode and which contributes to a short circuit therebetween is measured. On the basis of the measured size, the wavelength of a laser beam with which the foreign substance is irradiated is set, as is the number of times of irradiation. The foreign substance is irradiated with the laser beam to eliminate at least part of the foreign substance.

Abstract: Using a helium cryostat, the temperature for a substrate wafer(s) is reduced to 2.2 Kelvin over a period of twenty-four hours. Next, a soak segment will hold the temperature of the substrate wafer at 2.2 Kelvin for a period of ninety-six hours. At these low temperatures, alloys such as GaAs, InP, and GaP will form dipole molecular moments, which will re-align along lines of internal magnetic force as molecular bonds condense. Next the substrate wafer's temperature is ramped up to room temperature over a period of twenty-four hours. Next, the temperature of the substrate wafer is ramped up to assure that the temperature gradients made to occur within the wafer are kept low. Next, the substrate wafer undergoes a temper hold segment, which assures that the entire substrate wafer has had the benefit of the tempering temperature.

Abstract: Contaminants from surfaces of temperature sensitive substrates, such as glass substrates are removed by exposing the surfaces to a hydrogen Surface-mixed diffusion flame for a predetermined duration of time. The predetermined duration of time being insufficient to heat up the surfaces substantially thereby causing damage to the temperature sensitive substrates.

Abstract: A fuse box in a semiconductor device having a fuse line formed in a fuse line region to form a conductive pattern; wherein the conductive pattern has an empty space in the center thereof and a phase change material pattern in the empty space, and an insulation pattern formed over the fuse line to expose the phase change material pattern.

Abstract: A method of forming an interconnect structure for an integrated circuit, including the steps of providing a substrate and forming a dielectric stack on the substrate including an etch-stop layer, a low-k dielectric layer, and a hardmask layer. The method further includes the steps of patterning a photoresist masking layer on the dielectric stack to define a plurality of feature defining regions and plasma processing the substrate in a plasma-based reactor, The processing step includes etching a plurality of features into the hardmask layer and at least a portion of the low-k dielectric layer and performing a plasma treatment process in situ in the plasma-based reactor, where the plasma treatment process includes flowing at least one hydrocarbon into the reactor and generating a plasma, where a mass flow rate of the hydrocarbon is at least 0.1 sccm. The method also includes forming a metal conductor in the plurality of features.

Abstract: An electronic device including a semiconductor device with a plurality of bump electrodes, a mounting board connected to the semiconductor device, thermally expandable particles, and adhesive. The thermally expandable particles are provided on the sides of the semiconductor device and the surface of the mounting board around a projected area of the semiconductor device. The adhesive is provided on the sides of the semiconductor device and the surface of the mounting board such that it covers the area of thermally expandable particles. This improves the impact resistance of the semiconductor device soldered onto the mounting board, and also facilitates removal of the semiconductor device from the mounting board when the semiconductor device needs repair.

Abstract: A method for inspecting a pattern includes measuring, in a first direction, a width of a reference pattern at plural positions in the reference patter; measuring, in a second direction, a width of the reference pattern at the plural positions. Comparing the first and second width and determining which of the first and second widths is shortest; extracting a defect in a pattern to be inspected; and evaluating the extracted defect depending on the determined direction.

Abstract: The present invention allows correcting malfunctions occurring in the formation of a cap layer on an electrical element in a semiconductor substrate. It is detected whether a malfunction occurred in the formation of the cap layer. If a malfunction in the formation of the cap layer was detected, a rework procedure is performed. The rework procedure can comprise exposing the substrate to a first acid and a second acid.

Abstract: Systems and methods are disclosed for the disassembly and preferably reassembly of semiconductor device packages. A method of the invention includes steps for excavating a portion of a semiconductor device package to expose a target surface within the interior of the package. The technique further includes steps of focusing a laser at a selected distance from the target surface in order to ablate the package material, exposing the target surface. Preferred embodiments of the invention are disclosed in which a cavity is excavated through the package to expose portions of leadfingers within. A temporary chip mount plate is affixed to an exterior surface of the package to cover one side of the cavity. A chip is attached to the temporary chip mount plate where it is electrically coupled to the leadfingers in the interior of the package. The contents of the cavity are then encapsulated with dielectric mold compound and the temporary chip mount plate is preferably removed to expose the backside of the chip.

Abstract: A method for producing a matrix of electromagnetic radiation detectors made up of a plurality of elementary detection modules mounted on an interconnection substrate. The method includes depositing on the interconnection substrate a predefined number of quantities of solder or hybridization material, intended to constitute hybridization bumps for the elementary modules, in at least a first array for the nominal hybridization, and at least one second array, with the deposits of solder or hybridization material of the second array being lower in volume than those of the first array, depositing a liquid flux on the interconnection substrate, mounting the elementary modules to be hybridized on the interconnection substrate, and raising the temperature of a chamber in which the various elements to be hybridized are positioned until reaching at least the melting point of the solder or hybridization material to join the modules and interconnection substrate together by reflow effect.

Abstract: In an IC structure and method for debugging or adjusting the parameters of an IC circuitry, edit structures are formed in the IC device and are connected to desired portions of the IC circuitry buy forming vias through the passivation layer overlying the top metal layer and forming metal interconnects.

Abstract: A detachment jig is placed on a printed circuit board. Advancement of an inclined surface of the detachment jig is received on a solder bump of solid state disposed between the printed circuit board and an integrated circuit chip package. The solder bump melts to remove restraint to the advancement of the inclined surface, so that the inclined surface advances into a space between the printed circuit board and the chip package in response to the melt of the solder bump. A force to lift the chip package in the direction perpendicular to the surface of the printed circuit board acts on the chip package after the solder bump has completely melted down. Detachment of an electrically conductive pad is thus reliably prevented on the printed circuit board. The chip package can solely be removed without inducing detachment of the electrically conductive pad on the printed circuit board.

Abstract: A method for reclaiming a wafer is described. Embodiments of the invention describe a method in which an analytical measurement of a wafer surface is performed in order to determine a wafer type of the wafer. In an embodiment an XRF measurement is performed to determine the composition of a film disposed over a surface of the wafer. The XRF results are correlated with a wafer type. The wafer is then stripped in accordance with the wafer type.

Abstract: Methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplets in a similar pattern protruding from a substrate to position the dice through surface tension interaction. The alignment droplets are then solidified to maintain the positioning and an underfill is disposed between the dice and the fixture to strengthen and maintain the reconstructed wafer. A fixture plate may be used in combination with the underfill to add additional strength and simplify handling. The reconstructed wafer may be subjected to wafer-level processing, wafer-level testing and burn-in being particularly facilitated using the reconstructed wafer. Alignment droplets composed of sacrificial material may be removed from the reconstructed wafer and the resulting void filled to form interconnects or contacts on the resulting dice.

Abstract: Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be re-addressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.

Abstract: A semiconductor device mounting structure includes a semiconductor device whose electrodes are aligned on its one main face; a circuit board having board electrodes electrically connected to the electrodes of the semiconductor device by solder bumps; and curable resin applied between at least the side face of the semiconductor device and the circuit board. Multiple types of thermally expandable particles with different expansion temperatures are mixed in this curable resin. This structure offers the semiconductor device mounting structure that is highly resistant to impact and suited for mass production, its manufacturing method, and a removal method of the semiconductor device. In addition, this structure facilitates repair and reworking, leaving almost no adhesive residue on the circuit board after repair. Stress applied to the circuit board during repair can also be minimized.

Abstract: Using a helium cryostat, the temperature for a substrate wafer(s) is reduced to 2.2 Kelvin over a period of twenty-four hours. Next, a soak segment will hold the temperature of the substrate wafer at 2.2 Kelvins for a period of ninety-six hours. At these low temperatures, alloys such as GaAs, InP, and GaP will form dipole molecular moments, which will re-align along lines of internal magnetic force as molecular bonds condense. Next the substrate wafer's temperature is ramped up to room temperature over a period of twenty-four hours. Next, the temperature of the substrate wafer is ramped up to assure that the temperature gradients made to occur within the wafer are kept low. Typically, a temper ramp up temperature will range between 300° F. to 1100° F. and depends upon the single crystal material used to construct the substrate wafer. Next, the substrate wafer undergoes a temper hold segment, which assures that the entire substrate wafer has had the benefit of the tempering temperature.

Abstract: A method for in-situ repairing plasma damage, suitable for a substrate, is provided. A component is formed on the substrate. The formation steps of the component include a main etching process containing plasma. The method involves performing a soft plasma etching process in the apparatus of the main etching process containing plasma to remove a portion of the substrate. The soft plasma etching process is less than 30% of the power used in the main etching process.

Abstract: The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate compensating for retrograde feature profiles on an imprint mask. An aspect of the invention generates feedback information that facilitates control of imprint mask feature profile via employing a scatterometry system to detect retrograde feature profiles, and mitigating the retrograde profiles via a spacer etchback procedure.

Abstract: A repairing method of thin film transistor array is provided. The repairing method of thin film transistor array can remove a residue between pixel electrodes so as to prevent the residue from electrically connecting pixel electrodes adjacent to each other. The repairing method of thin film transistor array can also be provided to remove a portion of the pixel electrodes above a particle or a defect, which may cause leakage of a storage capacity. The parameters of repairing method of the thin film transistor array precisely controlled and the yield of the thin film transistor array can be effectively improved.

Abstract: A packaging substrate and a manufacturing method thereof are provided. The manufacturing method includes following steps. First, a first packaging substrate including several first substrate units and at least one defected substrate unit is provided. Next, the defected substrate unit is separated from the packaging substrate, and at least one opening is formed in a frame of the first packaging substrate correspondingly. Then, a second substrate unit is provided. The shape of the second substrate unit is different from the shape of the opening. Afterwards, the second substrate unit is disposed in the opening.

Abstract: A method of manufacturing an organic EL element includes applying a reverse bias to an organic EL element with an inverse layered structure until a current density of the organic EL element at an impressed voltage of 10 V reaches 0.075 mA/cm2 or more.

Abstract: A manufacturing method, remanufacturing method and reshipping method for a semiconductor memory device capable of preventing the charge hold characteristic from deteriorating even if information data is repeatedly written and erased. The manufacturing method is for a semiconductor memory device having a plurality of memory cells in an FET structure formed on a semiconductor substrate, wherein each of the plurality of memory cells is to store a unit bit and hold information data. Preparing a plurality of memory cells, bits of the information data are written to the memory cells. After writing the information data bits to the memory cells, the memory cells are allowed to stand at a predetermined ambient temperature for a predetermined time. Thereafter, bits of the information data are written to the memory cells.

Abstract: A method for patching up thin-film transistor (TFT) circuit patterns on a display panel comprises the following steps. Firstly, a mask having an opening is placed above the display panel and the opening corresponds to the location of the cracks of the circuits on the display panel. Subsequently, a plasma sputtering procedure is performed to deposit a metal thin film through the opening of the mask on the display panel so as to connect the broken circuits. When the metal thin film is covered on a plurality of the circuits, a laser cut-out procedure is performed to cut apart the metal thin film on the plurality of the circuits so as to prevent the different circuits from short circuits.

Abstract: An active matrix substrate including a substrate, a plurality of pixel units, a plurality of driving lines, an electron static discharge (ESD) protection circuit and a floating line is provided. The substrate has an active region and a peripheral region connected with the active region. The pixel units are arranged in a matrix in the active region. The driving lines electrically connected to the pixels are disposed in the active region and the peripheral region. The ESD protection circuit and the floating line are disposed in the peripheral region of the substrate. The ESD protection circuit is electrically connected to the driving lines. The ESD protection circuit includes an outer short ring (OSR) and an inner short ring (ISR) disposed between the pixel units and the OSR. The floating line is located beside the outer driving line.