Abstract: An apparatus for both detecting and repairing a shunt defect in a solar cell substrate. A shunt detection module detects the shunt defect in the substrate, using at least one of lock-in thermography and current-voltage testing. A process diagnostic module determines whether the substrate should be passed without further processing by the apparatus, rejected without further processing by the apparatus, or repaired by the apparatus. A shunt repair module electrically isolates the shunt defect in the substrate. In this manner, a single apparatus can quickly check for shunts and make a determination as to whether the substrate is worth repairing. If it is worth repairing, then the apparatus can make the repairs to the substrate.

Abstract: An encapsulant layer for a photovoltaic module enabling recovering and recycling or reusing of reutilizeable resources such as a transparent front face substrate and photovoltaic cell and the like among constituents of a photovoltaic module, and a method for manufacturing a regenerated photovoltaic cell and a regenerated transparent front face substrate. The photovoltaic module is formed by laminating: a transparent front face substrate; a photovoltaic cell carrying a wiring electrode and a takeoff electrode, and an encapsulant layer is placed on at least one surface; and a rear face protecting sheet. The encapsulant layer is a separable layer formed mainly of a thermoplastic resin, and an output maintenance factor of photoelectronic power of the photovoltaic module using the encapsulant layer is in a range of 80% to 100%.

Abstract: A method for providing a tuned repair for damage to a silicon based low-k dielectric layer with organic compounds, where damage replaces a methyl attached to silicon with a hydroxyl attached to silicon is provided. A precursor gas is provided, comprising a first repair agent represented as Si—(R)x(OR?)y, where y?1 and x+y=4, and wherein R is an alkyl or aryl group and R? is an alkyl or aryl group and a second repair agent represented as Si—(R)x(OR?)yR?, where y?1 and x+y=3, and wherein R is an alkyl or aryl group and R? is an alkyl or aryl group, and R? is of a group that reduces interfacial surface tension between a wet clean chemical and the low-k dielectric. Some of the first repair agent and second repair agent are bonded to the low-k dielectric to form a monolayer of the first repair agent and the second repair agent.

Abstract: Packaging is substantially entirely removed from an integrated circuit die. The method allows the batch processing of several integrated circuit dies, such that packaging is removed from each die approximately simultaneously.

Abstract: Provided is a method of manufacturing a photovoltatic cell according to the present invention, the photovoltatic cell including a substrate, and a structure in which a first conductive layer, a photoelectric conversion layer and a second conductive layer are superposed on the substrate in this order; the structure is electrically separated by a predetermined size to form a plurality of compartment elements; and the compartment elements adjacent to each other are electrically connected to each other, the method including: a defect region specifying step of specifying a region in which a structural defect exists from the plurality of compartment elements; and a repairing step of irradiating the region or the periphery thereof with a laser beam to remove the structural defect, wherein the repairing step includes a step ? of irradiating the structure with a first laser to remove or separate the region, and a step ? of irradiating an end portion of the structure generated by the removal or separation with a second

Abstract: An electronic device assembly is provided which includes a substrate, an interposer and an integrated circuit chip. The substrate is fabricated of a first material having a first thermal expansivity, and the interposer and integrated circuit chip are fabricated of a second material having a second thermal expansivity. The second thermal expansivity is different from the first thermal expansivity so that there is a coefficient of thermal expansion mismatch between the substrate and the interposer or chip. The interposer is coupled to the substrate via a first plurality of electrical contacts and an underfill adhesive at least partially surrounding the electrical contacts to bond the interposer to the substrate and thereby reduce strain on the first plurality of electrical contacts. The integrated circuit chip is coupled to the interposer via a second plurality of electrical contacts only, without use of an adhesive surrounding the second plurality of electrical contacts.

Abstract: A liquid crystal display (LCD) capable of easily implementing a repairing process is provided under a circumstance where a width of a sustain electrode line is reduced or even no sustain electrode line is provided for the purpose of ensuring an increased aperture ratio, and a method for repairing the liquid crystal display is provided. The LCD includes a gate line, extending in a first direction, and a data wiring being insulated from the gate line. The data wiring includes a source electrode, a drain electrode, and a data line extending in a second direction. A pixel electrode is connected to the drain electrode via a contact hole, and a sustain electrode line is formed in a substantially the same plane as the gate line and has a sustain electrode overlapped by the contact hole.

Abstract: The present invention provides a method for restoring the dielectric properties of a porous dielectric material. The method comprises providing a substrate comprising at least one layer of a porous dielectric material comprising a contaminant comprising at least one entrapped liquid having a surface tension, wherein the porous dielectric material comprising the at least one contaminant has a first dielectric constant. The substrate is contacted with a restoration fluid comprising water and at least one compound having a surface tension that is less than the surface tension of the at least one entrapped liquid in the at least one layer of a porous dielectric material. Upon drying, the porous dielectric material has a second dielectric constant that is lower than the first dielectric constant and all constituents of the restoration fluid are removed upon drying.

Abstract: A repair circuit of a semiconductor apparatus includes a plurality of through-silicon vias including repeated sets of one repair through-silicon via and an M number of normal through-silicon vias; a transmission unit configured to multiplex input data at a first multiplexing rate based on control signals, and transmit the multiplexed data to the plurality of through-silicon vias; a reception unit configured to multiplex signals transmitted through the plurality of through-silicon vias at a second multiplexing rate based on the control signals, and generate output data; and a control signal generation unit configured to generate sets of the control signals based on an input number of a test signal.

Abstract: Various embodiments of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, a semiconductor apparatus may include a chip, scribe lanes disposed around the chip, and a probe test logic circuit for conducting a probe test on the chip. The probe test logic circuit is disposed on a portion of the scribe lanes.

Abstract: A method, a system and a computer readable medium for integrated in-vacuo repair of low-k dielectric thin films damaged by etch and/or strip processing. A repair chamber is integrated onto a same platform as a plasma etch and/or strip chamber to repair a low-k dielectric thin film without breaking vacuum between the damage event and the repair event. UV radiation may be provided on the integrated etch/repair platform in any combination of before, after, or during the low-k repair treatment to increase efficacy of the repair treatment and/or stability of repair.

Abstract: The present invention provides a photovoltaic cell manufacturing method, the photovoltaic cell including: a photoelectric converter in which at least a first electrode layer, a semiconductor layer, and a second electrode layer are stacked in layers in this order being formed on a face of a substrate; and a connection portion of the first electrode layer and the second electrode layer, the photoelectric converter having a plurality of compartment elements which are electrically separated by a predetermined size using scribing lines at which the semiconductor layer and the second electrode layer are removed, adjacent compartment elements being electrically connected to each other, the photovoltaic cell manufacturing method comprising: a defect region specifying step in which a region at which the structural defect exists is specified in the photoelectric converter; and a repairing step in which at least three repair lines in which the semiconductor layer and the second electrode layer are removed are formed by

Abstract: Provided is a method of manufacturing an organic EL display which includes a substrate having a TFT therein and a plurality of organic EL elements disposed on the substrate, each of the organic EL elements having a first electrode disposed on the substrate, an organic layer disposed on the first electrode, and a second electrode disposed on the organic layer, the method including: providing the substrate having the TFT therein; forming the first electrode connected to the TFT on the substrate; forming the organic layer on the first electrode; detecting a foreign substance introduced in the organic layer; forming a groove which surrounds the foreign substance in the organic layer; and forming the second electrode on the organic layer, the second electrode being separated by the groove from a region surrounded by the groove.

Abstract: A system in package (10) has a, preferably wireless, test controller (20) for testing each die (30) after it has been mounted onto the substrate of the system in package (10), and a faulty die (30) is repaired before a next die (30) is mounted onto the substrate (15). This way, the system in package (10) can be tested during the intermediate stages of its manufacturing, thus ensuring that all dies (30) function correctly before sealing the dies in the single package. Consequently, a method for manufacturing a system in package (10) is obtained that has an improved yield compared to known manufacturing methods.

Abstract: The present invention provides a method of manufacturing a thin-film solar panel with a laser scribing process to perform linear groove processing by irradiating a thin-film layer formed on a substrate with laser light to be separated from adjacent structure, including steps of: specifying an accurate position, size, shape of a adhered foreign matter on a glass substrate, a glass scratch, an air-bubble in the glass substrate causing an imperfection by inspecting a scribe line; and performing repair processing to form a new scribe line to bypass a portion of the imperfection after a final scribe line is formed.

Abstract: A method of manufacturing a light emitting device is provided in which satisfactory image display can be performed by the investigation and repair of short circuits in defect portions of light emitting elements. A backward direction electric current flows in the defect portions if a reverse bias voltage is applied to the light emitting elements having the defect portions. Emission of light which occurred from the backward direction electric current flow is measured by using an emission microscope, specifying the position of the defect portions, and short circuit locations can be repaired by irradiating a laser to the defect portions, turning them into insulators.

Abstract: A method of fabricating a semiconductor device is disclosed. In one embodiment, the method includes providing at least one semiconductor chip including an electrically conductive layer. A voltage is applied to an electrode. The electrode is moved over the electrically conductive layer for growing a metal layer onto the electrically conductive layer.

Abstract: The invention provides a method for recycling/reclaiming a monitor or test wafer and a method for testing an integrated circuit manufacturing process. After a monitor wafer has been used for testing one or more semiconductor wafer processing steps to determine adequacy for use with production wafers, deposited materials and other residues from the tested processing steps are removed, and the stripped wafer is subjected to a thermal anneal to repair defects in its surface and return it to a reusable condition.

Abstract: A deposition film shape simulation method for calculating a thickness of a thin-film formed by supplying deposition species on a substrate surface, includes: changing a parameter to be used in the calculation depending on the thickness of the deposited thin-film.

Abstract: According to an embodiment of the invention, an electronic device with a fuse structure is provided. The electronic device includes a substrate, at least a conducting layer formed in or on the substrate and having a fuse area, and at least a lens disposed overlying the fuse area of the conducting layer, wherein the lens is substantially aligned with the fuse area and there is no optical device disposed between the lens and the fuse area.

Abstract: A method for the ultraviolet (UV) treatment of carbon-containing low-k dielectric and associated apparatus enables process induced damage repair. The methods of the invention are particularly applicable in the context of damascene processing to recover lost low-k property of a dielectric damaged during processing, either pre-metallization, post-planarization, or both. UV treatments can include an exposure of the subject low-k dielectric to a constrained UV spectral profile and/or chemical silylating agent, or both.

Abstract: Embodiments of the present invention generally provide techniques and apparatus for altering the functionality of a multi-chip package (MCP) without requiring entire replacement of the MCP. The MCP may be designed with a top package substrate designed to interface with an add-on package that, when sensed by the MCP, alters the functionality of the MCP.

Abstract: An semiconductor device having a plurality of fabrication layers. A first region of a first fabrication layer of the semiconductor device is revised. To signal the revision, a connectivity structure in a second region of the first fabrication layer is omitted to interrupt an otherwise continuous signal path that extends through a plurality of interconnection layers of the semiconductor device.

Abstract: Treatment of carbon-containing low-k dielectric with UV radiation and a reducing agent enables process-induced damage repair. Also, treatment with a reducing agent and UV radiation is effective to clean a processed wafer surface by removal of metal oxide (e.g., copper oxide) and/or organic residue of CMP slurry from the planarized surface of a processed wafer with or without low-k dielectric. The methods of the invention are particularly applicable in the context of damascene processing to recover lost low-k property of a dielectric damaged during processing, either pre-metalization, post-planarization, or both, and/or provide effective post-planarization surface cleaning to improve adhesion of subsequently applied dielectric barrier and/or other layers.

Abstract: A method for forming a thin film electrode for an organic thin film transistor of the invention provides a multi-layer mask on a substrate with an electrode area opening in a top layer of the mask that is undercut by openings in other layers of the mask. A thin film of metal is deposited in the electrode area on the substrate. Removing the multi-layer mask leaves a well-formed thin film electrode with naturally tapered edges. A preferred embodiment of the invention is a method for forming a thin film electrode for an organic thin film transistor. The method includes depositing a first layer of photoresist on a substrate. The photoresist of the first layer has a first etching rate. A second layer of photoresist is deposited on the first layer of photoresist. The photoresist of the second layer has a second etching rate that is lower than the first etching rate. The first and second layer of photoresist are patterned by exposure.

Abstract: A photovoltaic module and a method of manufacturing such a module in which metal is deposited in a pattern on the front side of a semiconductor wafer which acts as an electrode. Photovoltaic cells manufactured using a semiconductor wafer typically have a P type semiconductor region and an N type semiconductor region. The metal on the front side of each of the photovoltaic cells forms an electrical connection to the doped layer of the semiconductor wafer on its front side.

Abstract: An apparatus, system, and method are disclosed for restoring efficiency of a photovoltaic cell. An illumination module illuminates photovoltaic cells so the cells receive a time integrated irradiance equivalent to at least 5 hours of solar illumination. After illumination, an annealing module anneals the photovoltaic cells at a temperature above 90 degrees Celsius for a minimum of 10 minutes. In one embodiment, the illumination module illuminates the photovoltaic cells for a time integrated irradiance equivalent to at least 20 hours of solar illumination. In another embodiment, the illumination module illuminates the photovoltaic cells for a time integrated irradiance equivalent to at least 16 hours of solar illumination while being heated to at least 50 degrees Celsius. In another embodiment, a solar concentrator irradiates the photovoltaic cells in sunlight for at least 10 hours and increases the irradiance of solar illumination on the cells by a factor of 2 to 5.

Abstract: The present invention provides a method of manufacturing an organic light-emitting device which is applicable to a large-screen display device. The method includes the steps of: forming, over a drive substrate, an element region including a drive transistor, and an organic electroluminescence element in which, an anode, an organic layer and a cathode are stacked in this order; and after the formation of the element region, repairing a short circuit area while setting at least the element region in an atmosphere in which an oxygen concentration is 0.1% or higher and less than 1% and a dew point is ?50 degrees or less, and applying a voltage across the anode and the cathode.

Abstract: The present invention provides a signal transmitting/receiving method comprising: disposing a ferromagnetic film between a semiconductor device having an inductor and an external device which includes an external inductor provided in a position corresponding to the inductor of the semiconductor device; disposing the inductor and the external inductor so as to face each other via the ferromagnetic film therebetween; and in a state in which the inductor and the external inductor face each other, transmitting and receiving the signals between the inductor and the external inductor by electromagnetic induction.

Abstract: A method for providing a tuned repair for damage to a silicon based low-k dielectric layer with organic compounds, where damage replaces a methyl attached to silicon with a hydroxyl attached to silicon is provided. A precursor gas is provided, comprising a first repair agent represented as Si—(R)x(OR?)y, where y?1 and x+y=4, and wherein R is an alkyl or aryl group and R? is an alkyl or aryl group and a second repair agent represented as Si—(R)x(OR?)yR?, where y?1 and x+y=3, and wherein R is an alkyl or aryl group and R? is an alkyl or aryl group, and R? is of a group that reduces interfacial surface tension between a wet clean chemical and the low-k dielectric. Some of the first repair agent and second repair agent are bonded to the low-k dielectric to form a monolayer of the first repair agent and the second repair agent.

Abstract: A rework method of a gate insulating layer of a thin film transistor includes the following steps. First, a substrate including a silicon nitride layer, which serves as a gate insulating layer, disposed thereon. Subsequently, a first film removal process is performed to remove the silicon nitride layer. The first film removal process includes an inductively coupled plasma (ICP) etching process. The ICP etching process is carried out by introducing gases including sulfur hexafluoride and oxygen. The ICP etching process has an etching selectivity ratio of the silicon nitride layer to the substrate, which is substantially between 18 and 30.

Abstract: A treating agent composition for increasing the hydrophobicity of an organosilicate glass dielectric film when applied to said film. It includes a component capable of alkylating or arylating silanol moieties of the organosilicate glass dielectric film via silylation, and an activating agent which may be an acid, a base, an onium compound, a dehydrating agent, and combinations thereof, and a solvent or mixture of a main solvent and a co-solvent.

Abstract: An exemplary TFT array substrate includes: an insulating substrate (201), a gate line (23) and a repair structure (272) arranged on the insulating substrate, a gate insulating layer (204) covering the gate line and the repair structure; a data line (27) arranged on the gate insulating layer corresponding to the repair structure, which is insulated from the gate line and intersects with the gate line. The repair structure has a gap (274). The gap of the repair structure is located at where the repair structure overlapping to the gate line.

Abstract: Reconditioned donor substrates that include a remainder substrate from a donor substrate wherein the remainder substrate has a detachment surface where a transfer layer was detached and an opposite surface; and an additional layer deposited upon the opposite surface of the remainder substrate to increase its thickness and to form the reconditioned substrate. The reconditioned substrate is recycled as a donor substrate for fabricating compound material wafers and is typically made from gallium nitride donor substrates.

Abstract: A method for the ultraviolet (UV) treatment of carbon-containing low-k dielectric enables process-induced damage repair. The method is particularly applicable in the context of damascene processing. A method provides for forming a semiconductor device by depositing a carbon-containing low-k dielectric layer on a substrate and forming a trench in the low-k dielectric layer, the trench having sidewalls ending at a bottom. The trench is then exposed to UV radiation and, optionally a gas phase source of —CH3 groups, to repair damage to the carbon-containing low-k material of the trench sidewalls and bottom caused by the trench formation process (generally etching, ashing, and wet or dry cleaning). A similar treatment, with or without the gas phase source of —CH3 groups, may be applied to repair damage caused in a subsequent planarization operation.

Abstract: A method of treating a nanoporous low-k dielectric material formed on a semiconductor substrate is provided. The low-k dielectric material has etched openings with an etch damaged region containing silanol groups on exterior surfaces of the etched openings and on interior surfaces of interconnected pores. First, the low-k dielectric material is contacted with a vapor phase catalyst in an amount effective to form hydrogen bonds between the catalyst and the silanol groups in the etch damaged region, forming a catalytic intermediary.

Abstract: Disclosed is a method for manufacturing a solar cell module in which a wiring substrate having a base material and a wiring formed on the base material, and a plurality of solar cells electrically connected by being placed on the wiring of the wiring substrate are sealed with a sealant, including a first step of placing at least one of the solar cells on the wiring of the wiring substrate, and a second step of sealing the wiring substrate and the solar cells with the sealant, the method including the step of conducting an inspection of the solar cells after the first step and before the second step.

Abstract: A light-emitting device including a plurality of light-emitting units is provided. Each of the light-emitting units includes a first common electrode layer, a plurality of light-emitting layers, and a second common electrode layer. The first common electrode layer includes a bridge conductive line and a plurality of first electrode patterns electrically insulated from each other, in which the first electrode patterns cover a portion of the bridge conductive line and are electrically connected to each other through the bridge conductive line. Each of the light-emitting layers is disposed on one of the first electrode patterns. The second common electrode layer is disposed on the light-emitting layers, in which the first common electrode layer of each of the light-emitting units is electrically connected to the second common electrode layer of an adjacent light-emitting unit.

Abstract: Method for recovering treated metal silicide surfaces or layers are provided. In at least one embodiment, a substrate having an at least partially oxidized metal silicide surface disposed thereon is cleaned to remove the oxidized regions to provide an altered metal silicide surface. The altered metal silicide surface is then exposed to one or more silicon-containing compounds at conditions sufficient to recover the metal silicide surface.

Abstract: Often used to reduce the RC delay in integrated circuits are dielectric films of porous organosilicates which have a silica like backbone with alkyl or aryl groups (to add hydrophobicity to the materials and create free volume) attached directly to the Si atoms in the network. Si—R bonds rarely survive an exposure to plasmas or chemical treatments commonly used in processing; this is especially the case in materials with an open cell pore structure. When Si—R bonds are broken, the materials lose hydrophobicity, due to formation of hydrophilic silanols and low dielectric constant is compromised. A method by which the hydrophobicity of the materials is recovered using a novel class of silylation agents which may have the general formula (R2N)XSiR?Y where X and Y are integers from 1 to 3 and 3 to 1 respectively, and where R and R? are selected from the group of hydrogen, alkyl, aryl, allyl and a vinyl moiety. Mechanical strength of porous organosilicates is also improved as a result of the silylation treatment.

Abstract: A method for the ultraviolet (UV) treatment of carbon-containing low-k dielectric enables process-induced damage repair. The method is particularly applicable in the context of damascene processing. A method provides for forming a semiconductor device by depositing a carbon-containing low-k dielectric layer on a substrate and forming a trench in the low-k dielectric layer, the trench having sidewalls ending at a bottom. The trench is then exposed to UV radiation and, optionally a gas phase source of —CH3 groups, to repair damage to the carbon-containing low-k material of the trench sidewalls and bottom caused by the trench formation process (generally etching, ashing, and wet or dry cleaning). A similar treatment, with or without the gas phase source of —CH3 groups, may be applied to repair damage caused in a subsequent planarization operation.

Abstract: There is provided a processing method for performing a recovery process on a damaged layer formed on a surface of a low-k film of a target substrate by introducing a processing gas containing a methyl group into a processing chamber. The method includes: increasing an internal pressure of the processing chamber up to a first pressure lower than a processing pressure for the recovery process by introducing a dilution gas into the processing chamber maintained in a depressurized state; then stopping the introduction of the dilution gas, and increasing the internal pressure of the processing chamber up to a second pressure as the processing pressure for the recovery process by introducing the processing gas into a region where the target substrate exists within the processing chamber; and performing the recovery process on the target substrate while the processing pressure is maintained.

Abstract: Provided is a defect correcting device for an electronic circuit pattern, which is capable of making a defect seed obvious, and normalizing a pixel or forming a pixel into a semi-black spot. A defect correcting device for an electronic circuit pattern includes: an imaging unit for irradiating a defective portion of the electronic circuit pattern with irradiation light having a wavelength of a visible light region and a wavelength of an infrared light region, and receiving reflected light having the wavelength of the visible light region and the wavelength of the infrared light region from the electronic circuit pattern; a signal processing unit for extracting the defective portion from a picked-up image, and determining a correcting method; a laser irradiating unit for irradiating the defective portion with laser light; and a correction determining unit for determining success or failure of defect correction before and after laser irradiation.

Abstract: A method for fabricating a semiconductor device, includes forming a porous dielectric film above a substrate using a porous insulating material, forming an opening in the porous dielectric film, repairing film quality of the porous dielectric film on a surface of the opening by feeding a predetermined gas replacing a Si—OH group to the opening, and performing pore sealing of the surface of the opening using the same predetermined gas as that used for film quality repairs after repairing the film quality.

Abstract: A pixel structure disposed on a substrate and including a common line, a reserved line, a dielectric layer, two repair lines, an active device, and a pixel electrode is provided. The reserved line and the common line are disposed on the substrate and are covered by the dielectric layer. The repair lines are disposed on the dielectric layer, and each repair line has a first repairing region overlapped with the common line and a second repairing region overlapped with the reserved line. When the common line is open, the repair lines in the first and second repairing regions are connected with the common line and the reserved line, such that the common line, the repair lines, and the reserved line are electrically connected. After the common line, the repair lines, and the reserved line are connected, the above-mentioned pixel structure is effectively repaired.

Abstract: A writing data processing control apparatus includes an assignment part configured to assign processing of a plurality of pieces of writing data of predetermined divided writing regions, stored in a storage device, one by one to one of a plurality of processing apparatuses in which processing is performed in parallel, and a separation part configured, when a processing error occurred as a result of processing of writing data read from the storage device by a first processing apparatus assigned, to separate the first processing apparatus in which the processing error occurred from assigning targets of subsequent writing data processing, wherein the assignment part reassigns the processing of the writing data in which the processing error occurred to a second processing apparatus being different from the first processing apparatus.

Abstract: A method for repairing a chip with a stacked structure of chips is provided. First, a first chip is provided, which includes a first circuit block with a first function, a second circuit block with a second function, and a signal path electrically connected to the first and the second circuit blocks. A second chip is provided, which includes a third circuit block with the first function. The functions of the first and the second chips are verified. The first circuit block is disabled if the first circuit block is defective. The third circuit block is electrically connected to the signal path to replace the first circuit block and provide the first function if the second circuit block is functional and the third circuit block is functional.

Abstract: Disclosed are embodiments of a semiconductor chip structure and a method that incorporate a localized, on-chip, repair scheme for devices that exhibit performance degradation as a result of negative bias temperature instability (NBTI). The repair scheme utilizes a heating element above each device. The heating element is configured so that it can receive transmission line pulses and, thereby generate enough heat to raise the adjacent device to a temperature sufficient to allow for performance recovery. Specifically, high temperatures (e.g., between approximately 300-400° C. or greater) in the absence of bias can accelerate the recovery process to a matter of seconds as opposed to days or months. The heating element can be activated, for example, on demand, according to a pre-set service schedule, and/or in response to feedback from a device performance monitor.

Abstract: A method that includes forming a gate of a semiconductor device on a substrate and forming a recess for an embedded silicon-straining material in source and drain regions for the gate. In this method, a proximity value, which is defined as a distance between the gate and a closest edge of the recess, is controlled by controlling formation of an oxide layer provided beneath the gate. The method can also include feedforward control of process steps in the formation of the recess based upon values measured during the formation of the recess. The method can also apply feedback control to adjust a subsequent recess formation process performed on a subsequent semiconductor device based on the comparison between a measured proximity value and a target proximity value to decrease a difference between a proximity value of the subsequent semiconductor device and the target proximity value.

Abstract: A technique for altering or repairing the operating state of a semiconductor device comprises field-controlled diffusion of mobile dopant atoms within the metal oxide crystal lattice. When heated (e.g., above 550 K) in the presence of an electric field (e.g., bias to ground of +/?50 V) the dopant atoms are caused to collect to form an ohmic contact, leaving a depletion region. Metal-semiconductor junction devices such as diodes, photo-diodes, photo-detectors, MESFETs, etc. may thereby be fabricated, repaired or modified.