Abstract: A gallium ink is provided, comprising, as initial components: a gallium component comprising gallium; a stabilizing component; an additive; and, a liquid carrier; wherein the gallium ink is a stable dispersion. Also provided are methods of preparing the gallium ink and for using the gallium ink in the preparation of semiconductor films (e.g., in the deposition of a CIGS layer for use in photovoltaic devices).

Abstract: One aspect in the present disclosure relates to a method for manufacturing an amorphous metal oxide semiconductor. In an exemplary embodiment, a film is deposited on a substrate from a mixed solution as a starting element. For example, the mixed solution includes at least an indium alkoxide and a zinc alkoxide in a solvent. The film made from the mixed solution on the substrate is cured by thermal-annealing in a water vapor atmosphere, at a temperature range of, for example, 210 to 275 degrees Celsius, inclusive.

Abstract: The present invention relates to a method that involves providing a stack of a first substrate and a InGaN seed layer formed on the first substrate, growing an InGaN layer on the InGaN seed layer to obtain an InGaN-on-substrate structure, forming a first mirror layer overlaying the exposed surface of the grown InGaN layer, attaching a second substrate to the exposed surface of the mirror layer, detaching the first substrate from the InGaN seed layer and grown InGaN layer to expose a surface of the InGaN seed layer opposite the first mirror layer, and forming a second mirror layer overlaying the opposing surface of the InGaN seed layer.

Abstract: A substrate treating apparatus including: a first chamber having a coating part which forms a coating film of a liquid material containing an oxidizable metal and a solvent on a substrate; a second chamber having a first heating part which heats the coating film; and a connection part which connects the first chamber and the second chamber, wherein the connection part is provided with a second heating part which heats the coating film coated on the substrate and a pressure control part which controls the pressure around the coating film.

Abstract: The present invention is related to a method for manufacturing a low defect interface between a dielectric material and an III-V compound. More specifically, the present invention relates to a method for manufacturing a passivated interface between a dielectric material and an III-V compound. The present invention is also directed to a device comprising a low defect interface between a dielectric material and an III-V compound that has improved performance.

Abstract: The purpose is manufacturing a photoelectric conversion device with excellent photoelectric conversion characteristics typified by a solar cell with effective use of a silicon material. A single crystal silicon layer is irradiated with a laser beam through an optical modulator to form an uneven structure on a surface thereof. The single crystal silicon layer is obtained in the following manner; an embrittlement layer is formed in a single crystal silicon substrate; one surface of a supporting substrate and one surface of an insulating layer formed over the single crystal silicon substrate are disposed to be in contact and bonded; heat treatment is performed; and the single crystal silicon layer is formed over the supporting substrate by separating part of the single crystal silicon substrate fixed to the supporting substrate along the embrittlement layer or a periphery of the embrittlement layer.

Abstract: A method of fabricating templated semiconductor nanowires on a surface of a semiconductor substrate for use in semiconductor device applications is provided. The method includes controlling the spatial placement of the semiconductor nanowires by using an oxygen reactive seed material. The present invention also provides semiconductor structures including semiconductor nanowires. In yet another embodiment, patterning of a compound semiconductor substrate or other like substrate which is capable of forming a compound semiconductor alloy with an oxygen reactive element during a subsequent annealing step is provided. This embodiment provides a patterned substrate that can be used in various applications including, for example, in semiconductor device manufacturing, optoelectronic device manufacturing and solar cell device manufacturing.

Abstract: An ink composition includes a solvent system, a plurality of metal chalcogenide nanoparticles, at least one of metal ions and metal complex ions and a sodium source. The at least one of the metal ions and the metal complex ions are distributed on the surface of the metal chalcogenide nanoparticles and adapted to disperse the metal chalcogenide nanoparticles in the solvent system. The sodium source is dispersed in the solvent system and/or is included in at least one of the metal chalcogenide nanoparticle, the metal ions and the metal complex ions. The metals of the metal chalcogenide nanoparticles, the metal ions and the metal complex ions are selected from a group consisted of group I, group II, group III, group IV elements of periodic table, and sodium and include all metal elements of a chalcogenide semiconductor material.

Abstract: The invention relates to a process for deposition of elongated nanoparticles from a liquid carrier onto a substrate, and to electronic devices prepared by this process.

Abstract: Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure.

Abstract: A method and computer program for the control of the heat treatment of batches of metal workpieces for increasing the degree of automation of industrial furnace plants presumes an identical batch layout, an identical treatment program, and an identical article geometry of metal workpieces and relates it to a model batch, which has been run using batch thermoelements. The model batch becomes the foundation for a new batch. Through the assumption of program parameters of the actually run process of the model batch into the program of the new batch to be run, new batch thermoelements are not required for the new batch to be run.

Abstract: The invention is to provide a method for heat treating a silicon wafer reducing grown-in defects while suppressing generation of slip during RTP and improving surface roughness of the wafer. The method performing a first heat treatment while introducing a rare gas, the first heat treatment comprising the steps of rapidly heating the wafer to T1 of 1300° C. or higher and the melting point of silicon or lower, keeping the wafer at T1, rapidly cooling the wafer to T2 of 400-800° C. and keeping the wafer at T2; and performing a second heat treatment while introducing an oxygen gas in an amount of 20-100 vol. %, the second heat treatment comprising the steps of keeping the wafer at T2, rapidly heating the wafer from T2 to T3 of 1250° C. or higher and the melting point of silicon or lower, keeping the wafer at T3 and rapidly cooling the wafer.

Abstract: The present invention relates generally to the field of macro- and microelectronics with the potential for large-scale integration, optics, communications, and computer technology and particularly to the materials for these and other related fields. The present invention provides an anisotropic semiconductor film on a substrate, comprising at least one solid layer of material that comprises predominantly planar graphene-like carbon-based structures and possesses anisotropy of conductivity, and wherein the layer thickness is in a range from approximately 5 nm to 1000 nm.

Abstract: A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g.

Abstract: Embodiments of the invention contemplate the formation of a high efficiency solar cell using novel methods to form the active doped region(s) and the metal contact structure of the solar cell device. In one embodiment, the methods include the steps of depositing a dielectric material that is used to define the boundaries of the active regions and/or contact structure of a solar cell device. Various techniques may be used to form the active regions of the solar cell and the metal contact structure.

Abstract: Disclosed is a method for fabrication of a semiconductor of gallium nitride arsenide antimonide (GaNAsSb) on a substrate wherein the fabrication is performed at a fabrication temperature followed by annealing at an annealing temperature for an annealing time; wherein at least one of: the fabrication temperature, annealing temperature and annealing time, is controlled for controlling defect formation in the semiconductor so as to achieve predetermined performance characteristics of the semiconductor.

Abstract: The invention relates to a measuring arrangement, a semiconductor arrangement and a method for operating a reference source, wherein at least one semiconductor component and a voltage source are connected to a measuring unit and the measuring unit provides a measured value that is proportional to the number of defects.

Abstract: A three-dimensional polycrystalline semiconductor material provides a major ingredient forming individual crystalline grains having a nominal maximum grain diameter less than or equal to 50 nm, and a minor ingredient forming boundaries between the individual crystalline grains.

Abstract: This invention relates to processes for preparing films of CTS and CZTS and their selenium analogues on a substrate. Such films are useful in the preparation of photovoltaic devices. This invention also relates to processes for preparing coated substrates and for making photovoltaic devices.

Abstract: A semiconductor wafer in which a carbon thin film is formed on a surface of a silicon substrate implanted with impurities is irradiated with flash light emitted from flash lamps. Absorbing the flash light causes the temperature of the carbon thin film to increase. The surface temperature of the silicon substrate implanted with impurities is therefore increased to be higher than that in a case where no thin film is formed, and the sheet resistance value can be thereby decreased. When the semiconductor wafer with the carbon thin film formed thereon is irradiated with flash light in high concentration oxygen atmosphere, since the carbon of the thin film is oxidized to be vaporized, removal of the thin film is performed concurrently with flash heating.

Abstract: A method of manufacturing a silicon wafer provides a silicon wafer which can reduce the precipitation of oxygen to prevent a wafer deformation from being generated and can prevent a slip extension due to boat scratches and transfer scratches serving as a reason for a decrease in wafer strength, even when the wafer is provided to a rapid temperature-rising-and-falling thermal treatment process.

Abstract: Example embodiments relate to methods of manufacturing p-type Zn oxide nanowires and electronic devices including the p-type Zn oxide nanowires. The method may include forming Zn oxide nanowires in an aqueous solution by using a hydrothermal synthesis method and annealing the Zn oxide nanowires to form p-type Zn oxide nanowires.

Abstract: Methods for manufacturing a semiconductor device include forming a seed layer containing a silicon material on a substrate. An amorphous silicon layer containing amorphous silicon material is formed on the seed layer. The amorphous silicon layer is doped with an impurity. A laser beam is irradiated onto the amorphous silicon layer to produce a phase change of the amorphous silicon layer and change the amorphous silicon layer into a single-crystal silicon layer based on the seed layer.

Abstract: A heat treatment method which can prevent heat deformation of a substrate caused during a heat treatment process on the substrate with a thin film formed on its surface is provided. The heat treatment method in accordance with the present invention includes (a) stacking a second substrate 10b on a first substrate 10a; and (b) stacking a weight 20 on the second substrate 10b, wherein the first substrate 10a and the second substrate 10b are stacked, with thin films 12 of the substrates 10a and 10b being in contact with each other. In accordance with the present invention, deformation of the substrate can be prevented by stacking the substrates, with thin films formed on the substrates being in contact with each other, and placing a weight on the stacked substrates during the heat treatment process.

Abstract: An object of the present invention is to perform temperature setting of a heating plate so that a wafer is uniformly heated in an actual heat processing time. The temperature of a wafer is measured during a heat processing period from immediately after a temperature measuring wafer is mounted on the heating plate to the time when the actual heat processing time elapses. Whether the uniformity in temperature within the wafer is allowable or not is determined from the temperature of the wafer in the heat processing period, and if the determination result is negative, a correction value for a temperature setting parameter of the heating plate is calculated using a correction value calculation model from the measurement result, and the temperature setting parameter is changed.

Abstract: Disclosed is a method of providing a poly-Si layer used in fabricating poly-Si TFT's or devices containing poly-Si layers. Particularly, a method utilizing at least one metal plate covering the amorphous silicon layer or the substrate, and applying RTA (Rapid Thermal Annealing) for light illuminating process, then the light converted into heat by the metal plate will further be conducted to the amorphous silicon layer to realize rapid thermal crystallization. Thus the poly-Si layer of the present invention is obtained.

Abstract: An object of the present invention is obtaining a semiconductor film with uniform characteristics by improving irradiation variations of the semiconductor film. The irradiation variations are generated due to scanning while irradiating with a linear laser beam of the pulse emission. At a laser crystallization step of irradiating a semiconductor film with a laser light, a continuous light emission excimer laser emission device is used as a laser light source. For example, in a method of fabricating an active matrix type liquid crystal display device, a continuous light emission excimer laser beam is irradiated to a semiconductor film, which is processed to be a linear shape, while scanning in a vertical direction to the linear direction. Therefore, more uniform crystallization can be performed because irradiation marks can be avoided by a conventional pulse laser.

Abstract: In a manufacturing method for a silicon wafer, a first heat treatment process is performed on the silicon wafer while introducing a first gas having an oxygen gas in an amount of 0.01 vol. % or more and 1.00 vol. % or less and a rare gas, and a second heat treatment process is performed while stopping introducing the first gas and introducing a second gas having an oxygen gas in an amount of 20 vol. % or more and 100 vol. % or less and a rare gas. In the first heat treatment process, the silicon wafer is rapidly heated to first temperature of 1300° C. or higher and a melting point of silicon or lower at a first heating rate, and kept at the first temperature. In the second heat treatment process, the silicon wafer is kept at the first temperature, and rapidly cooled from the first temperature at a first cooling rate.

Abstract: A method of manufacturing a silicon wafer, an oxygen concentration in a surface layer to be maintained more than a predetermined value while promoting a defect-free layer. Strength of the surface layer can be made higher than that of an ordinary annealed sample as a COP free zone is secured. A method of manufacturing a silicon wafer doped with nitrogen and oxygen, includes growing a single crystal silicon doped with the nitrogen by Czochralski method, slicing the grown single crystal silicon to obtain a single crystal silicon wafer; heat treating the sliced single crystal silicon wafer in an ambient gas including a hydrogen gas and/or an inert gas; polishing the heat treated single crystal silicon wafer, after the heat treatment, such that an obtained surface layer from which COP defects have been removed by the heat treatment is polished away until an outermost surface has a predetermined oxygen concentration.

Abstract: A method is disclosed for manufacturing a semiconductor device, including providing a substrate comprising a main surface with a non flat topography, the surface comprising at least one substantial topography variation, forming a first capping layer over the main surface such that, during formation of the first capping layer, local defects in the first capping layer are introduced, the local defects being positioned at locations corresponding to the substantial topography variations and the local defects being suitable for allowing a predetermined fluid to pass through. Associated membrane layers, capping layers, and microelectronic devices are also disclosed.

Abstract: Embodiments of the invention contemplate the formation of a high efficiency solar cell using novel methods to form the active doped region(s) and the metal contact structure of the solar cell device. In one embodiment, the methods include the steps of depositing a dielectric material that is used to define the boundaries of the active regions and/or contact structure of a solar cell device. Various techniques may be used to form the active regions of the solar cell and the metal contact structure.

Abstract: A silicon wafer which achieves a gettering effect without occurrence of slip dislocations is provided, and the silicon wafer is subject to heat treatment after slicing from a silicon monocrystal ingot so that a layer which has zero light scattering defects according to the 90° light scattering method is formed in a region at a depth from the wafer surface of 25 ?m or more but less than 100 ?m, and a layer which has a light scattering defect density of 1×108/cm3 or more according to the 90° light scattering method is formed in a region at a depth of 100 ?m from the wafer surface.

Abstract: The present invention is related to a method for manufacturing a low defect interface between a dielectric material and an III-V compound. More specifically, the present invention relates to a method for manufacturing a passivated interface between a dielectric material and an III-V compound. The present invention is also directed to a device comprising a low defect interface between a dielectric material and an III-V compound that has improved performance.

Abstract: Methods for depositing a microcrystalline silicon film layer with improved deposition rate and film quality are provided in the present invention. Also, a photovoltaic (PV) cell having a microcrystalline silicon film is provided. In one embodiment, the method produces a microcrystalline silicon film on a substrate at a deposition rate greater than about 20 nm per minute, wherein the microcrystalline silicon film has a crystallized volume between about 20 percent to about 80 percent.

Abstract: A method is provided for growing mono-crystalline nanostructures onto a substrate. The method comprises at least the steps of first providing a pattern onto a main surface of the substrate wherein said pattern has openings extending to the surface of the substrate, providing a metal into the openings of the pattern on the exposed main surface, at least partly filling the opening with amorphous material, and then annealing the substrate at temperatures between 300° C. and 1000° C. thereby transforming the amorphous material into a mono-crystalline material by metal mediated crystallization to form the mono-crystalline nanostructure.

Abstract: A method for forming a passivated densified nanoparticle thin film on a substrate in a chamber is disclosed. The method includes depositing a nanoparticle ink on a first region on the substrate, the nanoparticle ink including a set of Group IV semiconductor particles and a solvent. The method also includes heating the nanoparticle ink to a first temperature between about 30° C. and about 400° C., and for a first time period between about 1 minute and about 60 minutes, wherein the solvent is substantially removed, and a porous compact is formed. The method further includes flowing an oxidizer gas into the chamber; and heating the porous compact to a second temperature between about 600° C. and about 1000° C., and for a second time period of between about 5 seconds and about 1 hour; wherein the passivated densified nanoparticle thin film is formed.

Abstract: Methods and devices are provided for transforming non-planar or planar precursor materials in an appropriate vehicle under the appropriate conditions to create dispersions of planar particles with stoichiometric ratios of elements equal to that of the feedstock or precursor materials, even after selective forces settling. In particular, planar particles disperse more easily, form much denser coatings (or form coatings with more interparticle contact area), and anneal into fused, dense films at a lower temperature and/or time than their counterparts made from spherical nanoparticles. These planar particles may be nanoflakes that have a high aspect ratio. The resulting dense films formed from nanoflakes are particularly useful in forming photovoltaic devices.

Abstract: A method for producing a thin film promoter layer is disclosed. The method includes depositing a Group IV semiconductor ink on a substrate, the Group IV semiconductor ink including a set of Group IV semiconductor nanoparticles and a set of metal nanoparticles to form a porous compact. The method also includes heating the substrate to a first temperature between about 350° C. to about 765° C. and for a first time period between 5 min to about 3 hours.

Abstract: A method of manufacturing a donor sheet for transferring a transfer layer having a prescribed shape onto a receiving substrate, wherein: a step for forming an organic semiconductor precursor wherein a solution in which the organic semiconductor precursor which converts to an organic semiconductor due to heat, is coated on a substrate sheet; a step for forming a transfer layer of a prescribed shape by heating the organic semiconductor precursor layer in the prescribed shape to convert the organic semiconductor precursor layer to the organic semiconductor; and a step for removing the organic semiconductor precursor that is not converted to the organic semiconductor are performed in that order.

Abstract: The present invention relates to a method for pattern formation and an apparatus for pattern formation, the method comprising: applying, between partition lines for pattern formation formed on a surface of a base member, a resin composition for pattern formation having small compatibility or substantially no compatibility with a resin forming the partition lines for pattern formation, in a state in which the surface of the base member with the partition lines for pattern formation formed whereon is placed face down; maintaining the state in which the resin composition for pattern formation is held on the surface of the base member that is placed face down in order to form the resin composition for pattern formation applied between the partition lines for pattern formation into a downward convex shape; and curing the resin composition for pattern formation that is formed into the downward convex shape in order to form a pattern.

Abstract: The invention relates to a method for producing electronic components in a vacuum. The aim of the invention is to create flexible electronic components that have an optimum action, are cost-effective, and easy to produce in a single working cycle. To this end, a carrier film (12) is partially and/or selectively compressed with a blocking liquid, and is subjected to cathodic sputtering. A metallic layer is deposited on the carrier film (12) in the region free of the blocking layer, and the blocking liquid is evaporated during the evaporation process. A semiconductor agent is applied to the coated carrier film (12) during another evaporation process, and a coating with acrylate is then carried out. The carrier liquid is then partially and/or selectively reapplied to the acrylate layer and a cathodic sputtering is carried out. The cited coating processes are optionally repeated, and connections can be established between the individual metallized layers.

Abstract: A method of subjecting a silicon wafer doped with boron to a heat treatment in an argon atmosphere, wherein the argon atmosphere is replaced with a hydrogen atmosphere or a mixed gas of an argon gas and a hydrogen gas in a proper fashion, to thereby uniformize a boron concentration in the thickness direction of the surface layer of the silicon wafer doped with boron.

Abstract: A method of manufacturing an electronic component comprising at least one n- or p-doped portion, comprising the steps of: co-depositing inorganic semi-conducting nanoparticles and dopant on a substrate, the nanoparticles being a group four element such as silicon or germanium; fusing the nanoparticles by heating to form a continuous layer; and subsequently; and, recrystallising the layer.

Abstract: Methods and devices are provided for transforming non-planar or planar precursor materials in an appropriate vehicle under the appropriate conditions to create dispersions of planar particles with stoichiometric ratios of elements equal to that of the feedstock or precursor materials, even after selective forces settling. In particular, planar particles disperse more easily, form much denser coatings (or form coatings with more interparticle contact area), and anneal into fused, dense films at a lower temperature and/or time than their counterparts made from spherical nanoparticles. These planar particles may be nanoflakes that have a high aspect ratio. The resulting dense films formed from nanoflakes are particularly useful in forming photovoltaic devices.

Abstract: Method for manufacturing a semiconductor optical device includes forming an epitaxial structure containing at least an active layer which can emit light, of a III-V group semiconductor material; forming an insulating layer over the epitaxial structure, which prevents the V group element from escaping from the epitaxial structure during heat treatment; heat treating the epitaxial structure at at least 800 degrees C.; and removing the insulating layer, thereby enhancing the reliability of the device.

Abstract: This invention relates to a method for producing group IB-IIA-VIA quaternary or higher alloy semiconductor films wherein the method comprises the steps of (i) providing a metal film comprising a mixture of group IB and group IIIA metals; (ii) heat treating the metal film in the presence of a source of a first group VIA element (said first group VIA element hereinafter being referred to as VIA1) under conditions to form a first film comprising a mixture of at least one binary alloy selected from the group consisting of a group IB-VIA1 alloy and a group IIIA-VIA1 alloy and at least one group IB-IIIA-VIA1 ternary alloy (iii) optionally heat treating the first film in the presence of a source of a second group VIA element (said second group VI element hereinafter being referred to as VIA2) under conditions to convert the first film into a second film comprising at least one alloy selected from the group consisting of a group IB-VIA1-VIA2 alloy and a group IIIA-VIA1-VIA2 alloy; and the at least one group IB-III-VI

Abstract: Semiconductor wafers composed of monocrystalline silicon and doped with nitrogen contain an OSF region and a PV region, wherein the OSF region extends from the center radially toward the edge of the wafer as far as the Pv region; the wafer has an OSF density of less than 10 cm?2, a BMD density in the bulk of at least 3.5×108 cm?3, and a radial distribution of the BMD density with a fluctuation range BMDmax/BMDmim of not more than 3. The wafers are produced by controlling initial nitrogen content and maintaining oxygen within a narrow window, followed by a heat treatment.

Abstract: In a manufacturing method for a silicon wafer, a first heat treatment process is performed on the silicon wafer while introducing a first gas having an oxygen gas in an amount of 0.01 vol. % or more and 1.00 vol. % or less and a rare gas, and a second heat treatment process is performed while stopping introducing the first gas and introducing a second gas having an oxygen gas in an amount of 20 vol. % or more and 100 vol. % or less and a rare gas. In the first heat treatment process, the silicon wafer is rapidly heated to first temperature of 1300° C. or higher and a melting point of silicon or lower at a first heating rate, and kept at the first temperature. In the second heat treatment process, the silicon wafer is kept at the first temperature, and rapidly cooled from the first temperature at a first cooling rate.

Abstract: A substrate, thermal treatment assembly and method of operating the thermal treatment assembly are described for controlling the temperature of a substrate. An electrical potential is applied across two or more locations on the substrate in order to generate an electrical current through a portion of the substrate, thereby altering a temperature of the substrate. The electrical current may dissipate electrical energy in the form of thermal energy due to the intrinsic resistance of the portion of substrate to the flow of electrical current.

Abstract: A compound semiconductor material for forming an active layer of a thin film transistor device is disclosed, which has a group II-VI compound doped with a dopant ranging from 0.1 to 30 mol %, wherein the dopant is selected from a group consisting of alkaline-earth metals, group IIIA elements, group IVA elements, group VA elements, group VIA elements, and transitional metals. The method for forming an active layer of a thin film transistor device by using the compound semiconductor material of the present invention is disclosed therewith.