Ion Implantation Patents (Class 438/506)
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Patent number: 6639233Abstract: An ion implantation apparatus includes an ion source for extracting ions therefrom at an extraction voltage, an acceleration pipe for accelerating the ions thus extracted at an acceleration voltage of VA and a momentum segregation magnet for selecting the ions having a specific momentum from the ions extracted from the acceleration pipe so that the desired ions are caused to be incident on a target. In the event that MI denotes the mass number of the desired ions, ZI denotes the valence thereof, MC denotes the mass number of noted impurity ions of the impurity ions generated an upstream side of the acceleration pipe, and ZC denotes the valence thereof, if the relationship that the value of MI·(VE+VA)/ZI and that of MC·VA/ZC are equal or approximately equal to each other is satisfied, one of the extraction voltage VE and the acceleration voltage VA is increased and the other thereof is decreased while the value of (VE+VA) is maintained substantially constant.Type: GrantFiled: August 9, 2002Date of Patent: October 28, 2003Assignee: Nissin Electric Co., Ltd.Inventor: Takatoshi Yamashita
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Patent number: 6620712Abstract: The present invention discloses an electro-optical device support on a substrate. The electro-optical device includes a sacrificial layer disposed on the substrate having a chamber-wall region surrounding and defining an optical chamber. The electro-optical device further includes a membrane layer disposed on top of the sacrificial layer having a chamber-removal opening surrounding and defining an electric tunable membrane for transmitting an optical signal therethrough. The electrically tunable membrane disposed on top of the optical chamber surrounded by the chamber wall regions. The chamber-wall region is doped with ion-dopants for maintaining the chamber-wall region for removal-resistance under a chamber-forming process performed through the chamber-removal opening. In a preferred embodiment, the chamber-wall region is a doped silicon dioxide region with carbon or nitrogen. In another preferred embodiment, the chamber-wall region is a nitrogen ion-doped SiNxOy region.Type: GrantFiled: November 12, 2001Date of Patent: September 16, 2003Assignee: INTPAX, Inc.Inventors: Liji Huang, Naiqian Han, Yahong Yao, Gaofeng Wang
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Patent number: 6613654Abstract: An integrated circuit has a multi-layer stack such as a gate stack or a digit line stack disposed on a layer comprising silicon. A conductive film is formed on the transition metal boride layer. A process for fabricating such devices can include forming the conductive film using a vapor deposition process with a reaction gas comprising fluorine. In the case of a gate stack, the transition metal boride layer can help reduce or eliminate the diffusion of fluorine atoms from the conductive film into a gate dielectric layer. Similarly, in the case of digit line stacks as well as gate stacks, the transition metal boride layer can reduce the diffusion of silicon from the polysilicon layer into the conductive film to help maintain a low resistance for the conductive film.Type: GrantFiled: December 19, 2000Date of Patent: September 2, 2003Inventors: Scott J. DeBoer, Husam N. Al-Shareef
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Patent number: 6599772Abstract: A solid-state pickup element achieves both improvement in sensitivity and reduction of pixel size and a method thereof, includes a first conductive type semiconductor area, which is formed at least so as to include the inside of the semiconductor substrate upward of the overflow barrier area inside the semiconductor substrate, and a charge accumulating area at the position corresponding to the first conductive type semiconductor area of the light receptive sensor part in the epitaxial layer on the semiconductor substrate. An overflow barrier area is formed in the semiconductor substrate, and the first conductive type semiconductor area is formed on the surface, respectively, wherein an epitaxial layer is formed on the semiconductor substrate, and a charge accumulating area is formed at the position corresponding to the first conductive type semiconductor area on the surface side of the epitaxial layer, thereby producing a solid-state pickup element.Type: GrantFiled: April 4, 2001Date of Patent: July 29, 2003Assignee: Sony CorporationInventor: Hideshi Abe
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Patent number: 6537887Abstract: An integrated circuit and a process for making the same are provided. The circuit has a nitrogen implanted emitter window, wherein the nitrogen has been implanted into the emitter window after the emitter window etch, but prior to the emitter conductor deposition. Nitrogen implantation is expected to minimize oxide growth variation.Type: GrantFiled: November 30, 2000Date of Patent: March 25, 2003Assignee: Agere Systems Inc.Inventors: Yih-Feng Chyan, Chung Wai Leung, Yi Ma, Demi Nguyen
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Publication number: 20030027411Abstract: A semiconductor device includes an isolation region which is formed in a semiconductor layer, and a resistance conductive layer which is in a sidewall shape. According to this semiconductor device, the resistance conductive layer having a high resistance can be obtained with a very small area. Thus, a novel semiconductor device including a resistance element can be provided.Type: ApplicationFiled: July 12, 2002Publication date: February 6, 2003Applicant: SEIKO EPSON CORPORATIONInventor: Masahiro Kanai
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Patent number: 6479313Abstract: Compound semiconductor material is irradiated with x-ray radiation to activate a dopant material. Active carrier concentration efficiency may be improved over known methods, including conventional thermal annealing. The method may be employed for III-V group compounds, including GaN-based semiconductors, doped with p-type material to form low resistivity p-GaN. The method may be further employed to manufacture GaN-based LEDs, including blue LEDs, having improved forward bias voltage and light-emitting efficiency.Type: GrantFiled: May 25, 2001Date of Patent: November 12, 2002Assignee: Kopin CorporationInventors: Jinlin Ye, Jyh-Chia Chen, Shirong Liao, Hong K. Choi, John C. C. Fan
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Patent number: 6465327Abstract: The invention relates to a method for producing a thin membrane, comprising the following steps: implanting gas species, through one surface of a first substrate (10) and through one surface of a second substrate (20), which in said substrates are able to create microcavities (11, 21) delimiting, for each substrate, a thin layer (13, 23) lying between these microcavities and the implanted surface, the microcavities being able, after their implantation, to cause detachment of the thin layer from its substrate; assembly of the first substrate (10) onto the second substrate (20) such that their implanted surfaces face one another; detaching each thin layer (13, 23) from its substrate (10, 20), the thin layers remaining assembled together to form said thin membrane. The invention also concerns a thin membrane structure obtained with this method.Type: GrantFiled: February 28, 2001Date of Patent: October 15, 2002Assignee: Commissariat a l'Energie AtomiqueInventors: Bernard Aspar, Michel Bruel, Claude Jaussaud, Chrystelle Lagahe
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Patent number: 6403452Abstract: In an ion implantation method using an ion implantation equipment having an extraction electrode and a post accelerator, ion is uniformly implanted into a shallow region from the surface of a sample by setting an applied volt. of the post accelerator higher than an applied volt. of the extraction electrode.Type: GrantFiled: February 22, 2000Date of Patent: June 11, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Murakoshi, Kyoichi Suguro
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Patent number: 6387779Abstract: The present invention relates to a method of crystallizing a silicon film, a thin film transistor, and a fabricating method thereof using the same. More particularly, the present invention relates forming a crystalline silicon film by crystallizing a silicon film using laser energy, and a thin film transistor and a fabricating method thereof using the same. The present invention includes forming a buffer layer on a substrate and forming an amorphous silicon film on the buffer layer wherein the amorphous silicon film includes a first region and second regions connected to both ends of the first region. The buffer layer is etched to a degree by using the amorphous silicon as a mask, wherein a space is formed under the first region and a central part of the second region contacts a remaining portion of the buffer layer. The amorphous silicon film is then crystallized.Type: GrantFiled: April 14, 2000Date of Patent: May 14, 2002Assignee: LG. Philips LCD Co., LTDInventors: Jonghoon Yi, Sanggul Lee
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Publication number: 20020016049Abstract: A process is described which allows a buried, retrograde doping profile or a delta doping to be produced in a relatively simple and inexpensive way. The process uses individual process steps that are already used in the mass production of integrated circuits and accordingly can be configured for a high throughput.Type: ApplicationFiled: July 12, 2001Publication date: February 7, 2002Inventors: Giuseppe Curello, Jurgen Faul
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Patent number: 6337239Abstract: A layer configuration includes a material layer and a diffusion barrier which blocks diffusing material components. The barrier is disposed in the vicinity of a layer boundary of the material layer and is formed predominantly in grain boundaries of the material layer. A process for producing a diffusion barrier is also provided.Type: GrantFiled: September 8, 1999Date of Patent: January 8, 2002Assignee: Siemens AktiengesellschaftInventors: Christine Dehm, Carlos Mazure-Espejo
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Patent number: 6268271Abstract: A method for forming a plurality of buried layers inside a semiconductor device is disclosed. The method includes the following steps. Firstly, a semiconductor substrate is provided. Then, the first type p+-type ions are implanted into the semiconductor substrate to form the p+-type region under the surface of semiconductor substrate. The semiconductor substrate is etched to form a plurality of concave portions and a plurality of convex portions using the first photoresist. The n+-type ions are second implanted into the semiconductor substrate as a plurality of n+-type region. Next, the oxide layer is deposited over the surface of the plurality of concave portions and the surface of the plurality of convex portions. The plurality of n+-type regions are heated to form as the buried layers. The oxide layer is removed. Finally, a silicon layer is formed to fill the plurality of concave of portions a silicon layer and to cover the surface of the plurality of convex portions.Type: GrantFiled: May 31, 2000Date of Patent: July 31, 2001Assignee: United Microelectronics Corp.Inventor: Kuen-Shyi Tsay
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Patent number: 6251754Abstract: The invention provides a number of semiconductor substrate manufacturing methods with which, in manufacturing a semiconductor substrate having a semiconductor layer in an insulated state on a supporting substrate, it is possible to obtain a thick semiconductor layer with a simple process and cheaply while reducing impurity contamination of the semiconductor layer to a minimum.Type: GrantFiled: May 8, 1998Date of Patent: June 26, 2001Assignee: Denso CorporationInventors: Hisayoshi Ohshima, Masaki Matsui, Kunihiro Onoda, Shoichi Yamauchi
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Patent number: 6124146Abstract: A method of depositing a material to a semiconductor device having a first mesa structure, a second mesa structure and a valley. Material is deposited from a first angular direction sufficient to substantially mask the valley with a first of the mesa structures and from a second angular direction sufficient to substantially mask the valley with the second mesa structure to form a first lip and a second lip on the respective first and second mesa structures overlying the valley and defining a space therebetween less than the width of the valley. Material is then deposited to the device from a third direction in substantial opposition to the device, the space operating to guide material deposition to the valley to provide discrete material deposition in the valley to form a discrete feature in the valley.Type: GrantFiled: May 15, 1998Date of Patent: September 26, 2000Assignee: Motorola, Inc.Inventor: Kumar Shiralagi
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Patent number: 6110841Abstract: A method for avoiding plasma damage. In a semiconductor substrate of a first conductive type, a second conductive type well is formed. While forming the second conductive well, a high-energy dopant is doped into the semiconductor substrate. The high energy makes a depletion region between the substrate and the well have defects. A leakage path is thus formed. The leakage path can direct any charged carriers coming from plasma to avoid accumulation of the charged carriers in the well. Thus, the electrical characteristics of the well or even the quality of gate oxide formed thereon is prevented from being degraded.Type: GrantFiled: October 14, 1999Date of Patent: August 29, 2000Assignees: United Microelectronics Corp., United Silicon IncorporatedInventors: Mu-Chun Wang, Yih-Jau Chang
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Patent number: 6057214Abstract: A silicon-on-insulator trench isolation structure is disclosed that includes an active silicon-on-insulator region, an active bulk substrate region, and a trench region positioned between the active silicon-on-insulator region and the active bulk substrate region. The active silicon-on-insulator region is provided with a silicon-on-insulator film (42) positioned above a buried insulator layer (32). The active bulk substrate region may be provided between two trench regions such as a trench region (20) and a trench region (22). The trench region (20) is positioned between the active silicon-on-insulator region and the active bulk substrate region.Type: GrantFiled: December 9, 1997Date of Patent: May 2, 2000Assignee: Texas Instruments IncorporatedInventor: Keith A. Joyner
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Patent number: 6036772Abstract: A method for making a semiconductor device comprises: depositing at least one Group II-VI compound semiconductor layer comprising at least one Group II element selected from the group consisting of zinc, magnesium, manganese, beryllium, cadmium and mercury and at least one Group VI element selected from the group consisting of oxygen, sulfur, selenium and tellurium onto a Group III-V compound semiconductor layer comprising at least one Group III element selected from the group consisting of gallium, aluminum, boron and indium and at least one Group V element selected from the group consisting of nitrogen, phosphorus, arsenic, antimony and bismuth; whereinbefore depositing the Group II-VI compound semiconductor layer, a particle beam composed of at least one Group II element selected from the group consisting of zinc, magnesium, beryllium, cadmium and mercury is radiated onto the Group III-V compound semiconductor layer in a dose of 8.times.10.sup.-4 Torr.multidot.sec or more.Type: GrantFiled: December 29, 1997Date of Patent: March 14, 2000Assignee: Sony CorporationInventors: Tomonori Hino, Satoshi Taniguchi, Satoshi Ito
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Patent number: 5950097Abstract: An oxide layer is thermally grown over a semiconductor body, and openings are etched in the oxide layer to expose portions of the surface of the semiconductor body. Then, epitaxial regions are grown from the semiconductor body into the openings in the oxide layer, which epitaxial regions will eventually become the active regions of devices.Type: GrantFiled: August 16, 1996Date of Patent: September 7, 1999Assignee: Advanced Micro Devices, Inc.Inventors: Kuang-Yeh Chang, Yowjuang William Liu, Mark I. Gardner, Frederick N. Hause
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Patent number: 5882950Abstract: A fabrication method for a horizontal direction semiconductor PN junction array which can be achieved when an epitaxial layer is grown by a metalorganic chemical vapor deposition (MOCVD method) by introducing (or doping) a small amount of CCl.sub.4 or CBr.sub.4 gas, includes forming a recess on an N type GaAs substrate by using a non-planar growth, performing a growth method of a P type epitaxial layer on the N type GaAs substrate by a metalorganic chemical vapor deposition method, and forming a horizontal direction PN junction array of P-GaAs/N-GaAs or P-AlGaAs/N-GaAs by introducing a gas comprising CCl.sub.4 or CBr.sub.4 .Type: GrantFiled: December 27, 1996Date of Patent: March 16, 1999Assignee: Korea Institute Of Science And TechnologyInventors: Suk-Ki Min, Seong-Il Kim, Eun Kyu Kim
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Patent number: 5856208Abstract: The present invention relates to an epitaxial wafer including a PN junction, which is improved in terms of light output and can have a good-enough ohmic electrode formed thereon. Epitaxial layers are formed of GaAs.sub.1-x P.sub.x where 0.45 <.times..ltoreq.1). A first P-type layer is formed by a vapor-phase growth process, and a second P-type layer is formed on the first P-type layer by a thermal diffusion process, said second P-type layer having a carrier concentration higher than that of said first P-type layer.Type: GrantFiled: June 3, 1996Date of Patent: January 5, 1999Assignee: Mitsubishi Chemical CorporationInventors: Tadashige Sato, Megumi Imai, Hitora Takahashi
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Patent number: 5834331Abstract: A p-i-n structure for use in photoconductors and diodes is disclosed, being formed of an Al.sub.x Ga.sub.1-x N alloy (X=0.fwdarw.1) with In.sub.y Ga.sub.1-Y N (Y=0.fwdarw.1) which as grown by MOCVD procedure with the p-type layer adjacent the substrate. In the method of the subject invention, buffer layers of p-type material are grown on a substrate and then doped. The active, confinement and cap layers of n-type material are next grown and doped. The structure is masked and etched as required to expose a surface which is ion implanted and annealed. A p-type surface contact is formed on this ion-implanted surface which is of sufficiently low resistance as to provide good quality performance for use in a device.Type: GrantFiled: October 17, 1996Date of Patent: November 10, 1998Assignee: Northwestern UniversityInventor: Manijeh Razeghi
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Patent number: 5789273Abstract: After a compound semiconductor layer including InP is formed on a semiconductor substrate, a compound semiconductor layer including As is epitaxially grown by metal organic chemical vapor deposition method using an organic As as the material for feeding the As.Type: GrantFiled: March 21, 1996Date of Patent: August 4, 1998Assignee: Sony CorporationInventor: Tadashi Yamamoto