Abstract: The present invention involves a system and method of remotely detecting the presence of a wafer comprising, a passive RFID circuit, wherein the RFID circuit is attached to an end of a transfer arm located inside a vacuum chamber of an ion implantation system, a reader located outside the vacuum chamber, and wherein the RFID tag provides an indication relating to whether or not a wafer is secured by the transfer arm.

Abstract: In an ion implantation method, a substrate is placed in a process zone and ions are implanted into a region of the substrate to form an ion implanted region. A porous capping layer is deposited on the ion implanted region. The substrate is annealed to volatize at least 80% of the porous capping layer overlying the ion implanted region during the annealing process. An intermediate product comprises a substrate, a plurality of ion implantation regions on the substrate, and a porous capping layer covering the ion implantation regions.

Abstract: A method of preparing nanorod arrays using ion beam implantation is described that includes defining a pattern on a substrate and then implanting ions into the substrate using ion beam implantation. Next, a thin film is deposited on the substrate. During film growth, nanotrenches form and catalyze the formation of nanorods through capillary condensation. The resulting nanorods are aligned with the supporting matrix and are free from lattice and thermal strain effect. The density, size, and aspect ratios of the nanorods can be varied by changing the ion beam implantation and thin film growth conditions resulting in control of emission efficiency.

Abstract: A method of manufacturing a semiconductor device comprises the steps of, in sequence: depositing a first silicon layer; patterning the first silicon layer to obtain a first silicon region; implanting a first dopant into a first part of the first silicon region, the first part of the first silicon region defined using a first mask; depositing a second silicon layer; patterning the second silicon layer to obtain a second silicon region; and implanting a second dopant into a second part of the first silicon region, the second part of the first silicon region defined by the first mask and the second silicon region. A device comprises a semiconductor layer (6); a first doped region (5) within the semiconductor layer; a second doped region (7) within the first doped region (5); and a silicon layer (9) disposed over a part of the semiconductor layer; wherein the silicon layer is disposed over a part of the first doped region (5) but not over the second doped region (7).

Abstract: The present invention provides a method of manufacturing a bonded wafer. The method comprises an oxidation step in which an oxide film is formed on at least one surface of a base wafer, a bonding step in which the base wafer on which the oxide film has been formed is bonded to a top wafer to form a bonded wafer, and a thinning step in which the top wafer included in the bonded wafer is thinned. The oxidation step comprises heating the base wafer to a heating temperature ranging from 800 to 1300° C. at a rate of temperature increase ranging from 1 to 300° C./second in an oxidizing atmosphere, and the bonding step is carried out so as to position the oxide film formed in the oxidation step at an interface of the top wafer and the base wafer.

Abstract: A method of forming a nitride semiconductor through ion implantation and an electronic device including the same are disclosed. In the method, an ion implantation region composed of a line/space pattern is formed on a substrate at an ion implantation dose of more than 1E17 ions/cm2 to 5E18 ions/cm2 or less and an ion implantation energy of 30˜50 keV, and a metal nitride thin film is grown on the substrate by epitaxial lateral overgrowth, thereby decreasing lattice defects in the metal nitride thin film. Thus, the electronic device has improved efficiency.

Abstract: A method for making a transistor within a semiconductor wafer. The method may include etching a recess at source/drain extension locations and depositing amorphous silicon within the recess to from amorphous silicon source/drain extensions. Dopants may be implanted into the amorphous silicon source/drain extensions and the semiconductor wafer may then be annealed.

Abstract: In a plasma immersion ion implantation process, the thickness of a pre-implant chamber seasoning layer is increased (to permit implantation of a succession of wafers without replacing the seasoning layer) without loss of wafer clamping electrostatic force due to increased seasoning layer thickness. This is accomplished by first plasma-discharging residual electrostatic charge from the thick seasoning layer. The number of wafers which can be processed using the same seasoning layer is further increased by fractionally supplementing the seasoning layer after each wafer is processed, which may be followed by a brief plasma discharging of the supplemented seasoning before processing the next wafer.

Abstract: An asymmetric semiconductor device (3) that includes an integrated high voltage diode (72), including: a substrate comprising an epitaxial layer (47) and a deep well implant (42) of a first type patterned above the epitaxial layer; a shallow trench isolation (STI) region (46) separating a cathode from an anode; a first well implant (40) of a second type residing below the anode; and a deep implant mask (34) of the second type patterned above the deep well implant and below both the cathode and a portion of the STI region.

Abstract: An implanter provides two-dimensional scanning of a substrate relative to an implant beam so that the beam draws a raster of scan lines on the substrate. The beam current is measured at turnaround points off the substrate and the current value is used to control the subsequent fast scan speed so as to compensate for the effect of any variation in beam current on dose uniformity in the slow scan direction. The scanning may produce a raster of non-intersecting uniformly spaced parallel scan lines and the spacing between the lines is selected to ensure appropriate dose uniformity.

Abstract: In a process for producing a semiconductor chip, a functional semiconductor layer sequence (2) is grown epitaxially on a growth substrate (1). Then, a separating zone (4), which lies parallel to a main surface (8) of the growth substrate (1), is formed in the growth substrate (1) by ion implantation, the ion implantation taking place through the functional semiconductor layer sequence (2). Then, a handle substrate (6) is applied to the functional semiconductor layer sequence (2), and a part of the growth substrate (1) which is remote from the handle substrate (6) as seen from the separating zone (4), is detached along the separating zone (4).

Abstract: A process can include forming a doped semiconductor layer over a substrate. The process can also include performing an action that reduces a dopant content along an exposed surface of a workpiece that includes the substrate and the doped semiconductor layer. The action is performed after forming the doped semiconductor layer and before the doped semiconductor layer is exposed to a room ambient. In particular embodiments, the doped semiconductor layer includes a semiconductor material that includes a combination of at least two elements selected from the group consisting of C, Si, and Ge, and the doped semiconductor layer also includes a dopant, such as phosphorus, arsenic, boron, or the like. The action can include forming an encapsulating layer, exposing the doped semiconductor layer to radiation, annealing the doped semiconductor layer, or any combination thereof.

Abstract: Random number generating method for generating random numbers in accordance with multivariate non-normal distributions based on the Yuan and Bentler method I on computer. The method includes application steps for applying n-dimensional multivariate non-normal distributions to n-dimensional experience distribution by using computer and steps for generating random numbers including pseudo-random numbers, quasi-random numbers, low discrepancy sequences, and physical random numbers by methods including additive generator method, M-sequence, generalized feedback shift-register method, and Mersenne Twister, and excluding congruential method, by using computer. The application steps use predetermined relationship equations for the third and fourth order moments to perform application associated with the third and fourth order moments of the empirical distributions. Moreover, by using random numbers generation method, parameters are estimated by maximum likelihood method.

Abstract: A stress relaxed monocrystalline layer structure is made on a nonlattice matched substrate by first applying to the substrate epitaxially a monocrystalline layer structure comprising at least one layer, the monocrystalline layer structure forming with the substrate an interface that has a greater lattice parameter mismatch on the substrate than within the monocrystalline layer structure. The monocrystalline layer is irradiated by directing an ion beam to generate predominantly point effects in the monocrystalline layer structure and an extended defect region in the substrate proximal to the monocrystalline layer structure. Then the monocrystalline layer structure is thermally treated in a temperature range of 550° C. to 1000° C. in an inert, reducing or oxidizing atmosphere so that the monocrystalline layer structure above the extended defect region is stress relaxed and has a defect density less than 106 cm?2 and a surface roughness of less than 1 nm.

Abstract: Impurity concentration (Nd(X)) in an n-drift layer in a diode is at a maximum at a position at a distance Xp from an anode electrode in a direction from the anode electrode to a cathode electrode, and gradually decreases from the position toward each of the anode electrode and the cathode electrode. A ratio of the peak impurity concentration Np to an averaged impurity concentration Ndm in the n-drift layer is in the range of 1 to 5. This provides a diode and a manufacturing method thereof by which oscillations in voltage and current at reverse recovery are inhibited to achieve enhancement both in high speed and low-loss characteristics and in soft recovery characteristics.

Abstract: Methods of fabricating semiconductor devices are provided. An NMOS transistor and a PMOS transistor are provided on a substrate. The NMOS transistor is positioned on an NMOS region of the substrate and the PMOS transistor is positioned on a PMOS region of the substrate. A first insulating layer is provided on the NMOS transistor. The first insulating layer has a first compressive stress. A second insulating layer is provided on the PMOS transistor. The second insulating layer has a second compressive stress and a stress relief ratio higher than a stress relief ratio of the first insulating layer. A thermal treatment process is performed on the first insulating layer and the second insulating layer such that the second compressive stress of the second insulating layer is lower than the first compressive stress of the first insulating layer. Related devices are also provided.

Abstract: A method is disclosed of forming an extension region for a transistor having a gate structure overlying a compound semiconductor layer. An anneal is used either before or after deep source/drain implantation to diffuse a dopant from a raised region adjacent the gate structure to a location underlying the gate structure. A non-diffusing activation process can be used to activate source/drain implants when the dopants from the raised region are diffused prior to deep source/drain implantation.

Abstract: A method to fabricate patterned strain-relaxed SiGe epitaxial with threading dislocation density control is provided. An ion-implanting area is first defined on a silicon substrate, and then proceeds ion-implanting. Finally, a buffer layer and a SiGe epitaxial layer are deposited. According to the disclosure, an active area and a non-active area are defined through ion-implanting. Therefore, the threading dislocation occurring in the active area concentrates in the non-active area, and the density of the threading dislocation is lowered. Furthermore, the performance of the semiconductor is also enhanced.

Abstract: A semiconductor substrate is patterned to form a depression and prominence. A floating gate is formed so as to cover at least both sidewalls of the prominence of the depression and prominence, and is then etched to form a trench for a device isolation self-aligned with the floating gate. Related structures are also described.

Abstract: In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extension structure is previously obtained. This correspondence satisfies that the transistor has a given threshold voltage. After formation of the gate electrode and measurement of the size of the gate electrode, ion implantation conditions or heat treatment conditions for forming the drain extension structure are set based on the previously-obtained correspondence and the measured size of the gate electrode. Ion implantation or heat treatment for forming the drain extension structure is performed under the ion implantation conditions or heat treatment conditions that have been set.

Abstract: By using a combination of solid phase epitaxy re-growth and laser annealing, the present invention provides a low thermal budget method which allows the crystal lattice of a semiconductor surface to recover after the doping by ion implantation. The low thermal budget limits the out-diffusion of the dopants ions, thus avoiding the enlargement of the doped source/drain regions. Therefore, the method is suited, for instance, for the fabrication of ultra-shallow source/drain regions in MOS transistors elements. The method according to the present invention comprises a first pre-amorphization process in order to limit channeling effects, a doping process by ion implantation and a re-crystallization by solid phase epitaxy, followed by laser annealing.

Abstract: Methods of forming a single crystal semiconductor thin film on an insulator and semiconductor devices fabricated thereby are provided. The methods include forming an interlayer insulating layer on a single crystal semiconductor layer. A single crystal semiconductor plug is formed to penetrate the interlayer insulating layer. A semiconductor oxide layer is formed within the single crystal semiconductor plug using an ion implantation technique and an annealing technique. As a result, the single crystal semiconductor plug is divided into a lower plug and an upper single crystal semiconductor plug with the semiconductor oxide layer being interposed therebetween. That is, the upper single crystal semiconductor plug is electrically insulated from the lower plug by the semiconductor oxide layer. A single crystal semiconductor pattern is formed to be in contact with the upper single crystal semiconductor plug and cover the interlayer insulating layer.

Abstract: The present invention provides a method for implanting ions in a substrate and a method for manufacturing an integrated circuit. The method for implanting ions in a substrate, among other steps, including placing a substrate (410) on an implant platen (405) such that a predominant axes (430) of the substrate (410) is rotated about 30 degrees to about 60 degrees or about 120 degrees to about 150 degrees offset from a radial with respect to the implant platen (405), and further wherein the substrate (410) is not tilted. The method further includes implanting ions into the substrate (410), the rotated position of the predominant axes (430) reducing shadowing.

Abstract: A method for forming a semiconductor substrate that can be dismantled, comprising the following steps: introduction of gaseous species in the substrate according to conditions enabling the constitution of an embrittled layer by the presence in said layer of micro-cavities and/or micro-bubbles, a thin layer of semiconductor material thus being delimited between the embrittled layer and one face of the substrate, thermal treatment of the substrate to increase the brittleness level of the embrittled layer, said thermal treatment being continued until the appearance of local deformations on said face of the substrate in the form of blisters but without generating exfoliations of the thin layer during this step and during the continuation of the method, epitaxy of semiconductor material on said face of the substrate to provide at least one epitaxial layer on said thin film.

Abstract: A method to achieve controlled conductivity in microfluidic devices, and a device formed thereby. The method comprises forming a microchannel or a well in an insulating material, and ion implanting at least one region of the insulating material at or adjacent the microchannel or well to increase conductivity of the region.

Abstract: A method for producing an SOI wafer by the hydrogen ion delamination method comprising at least a step of bonding a base wafer and a bond wafer having a micro bubble layer formed by gas ion implantation and a step of delaminating a wafer having an SOI layer at the micro bubble layer as a border, wherein, after the delamination step, the wafer having an SOI layer is subjected to a two-stage heat treatment in an atmosphere containing hydrogen or argon utilizing a rapid heating/rapid cooling apparatus (RTA) and a batch processing type furnace. Preferably, the heat treatment by the RTA apparatus is performed first. Surface roughness of an SOI layer surface delaminated by the hydrogen ion delamination method is improved over the range from short period to long period, and SOI wafers free from generation of pits due to COPs in SOI layers are efficiently produced with high throughput.

Abstract: A plurality of memory cell devices is formed by using an intermediate dual polysilicon-nitride control electrode stack overlying nanoclusters. The stack includes a first-formed polysilicon-nitride layer and a second-formed polysilicon-containing layer. The second-formed polysilicon-containing layer is removed from areas containing the plurality of memory cells. In one form the second-formed polysilicon-containing layer also contains a nitride portion which is also removed, thereby leaving the first-formed polysilicon-nitride layer for the memory cell devices. In another form the second-formed ploysilicon-containing layer does not contain nitride and a nitride portion of the first-formed polysilicon-nitride layer is also removed. In the latter form a subsequent nitride layer is formed over the remaining polysilicon layer. In both forms a top portion of the device is protected from oxidation, thereby preserving size and quality of underlying nanoclusters.

Abstract: A method for implanting atomic species through an uneven surface of a semiconductor layer. The technique includes applying a covering layer upon the uneven surface in an amount sufficient and in a manner to increase surface uniformity. The method also includes implanting atomic species through the covering layer and uneven surface to obtain a more uniform depth of implantation of the atomic species in the layer.

Abstract: A method of monitoring and adjusting the position of a wafer with respect to an ion beam including setting the position of a wafer holder so that a wafer to be held therein is positioned at a tilt angle of 45 degrees and a twist angle of 45 degrees with respect to the path of an ion beam; positioning a n-type wafer without screen oxide in the wafer holder; implanting boron species into a region of the wafer at 160 KeV and a dose level of 5.0×1013 atoms/cm2; periodically measuring the sheet resistivity of a implanted wafer and readjusting the wafer tilt angle when the sheet resistivity is greater than 30 ohms/square.

Abstract: The present invention provides a method of forming a liquid crystal display (LCD). Active layers of N-type and P-type low temperature polysilicon thin film transistors and a bottom electrode of a storage capacitor are formed first. Then a N-type source/drain is formed and the bottom electrode is doped with dopants. A gate insulator, a gate electrode, a capacitor dielectric, and a top electrode are thereafter formed. After that, a P-type source/drain is formed. Finally, a source interconnect, a drain interconnect, and a pixel electrode of the liquid crystal display are formed.

Abstract: A method is provided for manufacturing a semiconductor device having a high breakdown voltage transistor and a low breakdown voltage transistor with different driving voltages provided in a common layer. The method includes: (a) implanting an impurity of a second conductivity type in a specified region of a semiconductor layer of a first conductivity type to form a first well; (b) implanting an impurity of the second conductivity type in a specified region of the semiconductor layer to form a second well having an impurity concentration different from the first well; and (c) implanting an impurity of the first conductivity type in a specified region of the first well to form a third well.

Abstract: A process for fabricating a semiconductor device having a buried layer comprises the steps of implanting an impurity ion into where the buried layer to be formed in a substrate, providing the substrate inside a reactor furnace, preparing a nonoxidizing atmosphere inside of the reactor furnace, annealing the substrate to activate and diffuse the implanted impurity ion region while increasing inside temperature of the reactor furnace up to a first temperature, and shifting the inside temperature of the reactor furnace from the first temperature to a second temperature in which a epitaxial crystal starts to grow and introducing a epitaxial growth gas into the reactor furnace to grow an epitaxial layer on a surface of the substrate.

Abstract: An integrated circuit has a multi-layer stack such as a gate stack or a digit line stack disposed on a layer comprising silicon. A conductive film is formed on the transition metal boride layer. A process for fabricating such devices can include forming the conductive film using a vapor deposition process with a reaction gas comprising fluorine. In the case of a gate stack, the transition metal boride layer can help reduce or eliminate the diffusion of fluorine atoms from the conductive film into a gate dielectric layer. Similarly, in the case of digit line stacks as well as gate stacks, the transition metal boride layer can reduce the diffusion of silicon from the polysilicon layer into the conductive film to help maintain a low resistance for the conductive film.

Abstract: In the manufacture of a semiconductor laser device, sequentially grown on a sapphire substrate in the following order are a buffer layer, a first undoped GaN layer, a first super lattice defect reducing layer, a second undoped GaN layer, a second super lattice defect reducing layer, a third undoped GaN layer, a third super lattice defect reducing layer and a fourth undoped GaN layer. A device structure is then formed thereon. The first to third super lattice defect reducing layers each include five pairs of InGaN and AlGaN films alternately placed on one another in this order.

Abstract: A resist material used to mask an underlying layer during an etch process is subjected to ion implantation to harden the resist material against damage from the etch process. In a particular embodiment, the resist material is compatible with exposure to 193 nm radiation for patterning the resist material.

Abstract: A buried bit line and a fabrication method thereof, wherein the device includes a substrate, a shallow doped region disposed in the substrate, a deep doped region disposed in the substrate below a part of the shallow doped region, wherein the shallow doped region and the deep dope region together form a bit line of the memory device.

Abstract: A method for producing an SOI wafer by the hydrogen ion delamination method comprising at least a step of bonding a base wafer and a bond wafer having a micro bubble layer formed by gas ion implantation and a step of delaminating a wafer having an SOI layer at the micro bubble layer as a border, wherein, after the delamination step, the wafer having an SOI layer is subjected to a two-stage heat treatment in an atmosphere containing hydrogen or argon utilizing a rapid heating/rapid cooling apparatus (RTA) and a batch processing type furnace. Preferably, the heat treatment by the RTA apparatus is performed first. Surface roughness of an SOI layer surface delaminated by the hydrogen ion delamination method is improved over the range from short period to long period, and SOI wafers free from generation of pits due to COPs in SOI layers are efficiently produced with high throughput.

Abstract: A metal wiring method for an undercut in a MEMS packaging process includes disposing a MEMS element on a silicon substrate, welding a glass wafer to an upper portion of the silicon substrate having the MEMS element disposed thereon, the glass wafer having a hole formed therein for connecting a metal wiring, depositing a thin metal film for the metal wiring in the hole, and ion-mealing the deposited thin metal film. By the ion-mealing, the method is capable of connecting a metal wiring to a via hole having an undercut.

Abstract: One aspect of this disclosure relates to a method for forming a strained silicon over silicon germanium (Si/SiGe) structure. In various embodiments, germanium ions are implanted into a silicon substrate with a desired dose and energy to be located beneath a surface silicon layer in the substrate. The implantation of germanium ions at least partially amorphizes the surface silicon layer. The substrate is heat treated to regrow a crystalline silicon layer over a resulting silicon germanium layer using a solid phase epitaxial (SPE) process. The crystalline silicon layer is strained by a lattice mismatch between the silicon germanium layer and the crystalline silicon layer. Other aspects are provided herein.

Abstract: A method is provided for fabricating a substrate for optics, electronics, or optoelectronics. This method includes the steps of transferring a seed layer to a support layer, depositing a working layer onto the seed layer to form a composite substrate and detaching the working layer and the seed layer from the support to form a substrate. Advantageously, the support substrate comprises a material having a thermal expansion value of about 0.7 to 3 times the coefficient value of the working layer.

Abstract: The present invention relates to a method of fabricating polysilicon film by Nickel and Copper induced lateral crystallization for the TFT-LCD, comprising the step of: a) a thin (˜4 nm) Copper and Nickel being evaporated onto the substrate; b) a amorphous-silicon film (˜50 nm) being evaporated onto thereof obtained according to a); c) applying annealing at less than 600° C. to thereof obtained according to b) for fast fabricating poly-silicon film. It is approximately 10 times faster than that of Ni induced polysilicon. The present invention is to provide a low-temperature (<600° C.) fast growth rate process to convert the hydrogenated amorphous silicon (a-Si:H) films to polysilicon film for substantially time-saving process and industrial applicability.

Abstract: In one embodiment, the threshold voltage of a first transistor is adjusted by implanting a dopant through a mask (e.g., photoresist material). The thickness of the mask may be varied to obtain a particular threshold voltage. The mask may be formed such that it covers a first transistor region where the first transistor is to be fabricated, while leaving a second transistor region exposed. This allows an implant step to adjust the threshold voltage of the first transistor and to form a well in the second transistor region.

Abstract: A wafer has a substrate defined with a first region and a second region. An ONO layer, a first silicon layer, and a silicon nitride layer are formed on the substrate in sequence. Then the ONO layer, the first silicon layer, and the silicon nitride layer disposed on the second region are removed. At least one gate oxide layer is formed on the second region and a second silicon layer is deposited on the wafer. After that, a photo-etching process is performed to remove the second silicon layer and the silicon nitride layer on the first region. At least a third silicon layer is formed on the wafer. Photo-etching processes and a plurality of ion implantation processes are then performed to form a gate, a drain, and a source of each MOS transistor on the substrate.

Abstract: Several methods for producing an active region for a long wavelength light emitting device are disclosed. In one embodiment, the method comprises placing a substrate in an organometallic vapor phase epitaxy (OMVPE) reactor, the substrate for supporting growth of an indium gallium arsenide nitride (InGaAsN) film, supplying to the reactor a group-III-V precursor mixture comprising arsine, dimethylhydrazine, alkyl-gallium, alkyl-indium and a carrier gas, where the arsine and the dimethylhydrazine are the group-V precursor materials and where the percentage of dimethylhydrazine substantially exceeds the percentage of arsine, and pressurizing the reactor to a pressure at which a concentration of nitrogen commensurate with light emission at a wavelength longer than 1.2 um is extracted from the dimethylhydrazine and deposited on the substrate.

Abstract: Structure and method for filling an opening in a semiconductor structure that is less susceptible to the formation of voids. A first layer of a first material is formed over the layer in which the opening is to be formed, and a faceted opening is formed in the first layer. The opening in the underlying layer is subsequently formed, and the material that is to fill the opening is deposited over the faceted opening and into the opening of the underlying layer.

Abstract: Methods and apparatus are provided for plasma doping and ion implantation in an integrated processing system. The apparatus includes a process chamber, a beamline ion implant module for generating an ion beam and directing the ion beam into the process chamber, a plasma doping module including a plasma doping chamber that is accessible from the process chamber, and a wafer positioner. The positioner positions a semiconductor wafer in the path of the ion beam in a beamline implant mode and positions the semiconductor wafer in the plasma doping chamber in a plasma doping mode.

Abstract: In an ion implantation method using an ion implantation equipment having an extraction electrode and a post accelerator, ion is uniformly implanted into a shallow region from the surface of a sample by setting an applied volt. of the post accelerator higher than an applied volt. of the extraction electrode.

Abstract: A silicon substrate is coated with one or more layers of resist. First and second circuit patterns are exposed in sequence, where the second pattern crosses the first pattern. The patterned resist layers are developed to open holes which extend down to the substrate only where the patterns cross over each other. These holes provide a mask suitable for implanting single phosphorous ions in the substrate, for a solid state quantum computer. Further development of the resist layers provides a mask for the deposition of nanoelectronic circuits, such as single electron transistors, aligned to the phosphorous ions.

Abstract: A method is provided for manufacturing a semiconductor device having a high breakdown voltage transistor and a low breakdown voltage transistor with different driving voltages provided in a common layer. The method includes: (a) implanting an impurity of a second conductivity type in a specified region of a semiconductor layer of a first conductivity type to form a first well; (b) implanting an impurity of the second conductivity type in a specified region of the semiconductor layer to form a second well having an impurity concentration different from the first well; and (c) implanting an impurity of the first conductivity type in a specified region of the first well to form a third well.

Abstract: A method fabricates an integrated semiconductor product. The first step is providing a semiconductor wafer that has preformed semiconductor components. The next step is forming at least one connection, in particular a polysilicon connection. The next step is exposing the at least one connection from the wafer front surface. The next step is applying a protective layer, in particular a silicon nitride protective layer, to the wafer front surface. The next step is treating the wafer front surface by a chemical mechanical polishing (CMP) step, with the result that the at least one connection is made accessible again.