Heat Treatment Patents (Class 438/509)
  • Patent number: 9666432
    Abstract: Atomic Layer Deposition (ALD) is used for heteroepitaxial film growth at reaction temperatures ranging from 80-400° C. The substrate and film materials are preferably selected to take advantage of Domain Matched Epitaxy (DME). A laser annealing system is used to thermally anneal deposition layers after deposition by ALD. In preferred embodiments a silicon substrate is overlaid with an AIN nucleation layer and laser annealed. Thereafter a GaN device layers is applied over the AIN layer by an ALD process and then laser annealed. In a further example embodiment a transition layer is applied between the GaN device layer and the AIN nucleation layer. The transition layer comprises one or more different transition material layers each comprising a AlxGa1-x compound wherein the composition of the transition layer is continuously varied from AIN to GaN.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: May 30, 2017
    Assignee: Ultratech, Inc.
    Inventors: Ganesh Sundaram, Andrew M. Hawryluk, Daniel Stearns
  • Patent number: 9633997
    Abstract: A semiconductor device, in which, in a density distribution of first conductivity type impurities in the first conductivity type region measured along a thickness direction of the semiconductor substrate, a local maximum value N1, a local minimum value N2, a local maximum value N3, and a density N4 are formed in this order from front surface side, a relationship of N1>N3>N2>N4 is satisfied, a relationship of N3/10>N2 is satisfied, and a distance “a” from the surface to the depth having the local maximum value N1 is larger than twice a distance “b” from the depth having the local maximum value N1 to the depth having the local minimum N2.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: April 25, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Satoru Kameyama, Shinya Iwasaki, Yuki Horiuchi, Shuhei Oki
  • Patent number: 9585195
    Abstract: An annealing apparatus includes: a temperature-gradient preheating unit, configured for performing a gradient-preheating process for a substrate that is to be annealed by using a gradient temperature; a high temperature heating unit, configured for performing a high temperature heating process for the preheated substrate; and a shifting device, configured for transporting the substrate from the temperature-gradient preheating unit to the high temperature heating unit when and/or after the substrate is subjected to the gradient-preheating process. The annealing apparatus adopts a gradient heating method to perform a preheating treatment for the substrate, so the annealing efficiency is increased. An annealing process that uses the annealing apparatus is further provided.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: February 28, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventor: Zuqiang Wang
  • Patent number: 9281189
    Abstract: Disclosed is a method of manufacturing a thin film, the method including: growing an epitaxial layer on a surface of a wafer at a growth temperature, wherein the growing of the epitaxial layer comprises controlling a defect present on a surface of the wafer. Also, disclosed is a wafer including: a substrate; and an epitaxial layer located on the substrate, wherein a basal dislocation density of the epitaxial layer is equal to or less than 1/cm2.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: March 8, 2016
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Moo Seong Kim
  • Patent number: 9224822
    Abstract: A layer of a silicon germanium alloy containing 30 atomic percent or greater germanium and containing substitutional carbon is grown on a surface of a semiconductor layer. The presence of the substitutional carbon in the layer of silicon germanium alloy compensates the strain of the silicon germanium alloy, and suppresses defect formation. Placeholder semiconductor fins are then formed to a desired dimension within the layer of silicon germanium alloy and the semiconductor layer. The placeholder semiconductor fins will relax for the most part, while maintaining strain in a lengthwise direction. An anneal is then performed which may either remove the substitutional carbon from each placeholder semiconductor fin or move the substitutional carbon into interstitial sites within the lattice of the silicon germanium alloy. Free-standing permanent semiconductor fins containing 30 atomic percent or greater germanium, and strain in the lengthwise direction are provided.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: December 29, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9053933
    Abstract: The invention relates to a method for forming a graphene layer (105) on the surface of a substrate (100) including a silicon layer (101), the method comprising the consecutive steps of: forming (1) a silicon-carbide film (103) on a free surface of the silicon layer and gradually heating the substrate until the silicon of at least the first row of atoms of the silicon-carbide film is sublimated so as to form the graphene layer on the silicon-carbide film. According to the invention, a silicon layer, the free surface of which is stepped, is used.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: June 9, 2015
    Assignee: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventor: Abdelkarim Ouerghi
  • Publication number: 20150132928
    Abstract: A technique for forming nanostructures including introducing a plurality of molecular-size scale and/or nanoscale building blocks to a region near a substrate and simultaneously scanning a pattern on the substrate with an energy beam, wherein the energy beam causes a change in at least one physical property of at least a portion of the building blocks, such that a probability of the portion of the building blocks adhering to the pattern scanned by the energy beam is increased, and wherein the building blocks adhere to the pattern to form the structure. The energy beam and at least a portion of the building blocks may interact by electrostatic interaction to form the structure.
    Type: Application
    Filed: January 20, 2015
    Publication date: May 14, 2015
    Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Joseph M. Jacobson, David Kong, Vikas Anant, Ashley Salomon, Saul Griffith, Will DelHagen, Vikrant Agnihotri
  • Patent number: 9023721
    Abstract: Bulk III-nitride semiconductor materials are deposited in an HPVE process using a metal trichloride precursor on a metal nitride template layer of a growth substrate. Deposition of the bulk III-nitride semiconductor material may be performed without ex situ formation of the template layer using a MOCVD process. In some embodiments, a nucleation template layer is formed ex situ using a non-MOCVD process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process. In additional embodiments, a nucleation template layer is formed in situ using an MOCVD process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process. In further embodiments, a nucleation template layer is formed in situ using an HVPE process prior to depositing bulk III-nitride semiconductor material on the template layer using an HVPE process.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: May 5, 2015
    Assignee: Soitec
    Inventors: Chantal Arena, Ronald Thomas Bertram, Ed Lindow
  • Patent number: 9023718
    Abstract: A method of fabricating a semiconductor device includes: forming an epitaxial layer on a semiconductor substrate; forming a capping layer having a first thickness on the epitaxial layer; and oxidizing the capping layer in an oxygen atmosphere to form a first gate dielectric layer having a second thickness.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: May 5, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Ho Do, Ha-Jin Lim, Weon-Hong Kim, Hoi-Sung Chung, Moon-Kyun Song, Dae-Kwon Joo
  • Patent number: 9018021
    Abstract: A layer is deposited onto a semiconductor wafer by CVD in a process chamber having upper and lower covers, wherein the wafer front side temperature is measured; the wafer is heated to deposition temperature; the temperature of the upper process chamber cover is controlled to a target temperature by measuring the temperature of the center of the outer surface of the upper cover as the value of a controlled variable of an upper cover temperature control loop; a gas flow rate of process gas for depositing the layer is set; and a layer is deposited on the heated wafer front side during control of the upper cover temperature to the target temperature. A process chamber suitable therefor has a sensor for measuring the upper cover outer surface center temperature and a controller for controlling this temperature to a predetermined value.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: April 28, 2015
    Assignee: Siltronic AG
    Inventor: Georg Brenninger
  • Patent number: 9006083
    Abstract: Methods and structures for GaN on silicon-containing substrates are disclosed, comprising a texturing process to generate a rough surface containing (111) surface, which then can act as an underlayer for epitaxial GaN. LED devices are then fabricated on the GaN layer. Variations of the present invention include different orientations of silicon layer instead of (100), such as (110) or others; and other semiconductor materials instead of GaN, such as other semiconductor materials suitable for LED devices.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: April 14, 2015
    Inventor: Ananda H. Kumar
  • Patent number: 8987141
    Abstract: A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer sequentially on the Ge layer after a first annealing, forming a sample; polishing the sample's GaAs cap layer, and growing an nMOSFET structure after a second annealing on the sample; performing selective ICP etching on a surface of the nMOSFET structure to form a groove, and growing a SiO2 layer in the groove and the surface of the nMOSFET structure using PECVD; performing the ICP etching again to etch the SiO2 layer till the Ge layer, forming a trench; cleaning the sample and growing a Ge nucleation layer and a Ge top layer in the trench by UHVCVD; polishing the Ge top layer and removing a part of the SiO2 layer on the nMOSFET structure; performing a CMOS process.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: March 24, 2015
    Assignee: Institute of Semiconductors, Chinese Academy of Sciences
    Inventors: Xuliang Zhou, Hongyan Yu, Shiyan Li, Jiaoqing Pan, Wei Wang
  • Patent number: 8987069
    Abstract: A substrate with two SiGe regions having different Germanium concentrations and a method for making the same. The method includes: providing a substrate with at least two active regions; epitaxially depositing a first SiGe layer over each active regions; epitaxially depositing a Silicon layer over each SiGe layer; epitaxially depositing a second SiGe layer over each Silicon layer; forming a hard mask over the second SiGe layer of one of the active regions; removing the epitaxially deposited second SiGe layer of the unmasked active region, removing the hard mask, and thermally mixing the remaining Silicon and SiGe layers of the active regions to form a new SiGe layer with uniform Germanium concentration for each of the active regions, where the new SiGe layer with uniform Germanium concentration of one of the at least two active regions has a different concentration of Germanium than the new SiGe layer with uniform Germanium concentration of the other SiGe layer.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek
  • Publication number: 20150072509
    Abstract: Embodiments of the present invention generally relate to methods for forming a SiGe layer. In one embodiment, a seed SiGe layer is first formed using plasma enhanced chemical vapor deposition (PECVD), and a bulk SiGe layer is formed directly on the PECVD seed layer also using PECVD. The processing temperature for both seed and bulk SiGe layers is less than 450 degrees Celsius.
    Type: Application
    Filed: August 14, 2014
    Publication date: March 12, 2015
    Inventors: Hyo-In CHI, Farzad Dean TAJIK, Michel Anthony ROSA
  • Publication number: 20150069465
    Abstract: A layer of a silicon germanium alloy containing 30 atomic percent or greater germanium and containing substitutional carbon is grown on a surface of a semiconductor layer. The presence of the substitutional carbon in the layer of silicon germanium alloy compensates the strain of the silicon germanium alloy, and suppresses defect formation. Placeholder semiconductor fins are then formed to a desired dimension within the layer of silicon germanium alloy and the semiconductor layer. The placeholder semiconductor fins will relax for the most part, while maintaining strain in a lengthwise direction. An anneal is then performed which may either remove the substitutional carbon from each placeholder semiconductor fin or move the substitutional carbon into interstitial sites within the lattice of the silicon germanium alloy. Free-standing permanent semiconductor fins containing 30 atomic percent or greater germanium, and strain in the lengthwise direction are provided.
    Type: Application
    Filed: September 10, 2013
    Publication date: March 12, 2015
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8969185
    Abstract: A manufacturing apparatus and a manufacturing method for a quantum dot material. The manufacturing apparatus adds an optical device capable of generating an interference pattern in an existing epitaxial apparatus, so that a substrate applies an interference pattern on an epitaxial layer while performing epitaxial growth. By means of the interference pattern, a regularly distributed temperature field is formed on the epitaxial layer, so that on the epitaxial layer, an atom aggregation phenomenon is formed at dot positions with higher temperature, but no atoms are aggregated on areas having relatively lower temperature. Therefore, according to the temperature distribution on the surface of the epitaxial layer, positions where quantum dots generate can be controlled manually without introducing defects, thereby achieving a defect-free and long-range ordered quantum dot manufacturing.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: March 3, 2015
    Assignee: Soochow University
    Inventor: Changsi Peng
  • Patent number: 8945305
    Abstract: Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Patent number: 8945302
    Abstract: Method for crystal growth from a surfactant of a metal-nonmetal (MN) compound, including the procedures of providing a seed crystal, introducing atoms of a first metal to the seed crystal thus forming a thin liquid metal wetting layer on a surface of the seed crystal, setting a temperature of the seed crystal below a minimal temperature required for dissolving MN molecules in the wetting layer and above a melting point of the first metal, each one of the MN molecules being formed from an atom of a second metal and an atom of a first nonmetal, introducing the MN molecules which form an MN surfactant monolayer, thereby facilitating a formation of the wetting layer between the MN surfactant monolayer and the surface of the seed crystal, and regulating a thickness of the wetting layer, thereby growing an epitaxial layer of the MN compound on the seed crystal.
    Type: Grant
    Filed: March 4, 2012
    Date of Patent: February 3, 2015
    Assignee: Mosaic Crystals Ltd.
    Inventor: Moshe Einav
  • Patent number: 8937001
    Abstract: A technique for forming nanostructures including a definition of a charge pattern on a substrate and introduction of charged molecular scale sized building blocks (MSSBBs) to a region proximate the charge pattern so that the MSSBBs adhere to the charge pattern to form the feature.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: January 20, 2015
    Assignee: Massachusetts Institute of Technology
    Inventors: Joseph M. Jacobson, David Kong, Vikas Anant, Ashley Salomon, Saul Griffith, Will DelHagen, Vikrant Agnihotri
  • Patent number: 8932954
    Abstract: According to one embodiment, an impurity analysis method comprises performing vapor-phase decomposition on a silicon-containing film formed on a substrate, heating the substrate at a first temperature after vapor phase decomposition, heating the substrate at a second temperature higher than the first temperature after heating at the first temperature, to remove a silicon compound deposited on the surface of the silicon-containing film, dropping a recovery solution onto the substrate surface after heating at the second temperature and moving the substrate surface, to recover metal into the recovery solution, and drying the recovery solution, to perform X-ray fluorescence spectrometry on a dried mark.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: January 13, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuji Yamada, Makiko Katano, Chikashi Takeuchi, Tomoyo Naito
  • Patent number: 8927398
    Abstract: A patterned substrate is provided having at least two mesa surface portions, and a recessed surface located beneath and positioned between the at least two mesa surface portions. A Group III nitride material is grown atop the mesa surface portions of the patterned substrate and atop the recessed surface. Growth of the Group III nitride material is continued merging the Group III nitride material that is grown atop the mesa surface portions. When the Group III nitride material located atop the mesa surface portions merge, the Group III nitride material growth on the recessed surface ceases. The merged Group III nitride material forms a first Group III nitride material structure, and the Group III nitride material formed in the recessed surface forms a second material structure. The first and second material structures are disjoined from each other and are separated by an air gap.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Can Bayram, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 8921212
    Abstract: A semiconductor device manufacturing apparatus includes a chamber in which a wafer is loaded; a first gas supply unit for supplying a process gas into the chamber; a gas exhaust unit for exhausting a gas from the chamber; a wafer support member on which the wafer is placed; a ring on which the wafer support member is placed; a rotation drive control unit connected to the ring to rotate the wafer; a heater disposed in the ring and comprising a heater element for heating the wafer to a predetermined temperature and including an SiC layer on at least a surface, and a heater electrode portion molded integrally with a heater element and including an SiC layer on at least a surface; and a second gas supply unit for supplying an SiC source gas into the ring.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: December 30, 2014
    Assignee: NuFlare Technology, Inc.
    Inventors: Kunihiko Suzuki, Shinichi Mitani
  • Patent number: 8900958
    Abstract: The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) descried enable forming an epitaxially grown silicon-containing material without using GeH4 in an etch gas mixture of an etch process for a cyclic deposition/etch (CDE) process. The etch process is performed at a temperature different form the deposition process to make the etch gas more efficient. As a result, the etch time is reduced and the throughput is increased.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Meng-Yueh Liu
  • Patent number: 8901605
    Abstract: There is provided a semiconductor wafer including a base wafer whose surface is entirely or partially a silicon crystal plane, an inhibitor positioned on the base wafer to inhibit crystal growth and having an opening that reaches the silicon crystal plane, a first crystal layer made of SixGe1-x (0?x<1) and positioned on the silicon crystal plane that is exposed in the opening, a second crystal layer positioned on the first crystal layer and made of a III-V Group compound semiconductor that has a band gap width larger than a band gap width of the first crystal layer, and a pair of metal layers positioned on the inhibitor and the second crystal layer. The pair of the metal layers are each in contact with the first crystal layer and the second crystal layer.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: December 2, 2014
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Tomoyuki Takada, Sadanori Yamanaka, Masao Shimada, Masahiko Hata, Taro Itatani, Hiroyuki Ishii, Eiji Kume
  • Patent number: 8900961
    Abstract: A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ashima B. Chakravarti, Anthony I. Chou, Toshiharu Furukawa, Steven J. Holmes, Wesley C. Natzle
  • Patent number: 8871617
    Abstract: In one aspect, methods of forming mixed metal thin films comprising at least two different metals are provided. In some embodiments, a mixed metal oxide thin film is formed by atomic layer deposition and subsequently reduced to a mixed metal thin film. Reduction may take place, for example, in a hydrogen atmosphere. The presence of two or more metals in the mixed metal oxide allows for reduction at a lower reduction temperature than the reduction temperature of the individual oxides of the metals in the mixed metal oxide film.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: October 28, 2014
    Assignee: ASM IP Holding B.V.
    Inventors: Viljami J. Pore, Eva Tois
  • Patent number: 8874254
    Abstract: An object of the present invention is to perform temperature setting of a heating plate so that a wafer is uniformly heated in an actual heat processing time. The temperature of a wafer is measured during a heat processing period from immediately after a temperature measuring wafer is mounted on the heating plate to the time when the actual heat processing time elapses. Whether the uniformity in temperature within the wafer is allowable or not is determined from the temperature of the wafer in the heat processing period, and if the determination result is negative, a correction value for a temperature setting parameter of the heating plate is calculated using a correction value calculation model from the measurement result, and the temperature setting parameter is changed.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: October 28, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Shuji Iwanaga, Nobuyuki Sata
  • Patent number: 8859405
    Abstract: A method for fabricating high efficiency CIGS solar cells including the deposition of Ga concentrations (Ga/(Ga+In)=0.25?0.66) from sputtering targets containing Ga concentrations between about 25 atomic % and about 66 atomic %. Further, the method includes a high temperature selenization process integrated with a high temperature anneal process that results in high efficiency.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: October 14, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Haifan Liang, Sang Lee, Wei Liu, Sandeep Nijhawan, Jeroen Van Duren
  • Patent number: 8859406
    Abstract: A method for fabricating high efficiency CIGS solar cells including the deposition of Ga concentrations (Ga/(Ga+In)=0.25-0.66) from sputtering targets containing Ga concentrations between about 25 atomic % and about 66 atomic %. Further, the method includes a high temperature selenization process integrated with a high temperature anneal process that results in high efficiency.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: October 14, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Haifan Liang, Sang Lee, Wei Liu, Sandeep Nijhawan, Jeroen Van Duren
  • Publication number: 20140295653
    Abstract: A manufacturing apparatus and a manufacturing method for a quantum dot material. The manufacturing apparatus adds an optical device capable of generating an interference pattern in an existing epitaxial apparatus, so that a substrate applies an interference pattern on an epitaxial layer while performing epitaxial growth. By means of the interference pattern, a regularly distributed temperature field is formed on the epitaxial layer, so that on the epitaxial layer, an atom aggregation phenomenon is formed at dot positions with higher temperature, but no atoms are aggregated on areas having relatively lower temperature. Therefore, according to the temperature distribution on the surface of the epitaxial layer, positions where quantum dots generate can be controlled manually without introducing defects, thereby achieving a defect-free and long-range ordered quantum dot manufacturing.
    Type: Application
    Filed: July 2, 2012
    Publication date: October 2, 2014
    Applicant: Soochow University
    Inventor: Changsi Peng
  • Publication number: 20140287572
    Abstract: A manufacturing method of MIS (Metal Insulator Semiconductor)-type semiconductor device includes the steps of; forming a zirconium oxynitride (ZrON) layer; forming an electrode layer containing titanium nitride (TiN) on the zirconium oxynitride (ZrON) layer; and heating the electrode layer.
    Type: Application
    Filed: February 3, 2014
    Publication date: September 25, 2014
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Kiyotaka MIZUKAMI, Takahiro Sonoyama, Toru Oka, Junya Nishii
  • Publication number: 20140284627
    Abstract: Disclosed is a method of manufacturing a thin film, the method including: growing an epitaxial layer on a surface of a wafer at a growth temperature, wherein the growing of the epitaxial layer comprises controlling a defect present on a surface of the wafer. Also, disclosed is a wafer including: a substrate; and an epitaxial layer located on the substrate, wherein a basal dislocation density of the epitaxial layer is equal to or less than 1/cm2.
    Type: Application
    Filed: October 26, 2012
    Publication date: September 25, 2014
    Inventor: Moo Seong Kim
  • Patent number: 8842710
    Abstract: There are provided a process for producing a semiconductor device and a semiconductor device which allow conductivity distribution to be formed without making refractive index distributed even in a material system of a semiconductor difficult to be subjected to ion implantation. The process for producing a semiconductor device includes the steps of forming a semiconductor layer containing a dopant; forming a concave and convex structure on the semiconductor layer by partially removing the semiconductor layer; and forming a conductivity distribution reflecting the concave and convex structure in the semiconductor layer by performing heat treatment on the semiconductor layer in which the concave and convex structure has been formed at a temperature at which a material forming the semiconductor layer causes mass transport and filling up a hole of a concave portion of the concave and convex structure with the material forming the semiconductor layer.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: September 23, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuhiro Nagatomo, Takeshi Kawashima, Katsuyuki Hoshino, Shoichi Kawashima
  • Patent number: 8841221
    Abstract: The invention relates to a device for depositing semiconductor layers, comprising a process chamber (1) arranged substantially rotationally symmetrically about a center (11), a susceptor (2), a process chamber ceiling (3), a gas inlet element (4) having gas inlet chambers (8, 9, 10) that are arranged vertically on top of each other, and a heater (27) arranged below the susceptor (2), wherein the topmost (8) of the gas inlet chambers is directly adjacent to the process chamber ceiling (3) and is connected to a feed line (14) for feeding a hydride together with a carrier gas into the process chamber (1), wherein the lowest (10) of the gas inlet chambers is directly adjacent to the susceptor (2) and is connected to a feed line (16) for feeding a hydride together with a carrier gas into the process chamber (1), wherein at least one center gas inlet chamber (9) arranged between the lowest (10) and the topmost (8) gas inlet chamber is connected to a feed line (15) for feeding an organometallic compound into the pro
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: September 23, 2014
    Assignee: Aixtron SE
    Inventors: Daniel Brien, Oliver Schön
  • Patent number: 8840797
    Abstract: A unique and cost-effective method for producing a multilayer ceramic structure by using a first green film that contains a ceramic material, and the multilayer ceramic structure produced thereby. The method including the steps of: (a) producing at least one porous region in the first green film, the at least one porous region extending from the surface of the first green film; (b) applying a first layer, in sections, to the surface of the first green film, wherein one section of the first layer is located above the at least one porous region produced in step (a); (c) positioning at least one additional green film on the surface of the first green film, to which the first layer has been applied; (d) laminating the first green film and the at least one additional green film to form a green film composite; and (e) sintering the green film composite.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: September 23, 2014
    Assignees: Micro Systems Engineering GmbH, Technische Universitaet Wien
    Inventors: Thomas Haas, Dieter Schwanke, Achim Bittner, Ulrich Schmid
  • Patent number: 8835286
    Abstract: The invention provides a manufacturing method of a graphene-on-insulator substrate which is mass productive, of high quality, and yet is directly usable for manufacture of semiconductor devices at a low manufacturing cost. According to the manufacturing method of a graphene substrate of the invention, a metal layer and a carbide layer are heated with the metal layer in contact with the carbide layer so that carbon in the carbide layer is dissolved into the metal layer, and then the metal layer and the carbide layer are cooled so that the carbon in the metal layer is segregated as graphene on the surface of the carbide layer.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: September 16, 2014
    Assignee: NEC Corporation
    Inventors: Hidefumi Hiura, Kazuhito Tsukagoshi
  • Patent number: 8802485
    Abstract: In the frame of manufacturing a photovoltaic cell a layer (3) of silicon compound is deposited on a structure (1). The yet uncovered surface (3a) is treated in a predetermined oxygen (O2) containing atmosphere which additionally contains a dopant (D). Thereby, the silicon compound layer is oxidized and doped in a thin surface area (5).
    Type: Grant
    Filed: September 7, 2009
    Date of Patent: August 12, 2014
    Assignee: Tel Solar AG
    Inventors: Johannes Meier, Markus Bronner, Markus Kupich, Tobias Roschek, Hanno Goldbach
  • Publication number: 20140203297
    Abstract: This invention relates to a method for depositing silicon carbide material onto a substrate such that the resulting substrate has a carrier lifetime of 0.5-1000 microseconds, the method comprising a. introducing a gas mixture comprising a chlorosilane gas, a carbon-containing gas, and hydrogen gas into a reaction chamber containing a substrate; and b. heating the substrate to a temperature of greater than 1000° C. but less than 2000° C.; with the proviso that the pressure within the reaction chamber is maintained in the range of 0.1 to 760 torr. This invention also relates to a method for depositing silicon carbide material onto a substrate such that the resulting substrate has a carrier lifetime of 0.5-1000 microseconds, the method comprising a. introducing a gas mixture comprising a non-chlorinated silicon-containing gas, hydrogen chloride, a carbon-containing gas, and hydrogen gas into a reaction chamber containing a substrate; and b. heating the substrate to a temperature of greater than 1000° C.
    Type: Application
    Filed: January 18, 2013
    Publication date: July 24, 2014
    Applicant: Dow Corning Corporation
    Inventors: Gilyong Chung, Mark Loboda
  • Patent number: 8784703
    Abstract: A method of making a colloidal solution of high confinement semiconductor nanocrystals includes: forming a first solution by combining a solvent, growth ligands, and at most one semiconductor precursor; heating the first solution to the nucleation temperature; and adding to the first solution, a second solution having a solvent, growth ligands, and at least one additional and different precursor than that in the first solution to form a crude solution of nanocrystals having a compact homogenous semiconductor region. The method further includes: waiting 0.5 to 20 seconds and adding to the crude solution a third solution having a solvent, growth ligands, and at least one additional and different precursor than those in the first and second solutions; and lowering the growth temperature to enable the formation of a gradient alloy region around the compact homogenous semiconductor region, resulting in the formation of a colloidal solution of high confinement semiconductor nanocrystals.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: July 22, 2014
    Assignee: Eastman Kodak Company
    Inventors: Keith Brian Kahen, Matthew Holland, Sudeep Pallikkara Kuttiatoor
  • Patent number: 8765507
    Abstract: A method for manufacturing a Group III nitride semiconductor of the present invention includes a sputtering step of forming a single-crystalline Group III nitride semiconductor on a substrate by a reactive sputtering method in a chamber in which a substrate and a Ga element-containing target are disposed, wherein said sputtering step includes respective substeps of: a first sputtering step of performing a film formation of the Group III nitride semiconductor while setting the temperature of the substrate to a temperature T1; and a second sputtering step of continuing the film formation of the Group III nitride semiconductor while lowering the temperature of the substrate to a temperature T2 which is lower than the temperature T1.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: July 1, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Yasunori Yokoyama, Hisayuki Miki
  • Patent number: 8759198
    Abstract: A method for fabricating an integrated circuit (IC) includes initial oxidizing of a semiconductor surface of a substrate. The substrate is heated after the initial oxidizing using a plurality of furnace processing steps which each include a peak processing temperature between 800° C. and 1300° C. The furnace processing steps include at least one accelerated processing step having an accelerated ramp portion in a temperature range between 800° C. and 1250° C. providing an accelerated ramp-up rate and/or an |accelerated ramp-down rate| of at least (?) 5.5° C./min.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: June 24, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Bradley David Sucher, Rick L. Wise
  • Publication number: 20140170841
    Abstract: The present invention provides a silicon carbide semiconductor device having an ohmic electrode improved in adhesion of a wire thereto by preventing deposition of carbon so as not to form a Schottky contact, as well as a method for manufacturing such a silicon carbide semiconductor device. In the SiC semiconductor device, upon forming the ohmic electrode, a first metal layer made of one first metallic element is formed on one main surface of a SiC layer. Further, a Si layer made of Si is formed on an opposite surface of the first metal layer to its surface facing the SiC layer. The stacked structure thus formed is subjected to thermal treatment. In this way, there can be obtained a silicon carbide semiconductor device having an ohmic electrode adhered well to a wire by preventing deposition of carbon atoms on the surface layer of the electrode and formation of a Schottky contact resulting from Si and SiC.
    Type: Application
    Filed: January 29, 2014
    Publication date: June 19, 2014
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Hideto Tamaso
  • Publication number: 20140147978
    Abstract: A semiconductor device comprises a substrate comprising a major surface; a p-type Field Effect Transistor (pFET) comprising: a P-gate stack over the major surface, a P-strained region in the substrate adjacent to one side of the P-gate stack, wherein a lattice constant of the P-strained region is different from a lattice constant of the substrate, wherein the P-strained region has a first top surface higher than the major surface; and a P-silicide region on the P-strained region; and an n-type Field Effect Transistor (nFET) comprising: an N-gate stack over the major surface, an N-strained region in the substrate adjacent to one side of the N-gate stack, wherein a lattice constant of the N-strained region is different from a lattice constant of the substrate, wherein the N-strained region has a second top surface lower than the major surface and a N-silicide region on the N-strained region.
    Type: Application
    Filed: January 28, 2014
    Publication date: May 29, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Hsien Chen, Ting-Chu Ko, Chih-Hao Chang, Chih-Sheng Chang, Shou-Zen Chang, Clement Hsingjen Wann
  • Patent number: 8716049
    Abstract: Techniques for crack-free growth of GaN, and related, films on larger-size substrates via spatially confined epitaxy are described.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: May 6, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Jie Su, Olga Kryliouk
  • Patent number: 8685826
    Abstract: A method for forming a nanocrystalline silicon structure for the manufacture of integrated circuit devices, e.g., memory, dynamic random access memory, flash memory, read only memory, microprocessors, digital signal processors, application specific integrated circuits. The method includes providing a semiconductor substrate including a surface region. The method forms an insulating layer (e.g., silicon dioxide, silicon nitride, silicon oxynitride) overlying the surface region. In a specific embodiment, the method includes forming an amorphous silicon material of a determined thickness of less than twenty nanometers overlying the insulating layer using a chloro-silane species. The method includes subjecting the amorphous silicon material to a thermal treatment process to cause formation of a plurality of nanocrystalline silicon structures derived from the thickness of amorphous silicon material less than twenty nanometers.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: April 1, 2014
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Mieno Fumitake
  • Patent number: 8673747
    Abstract: A method of fabricating a semiconductor device includes: forming an epitaxial layer on a semiconductor substrate; forming a capping layer having a first thickness on the epitaxial layer; and oxidizing the capping layer in an oxygen atmosphere to form a first gate dielectric layer having a second thickness.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: March 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Ho Do, Ha-Jin Lim, Weon-Hong Kim, Hoi-Sung Chung, Moon-Kyun Song, Dae-Kwon Joo
  • Patent number: 8652951
    Abstract: Methods and apparatus for forming a germanium containing film on a patterned substrate are described. The patterned substrate is a silicon, or silicon containing material, and may have a mask material formed on a surface thereof. The germanium containing material is formed selectively on exposed silicon in the recesses of the substrate, and an overburden of at least 50% is formed on the substrate. The germanium containing layer is thermally treated using pulsed laser radiation, which melts a portion of the overburden, but does not melt the germanium containing material in the recesses. The germanium containing material in the recesses is typically annealed, at least in part, by the thermal treatment. The overburden is then removed.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: February 18, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Yi-Chiau Huang, Jiping Li, Miao Jin, Bingxi Sun Wood, Errol Antonio C. Sanchez, Yihwan Kim
  • Patent number: 8652946
    Abstract: A system and method for forming graphene layers on a substrate. The system and methods include direct growth of graphene on diamond and low temperature growth of graphene using a solid carbon source.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: February 18, 2014
    Assignee: Uchicago Argonne, LLC.
    Inventors: Anirudha V. Sumant, Alexander Balandin
  • Publication number: 20140035103
    Abstract: Provided is a high-quality Group III nitride crystal of excellent processability. A Group III nitride crystal is produced by forming a film is composed of an oxide, hydroxide and/or oxyhydroxide containing a Group III element by heat-treating a Group III nitride single crystal at 1000° C. or above, and removing the film.
    Type: Application
    Filed: October 15, 2013
    Publication date: February 6, 2014
    Applicant: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Hajime MATSUMOTO, Kunitada SUZAKI, Kenji FUJITO, Satoru NAGAO
  • Patent number: 8642449
    Abstract: A silicon wafer which has DZ layers formed on both sides thereof by heat treatment in an atmosphere of reducing gas (such as hydrogen) or rare gas (such as argon) with a specific temperature profile for heating, holding, and cooling, and which also has a gettering site of BMD in the bulk inside the DZ layer. A silicon wafer which has a silicon epitaxial layer formed on one side thereof. The DZ layer and the silicon epitaxial layer contain dissolved oxygen introduced into their surface parts, with the concentration and distribution of dissolved oxygen properly controlled. Introduction of oxygen into the surface part is accomplished by heat treatment and ensuing rapid cooling in an atmosphere of oxygen-containing gas.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: February 4, 2014
    Assignee: Globalwafers Japan Co., Ltd.
    Inventors: Takashi Watanabe, Ryuji Takeda