Heat Treatment Patents (Class 438/509)
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Patent number: 8673747Abstract: A method of fabricating a semiconductor device includes: forming an epitaxial layer on a semiconductor substrate; forming a capping layer having a first thickness on the epitaxial layer; and oxidizing the capping layer in an oxygen atmosphere to form a first gate dielectric layer having a second thickness.Type: GrantFiled: April 25, 2011Date of Patent: March 18, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Ho Do, Ha-Jin Lim, Weon-Hong Kim, Hoi-Sung Chung, Moon-Kyun Song, Dae-Kwon Joo
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Patent number: 8652951Abstract: Methods and apparatus for forming a germanium containing film on a patterned substrate are described. The patterned substrate is a silicon, or silicon containing material, and may have a mask material formed on a surface thereof. The germanium containing material is formed selectively on exposed silicon in the recesses of the substrate, and an overburden of at least 50% is formed on the substrate. The germanium containing layer is thermally treated using pulsed laser radiation, which melts a portion of the overburden, but does not melt the germanium containing material in the recesses. The germanium containing material in the recesses is typically annealed, at least in part, by the thermal treatment. The overburden is then removed.Type: GrantFiled: February 13, 2013Date of Patent: February 18, 2014Assignee: Applied Materials, Inc.Inventors: Yi-Chiau Huang, Jiping Li, Miao Jin, Bingxi Sun Wood, Errol Antonio C. Sanchez, Yihwan Kim
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Patent number: 8652946Abstract: A system and method for forming graphene layers on a substrate. The system and methods include direct growth of graphene on diamond and low temperature growth of graphene using a solid carbon source.Type: GrantFiled: April 16, 2012Date of Patent: February 18, 2014Assignee: Uchicago Argonne, LLC.Inventors: Anirudha V. Sumant, Alexander Balandin
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Publication number: 20140035103Abstract: Provided is a high-quality Group III nitride crystal of excellent processability. A Group III nitride crystal is produced by forming a film is composed of an oxide, hydroxide and/or oxyhydroxide containing a Group III element by heat-treating a Group III nitride single crystal at 1000° C. or above, and removing the film.Type: ApplicationFiled: October 15, 2013Publication date: February 6, 2014Applicant: MITSUBISHI CHEMICAL CORPORATIONInventors: Hajime MATSUMOTO, Kunitada SUZAKI, Kenji FUJITO, Satoru NAGAO
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Patent number: 8642449Abstract: A silicon wafer which has DZ layers formed on both sides thereof by heat treatment in an atmosphere of reducing gas (such as hydrogen) or rare gas (such as argon) with a specific temperature profile for heating, holding, and cooling, and which also has a gettering site of BMD in the bulk inside the DZ layer. A silicon wafer which has a silicon epitaxial layer formed on one side thereof. The DZ layer and the silicon epitaxial layer contain dissolved oxygen introduced into their surface parts, with the concentration and distribution of dissolved oxygen properly controlled. Introduction of oxygen into the surface part is accomplished by heat treatment and ensuing rapid cooling in an atmosphere of oxygen-containing gas.Type: GrantFiled: November 5, 2010Date of Patent: February 4, 2014Assignee: Globalwafers Japan Co., Ltd.Inventors: Takashi Watanabe, Ryuji Takeda
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Publication number: 20140008698Abstract: There is provided a semiconductor wafer including a base wafer whose surface is entirely or partially a silicon crystal plane, an inhibitor positioned on the base wafer to inhibit crystal growth and having an opening that reaches the silicon crystal plane, a first crystal layer made of SixGe1-x (0?x<1) and positioned on the silicon crystal plane that is exposed in the opening, a second crystal layer positioned on the first crystal layer and made of a III-V Group compound semiconductor that has a band gap width larger than a band gap width of the first crystal layer, and a pair of metal layers positioned on the inhibitor and the second crystal layer. The pair of the metal layers are each in contact with the first crystal layer and the second crystal layer.Type: ApplicationFiled: September 5, 2013Publication date: January 9, 2014Applicants: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Tomoyuki TAKADA, Sadanori YAMANAKA, Masao SHIMADA, Masahiko HATA, Taro ITATANI, Hiroyuki ISHII, Eiji KUME
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Patent number: 8609456Abstract: The disclosure provides a method for fabricating a semiconductor layer having a textured surface, including: (a) providing a textured substrate; (b) forming at least one semiconductor layer on the textured substrate; (c) forming a metal layer on the semiconductor layer; and (d) conducting a thermal process to the textured substrate, the semiconductor layer and the metal layer, wherein the semiconductor layer is separated from the textured substrate by the thermal process to obtain the semiconductor layer having the metal layer and a textured surface.Type: GrantFiled: September 9, 2012Date of Patent: December 17, 2013Assignee: Industrial Technology Research InstituteInventors: Teng-Yu Wang, Chien-Hsun Chen, Chen-Hsun Du, Chung-Yuan Kung
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Patent number: 8603886Abstract: A method for fabricating an epitaxial structure includes: (a) forming over a temporary substrate a patterned sacrificial layer that partially exposes the temporary substrate; (b) growing laterally and epitaxially a temporary epitaxial film over the patterned sacrificial layer and the temporary substrate; (c) forming over the temporary epitaxial film an etching-stop layer; (d) forming an epitaxial layer unit over the etching-stop layer; (e) removing the patterned sacrificial layer using a first etchant; and (f) removing the temporary epitaxial film using a second etchant.Type: GrantFiled: December 20, 2011Date of Patent: December 10, 2013Assignee: National Chung-Hsing UniversityInventors: Dong-Sing Wuu, Ray-Hua Horng, Tsung-Yen Tsai
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Patent number: 8598023Abstract: There is disclosed a substrate processing apparatus including a processing chamber housing a substrate, pipes for supplying gas into the processing chamber, and heaters provided in the middle of the pipes, and heating the gas. In the substrate processing apparatus, the heaters heat the gas to a temperature lower than a temperature at which exhaust gas is generated from the pipes to dry the substrate in the heated gas.Type: GrantFiled: July 31, 2012Date of Patent: December 3, 2013Assignee: Fujitsu Semiconductor LimitedInventor: Tomokazu Kawamoto
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Publication number: 20130309850Abstract: A method for fabricating high efficiency CIGS solar cells including the deposition of Ga concentrations (Ga/(Ga+In)=0.25?0.66) from sputtering targets containing Ga concentrations between about 25 atomic % and about 66 atomic %. Further, the method includes a high temperature selenization process integrated with a high temperature anneal process that results in high efficiency.Type: ApplicationFiled: August 27, 2012Publication date: November 21, 2013Inventors: Haifan Liang, Sang Lee, Wei Liu, Sandeep Nijhawan, Jeroen Van Duren
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Patent number: 8586457Abstract: A method for fabricating high efficiency CIGS solar cells including the deposition of Ga concentrations (Ga/(Ga+In)=0.25?0.66) from sputtering targets containing Ga concentrations between about 25 atomic % and about 66 atomic %. Further, the method includes a high temperature selenization process integrated with a high temperature anneal process that results in high efficiency.Type: GrantFiled: August 27, 2012Date of Patent: November 19, 2013Assignee: Intermolecular, Inc.Inventors: Haifan Liang, Sang Lee, Wei Liu, Sandeep Nijhawan, Jeroen Van Duren
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Patent number: 8558304Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing are also provided.Type: GrantFiled: April 29, 2011Date of Patent: October 15, 2013Assignee: SanDisk CorporationInventors: Jian Chen, Xiangfeng Duan, Chao Liu, Madhuri Nallabolu, J. Wallace Parce, Srikanth Ranganathan
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Patent number: 8530360Abstract: A device including a first body (101) with terminals (102) on a surface (101a), each terminal having a metallic connector (110), which is shaped as a column substantially perpendicular to the surface. Preferably, the connectors have an aspect ratio of height to diameter of 2 to 1 or greater, and a fine pitch center-to-center. The connector end (110a) remote from the terminal is covered by a film (130) of a sintered paste including a metallic matrix embedded in a first polymeric compound. Further a second body (103) having metallic pads (140) facing the respective terminals (102). Each connector film (130) is in contact with the respective pad (140), whereby the first body (101) is spaced from the second body (103) with the connector columns (110) as standoff. A second polymeric compound (150) is filling the space of the standoff.Type: GrantFiled: January 25, 2011Date of Patent: September 10, 2013Assignee: Texas Instruments IncorporatedInventor: Abram M. Castro
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Patent number: 8525303Abstract: A photovoltaic device includes a semiconductor nanocrystal and a charge transporting layer that includes an inorganic material. The charge transporting layer can be a hole or electron transporting layer. The inorganic material can be an inorganic semiconductor.Type: GrantFiled: June 25, 2007Date of Patent: September 3, 2013Assignee: Massachusetts Institute of TechnologyInventors: Alexi Arango, Vladimir Bulovic, Vanessa Wood, Moungi G. Bawendi
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Patent number: 8518808Abstract: A GaN sample in a sealed enclosure is heated very fast to a high temperature above the point where GaN is thermodynamically stable and is then cooled down very fast to a temperature where it is thermodynamically stable. The time of the GaN exposure to a high temperature range above its thermodynamic stability is sufficiently short, in a range of few seconds, to prevent the GaN from decomposing. This heating and cooling cycle is repeated multiple times without removing the sample from the enclosure. As a result, by accumulating the exposure time in each cycle, the GaN sample can be exposed to a high temperature above its point of thermodynamic stability for a long time but the GaN sample integrity is maintained (i.e., the GaN doesn't decompose) due to the extremely short heating duration of each single cycle.Type: GrantFiled: September 16, 2011Date of Patent: August 27, 2013Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Boris N. Feigelson, Travis Anderson, Francis J. Kub
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Publication number: 20130210221Abstract: Methods and apparatus for forming a germanium containing film on a patterned substrate are described. The patterned substrate is a silicon, or silicon containing material, and may have a mask material formed on a surface thereof. The germanium containing material is formed selectively on exposed silicon in the recesses of the substrate, and an overburden of at least 50% is formed on the substrate. The germanium containing layer is thermally treated using pulsed laser radiation, which melts a portion of the overburden, but does not melt the germanium containing material in the recesses. The germanium containing material in the recesses is typically annealed, at least in part, by the thermal treatment. The overburden is then removed.Type: ApplicationFiled: February 13, 2013Publication date: August 15, 2013Inventors: YI-CHIAU HUANG, Jiping Li, Miao Jin, Bingxi Sun Wood, Errol Antonio C. Sanchez, Yihwan Kim
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Patent number: 8501599Abstract: A substrate processing apparatus has: a process chamber in which a substrate is processed; a heating device that optically heats the substrate accommodated in the process chamber from an outer periphery side of the substrate; a cooling device that cools the outer periphery side of the substrate by flowing a fluid in a vicinity of an outer periphery of the substrate optically heated by the heating device; a temperature detection portion that detects a temperature inside the process chamber; and a heating control portion that controls the heating device and the cooling device in such a manner so as to provide a temperature difference between a center portion of the substrate and an end portion of the substrate while maintaining a temperature at the center portion at a pre-determined temperature according to the temperature detected by the temperature detection portion.Type: GrantFiled: February 21, 2007Date of Patent: August 6, 2013Assignee: Hitachi Kokusai Electric Inc.Inventors: Masaaki Ueno, Masakazu Shimada, Takeo Hanashima, Haruo Morikawa, Akira Hayashida
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Patent number: 8492251Abstract: A thin layer structure includes a substrate, a blocking pattern that exposes part of an upper surface of the substrate, and a single crystalline semiconductor layer on the part of the upper surface of the substrate exposed by the pattern and in which all outer surfaces of the single crystalline semiconductor layer have a <100> crystallographic orientation. The thin layer structure is formed by an SEG process in which the temperature is controlled to prevent migration of atoms in directions towards the central portion of the upper surface of the substrate. Thus, sidewall surfaces of the layer will not be constituted by facets.Type: GrantFiled: August 28, 2012Date of Patent: July 23, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Hoon Kang, Bong-Jin Kuh, Tae-Gon Kim, Han-Mei Choi, Ki-Chul Kim, Eun-Young Jo
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Patent number: 8486813Abstract: A silicon wafer and fabrication method thereof are provided. The silicon wafer includes a first denuded zone formed with a predetermined depth from a top surface of the silicon wafer, the first denuded zone being formed with a depth ranging from approximately 20 ?m to approximately 80 ?m from the top surface, and a bulk area formed between the first denuded zone and a backside of the silicon wafer, the bulk area having a concentration of oxygen uniformly distributed within a variation of 10% over the bulk area.Type: GrantFiled: June 1, 2011Date of Patent: July 16, 2013Assignee: Magnachip Semiconductor, Ltd.Inventor: Jung-Goo Park
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Patent number: 8481393Abstract: A semiconductor substrate is irradiated with accelerated hydrogen ions, thereby forming a damaged region including a large amount of hydrogen. After a single crystal semiconductor substrate and a supporting substrate are bonded to each other, the semiconductor substrate is heated, so that the single crystal semiconductor substrate is separated in the damaged region. A single crystal semiconductor layer which is separated from the single crystal semiconductor substrate is irradiated with a laser beam. The single crystal semiconductor layer is melted by laser beam irradiation, whereby the single crystal semiconductor layer is recrystallized to recover its crystallinity and to planarized a surface of the single crystal semiconductor layer. After the laser beam irradiation, the single crystal semiconductor layer is heated at a temperature at which the single crystal semiconductor layer is not melted, so that the lifetime of the single crystal semiconductor layer is improved.Type: GrantFiled: July 27, 2010Date of Patent: July 9, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masaki Koyama, Fumito Isaka, Akihisa Shimomura, Junpei Momo
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Publication number: 20130168697Abstract: A method of manufacturing a silicon carbide structure includes forming a silicon carbide layer by depositing silicon carbide on a base plate by chemical vapor deposition, removing the base plate, decreasing electrical conductivity by heat-treating the silicon carbide structure, and removing a thickness of 200 ?m from an upper surface and a lower surface of the silicon carbide structure. In the present invention, silicon carbide is deposited by a CVD method, and the electrical conductivity of the silicon carbide is reduced to the electrical conductivity required for a protection ring of a plasma device through a post-treatment and a post-process. The electrical conductivity may be adjusted even without using separate additives.Type: ApplicationFiled: September 11, 2012Publication date: July 4, 2013Applicant: TOKAI CARBON KOREA CO., LTD.Inventors: Joung Il Kim, Jae Seok Lim, Mi-Ra Yoon
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Patent number: 8461031Abstract: A method for making a thin-film structure includes a thin film stabilized on a substrate. The structure of the thin film is defined by a material which includes at least one first chemical species. The method includes a step of inputting particles of the first chemical species into the thin film so as to compensate for the flow of vacancies from the surface of the film.Type: GrantFiled: October 25, 2006Date of Patent: June 11, 2013Assignee: Commissariat a l'Energie AtomiqueInventors: Joël Eymery, Pascal Pochet
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Patent number: 8445364Abstract: A method for treating semiconducting materials includes providing a semiconducting material having a crystalline structure, pre-heating a portion of the semiconducting material to a temperature less than the melting temperature of the semiconducting material, and then cooling the semiconducting material prior to exposing at least the portion of the semiconducting material to a heat source to create a melt pool, and cooling the semiconducting material.Type: GrantFiled: June 2, 2008Date of Patent: May 21, 2013Assignee: Corning IncorporatedInventors: Prantik Mazumder, Kamal Kishore Soni, Christopher Scott Thomas, Natesan Venkataraman, Glen Bennett Cook
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Publication number: 20130115760Abstract: A thin layer structure includes a substrate, a blocking pattern that exposes part of an upper surface of the substrate, and a single crystalline semiconductor layer on the part of the upper surface of the substrate exposed by the pattern and in which all outer surfaces of the single crystalline semiconductor layer have a <100> crystallographic orientation. The thin layer structure is formed by an SEG process in which the temperature is controlled to prevent migration of atoms in directions towards the central portion of the upper surface of the substrate. Thus, sidewall surfaces of the layer will not be constituted by facets.Type: ApplicationFiled: August 28, 2012Publication date: May 9, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: JONG-HOON KANG, BONG-JIN KUH, TAE-GON KIM, HAN-MEI CHOI, KI-CHUL KIM, EUN-YOUNG JO
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Patent number: 8399341Abstract: The invention is to provide a method for heat treating a silicon wafer reducing grown-in defects while suppressing generation of slip during RTP and improving surface roughness of the wafer. The method performing a first heat treatment while introducing a rare gas, the first heat treatment comprising the steps of rapidly heating the wafer to T1 of 1300° C. or higher and the melting point of silicon or lower, keeping the wafer at T1, rapidly cooling the wafer to T2 of 400-800° C. and keeping the wafer at T2; and performing a second heat treatment while introducing an oxygen gas in an amount of 20-100 vol. %, the second heat treatment comprising the steps of keeping the wafer at T2, rapidly heating the wafer from T2 to T3 of 1250° C. or higher and the melting point of silicon or lower, keeping the wafer at T3 and rapidly cooling the wafer.Type: GrantFiled: May 17, 2010Date of Patent: March 19, 2013Assignee: Covalent Materials CorporationInventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Kumiko Murayama, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
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Publication number: 20130062665Abstract: A method for producing a monolithic template comprises a Si wafer with a layer of a III/V semiconductor epitaxially applied to its surface. The III/V semiconductor has a lattice constant differing by less than 10% from that of Si. The method includes epitaxially growing a layer of a III/V semiconductor on the surface of the Si wafer at a wafer temperature from 350 to 650° C., a growth rate from 0.1 to 2 ?m/h, and a layer thickness from 1 to 100 nm. A layer of another III/V semiconductor, identical to or different from the previously applied III/V semiconductor, is epitaxially grown on the III/V semiconductor layer at a wafer temperature from 500 to 800° C., a growth rate from 0.1 to 10 ?m/h, and a layer thickness from 10 to 150 nm.Type: ApplicationFiled: September 11, 2012Publication date: March 14, 2013Applicant: NASP III/V GMBHInventor: Bernardette Kunert
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Publication number: 20130043508Abstract: The present invention is related to a method for manufacturing a low defect interface between a dielectric material and an III-V compound. More specifically, the present invention relates to a method for manufacturing a passivated interface between a dielectric material and an III-V compound. The present invention is also directed to a device comprising a low defect interface between a dielectric material and an III-V compound that has improved performance.Type: ApplicationFiled: October 17, 2012Publication date: February 21, 2013Inventor: Clement Merckling
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Patent number: 8377729Abstract: A method of making II-VI core-shell semiconductor nanowires includes providing a support; depositing a layer including metal alloy nanoparticles on the support; and heating the support and growing II-VI core semiconductor nanowires where the metal alloy nanoparticles act as catalysts and selectively cause localized growth of the core nanowires. The method further includes modifying the growth conditions and shelling the core nanowires to form II-VI core-shell semiconductor nanowires.Type: GrantFiled: January 19, 2010Date of Patent: February 19, 2013Assignee: Eastman Kodak CompanyInventors: Keith B. Kahen, Matthew Holland
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Patent number: 8372687Abstract: A method for forming multiple layers in a single process chamber includes placing a substrate in the process chamber having multiple processing sources and iteratively forming a copper indium gallium selenium (CIGS) including forming multiple relatively thin CIGS layers including forming a copper indium gallium (CIG) layer on the substrate, the CIG layer having a thickness of between less than about 50 angstroms and about 200 angstroms, forming a selenium layer on the CIG layer, the selenium layer having a thickness of between less than about 50 angstroms and about 200 angstroms and heating the substrate, the CIG layer and the selenium layer. A processing chamber system is also disclosed.Type: GrantFiled: February 16, 2011Date of Patent: February 12, 2013Assignee: Ahbee1, LPInventor: Aiguo Feng
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Publication number: 20130005125Abstract: Embodiments of the present invention are generally directed to a method for disposing nanoparticles on a substrate. In one embodiment, a substrate having a plurality of recesses is provided. In this embodiment, a plurality of nanoparticles is also provided. The nanoparticles include a catalyst material coupled to one or more ligands, and these nanoparticles are disposed within respective recesses of the substrate. In some embodiments, the substrate is processed to form nanostructures, such as nanotubes or nanowires, within the recesses. Devices and systems having such nanostructures are also disclosed.Type: ApplicationFiled: September 12, 2012Publication date: January 3, 2013Applicant: Micron Technology, Inc.Inventor: Gurtej Sandhu
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Patent number: 8343782Abstract: The present invention relates to a method that involves providing a stack of a first substrate and a InGaN seed layer formed on the first substrate, growing an InGaN layer on the InGaN seed layer to obtain an InGaN-on-substrate structure, forming a first mirror layer overlaying the exposed surface of the grown InGaN layer, attaching a second substrate to the exposed surface of the mirror layer, detaching the first substrate from the InGaN seed layer and grown InGaN layer to expose a surface of the InGaN seed layer opposite the first mirror layer, and forming a second mirror layer overlaying the opposing surface of the InGaN seed layer.Type: GrantFiled: September 29, 2010Date of Patent: January 1, 2013Assignee: SoitecInventor: Fabrice M. Letertre
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Patent number: 8334154Abstract: A method for producing quantum dots embedded in a matrix on a substrate includes the steps of: depositing a precursor on the substrate, the precursor including at least one first metal or a metal compound; contacting the deposited precursor and uncovered areas of the substrate with a gas-phase reagent including at least one second metal and/or a chalcogen; and initiating a chemical reaction between the precursor and the reagent by raising a temperature thereof simultaneously with or subsequent to the contacting so that the matrix consists exclusively of elements of the reagent.Type: GrantFiled: December 11, 2007Date of Patent: December 18, 2012Assignee: Helmholtz-Zentrum Berlin Fuer Materialien und Energie GmbHInventors: David Fuertes Marón, Sebastian Lehmann, Sascha Sadewasser, Martha Christina Lux-Steiner
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Publication number: 20120306052Abstract: An object of the present invention is to provide an epitaxial wafer on which dislocation is preventable even when a LSA treatment is performed in device processes. An epitaxial wafer according to the present invention includes a wafer 11 whose nitrogen concentration is 1×1012 atoms/cm3 or more or whose specific resistance is 20 m?·cm or less by boron doping, and an epitaxial layer 12 provided on the wafer 11. On the wafer 11, if a thermal treatment is performed at 750° C. for 4 hours and then at 1,000° C. for 4 hours, polyhedron oxygen precipitates grow predominantly over plate-like oxygen precipitates. Therefore, in the device processes, plate-like oxygen precipitates cannot be easily formed. As a result, even when the LSA treatment is performed after various thermal histories in the device processes, it is possible to prevent the dislocation, which is triggered by oxygen precipitates, from generating.Type: ApplicationFiled: February 3, 2011Publication date: December 6, 2012Applicant: SUMCO CORPORATIONInventors: Toshiaki Ono, Jun Fujise
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Patent number: 8324087Abstract: Among others, techniques are described for forming nanotubes. In one aspect, a method includes forming a base layer of a transition metal on a substrate. The method also includes heating the substrate with the base layer in a mixture of gases to grow nanotubes on the base layer.Type: GrantFiled: March 19, 2010Date of Patent: December 4, 2012Assignee: University of Southern CaliforniaInventors: Chongwu Zhou, Lewis Gomez De Arco, Akshay Kumar
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Patent number: 8293646Abstract: A high quality interface is formed at a low oxygen-carbon density between a substrate and a thin film while preventing heat damage on the substrate and increase of thermal budget. This method includes a step of loading a wafer into a reaction furnace, a step of pretreating the wafer in the reaction furnace, a step of performing a main processing of the pretreated wafer in the reaction furnace, and a step of unloading the wafer from the reaction furnace after the main processing. Hydrogen gas is continuously supplied to the reaction furnace in the period from the end of the pretreating step to the start of the main processing and at least during vacuum-exhausting an interior of the reaction furnace.Type: GrantFiled: November 2, 2005Date of Patent: October 23, 2012Assignee: Hitachi Kokusai Electric Inc.Inventors: Takashi Ozaki, Osamu Kasahara, Takaaki Noda, Kiyohiko Maeda, Atsushi Moriya, Minoru Sakamoto
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Patent number: 8278135Abstract: There is provided a film formation apparatus which is capable of forming an EL layer using an EL material with high purity. The EL material is purified by sublimation immediately before film formation in the film formation apparatus, to thereby remove oxygen, water, and another impurity, which are included in the EL material. Also, when film formation is performed using the EL material (high purity EL material) obtained by purifying with sublimation as an evaporation source, a high purity EL layer can be formed.Type: GrantFiled: September 18, 2007Date of Patent: October 2, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toshimitsu Konuma, Takeshi Nishi
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Patent number: 8280531Abstract: A method and computer program for the control of the heat treatment of batches of metal workpieces for increasing the degree of automation of industrial furnace plants presumes an identical batch layout, an identical treatment program, and an identical article geometry of metal workpieces and relates it to a model batch, which has been run using batch thermoelements. The model batch becomes the foundation for a new batch. Through the assumption of program parameters of the actually run process of the model batch into the program of the new batch to be run, new batch thermoelements are not required for the new batch to be run.Type: GrantFiled: April 1, 2010Date of Patent: October 2, 2012Assignee: Ipsen, Inc.Inventors: Thomas Eversmann, Thomas Muhlhaus, Frank Biester, Regina Wolf, Jorg Willeke, Werner Schulte
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Publication number: 20120208358Abstract: Method of fabricating a multilayer film having at least one ultrathin layer of crystalline silicon, the film being fabricated from a substrate having a crystalline structure and including a previously-cleaned surface. The method includes the steps of: a) exposing the cleaned surface to a radiofrequency plasma generated in a gaseous mixture of SiF4, hydrogen, and argon, so as to form an ultrathin layer of crystalline silicon having an interface sublayer in contact with the substrate and containing microcavities; b) depositing at least one layer of material on the ultrathin layer of crystalline silicon so as form a multilayer film, the multilayer film including at least one mechanically strong layer; and c) annealing the substrate covered in the multilayer film at a temperature higher than 400° C., thereby enabling the multilayer film to be separated from the substrate.Type: ApplicationFiled: October 15, 2010Publication date: August 16, 2012Applicants: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, ECOLE POLYTECHNIQUEInventors: Pere Roca I Cabarrocas, Mario Moreno
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Publication number: 20120199814Abstract: A p-channel tunneling field effect transistor (TFET) is selected from a group consisting of (i) a multi-layer structure of group IV layers and (u) a multi-layer structure of group III-V layers. The p-channel TFET includes a channel region comprising one of a silicon-germanium alloy with non-zero germanium content and a ternary III-V alloy. An n-channel TFET is selected from a group consisting of (i) a multi-layer structure of group IV layers and (u) a multi-layer structure of group III-V layers. The n-channel TFET includes an n-type region, a p-type region with a p-type delta doping, and a channel region disposed between and spacing apart the n-type region and the p-type region. The p-channel TFET and the n-channel TFET may be electrically connected to define a complementary field-effect transistor element. TFETs may be fabricated from a silicon-germanium TFET layer structure grown by low temperature (500 degrees Centigrade) molecular beam epitaxy.Type: ApplicationFiled: September 13, 2010Publication date: August 9, 2012Applicant: THE OHIO STATE UNIVERSITYInventor: Paul R. Berger
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Patent number: 8216921Abstract: A method for producing a silicon wafer for epitaxial substrate which includes a first step of performing thermal oxidization on a silicon wafer containing boron atoms no less than 1E19 atoms/cm3, thereby forming a silicon oxide film on the surface of the silicon wafer, a second step of peeling off the silicon oxide film, and a third step of performing heat treatment on the silicon wafer in a hydrogen atmosphere.Type: GrantFiled: September 16, 2009Date of Patent: July 10, 2012Assignee: Covalent Materials CorporationInventor: Tatsuo Fujii
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Publication number: 20120168724Abstract: A method of manufacturing one or more graphene devices is disclosed. A thin film growth substrate is formed directly on a device substrate. Graphene is formed on the thin film growth substrate. A transistor is also disclosed, having a device substrate and a source supported by the device substrate. The transistor also has a drain separated from the source and supported by the device substrate. The transistor further has a single layer graphene (SLG) channel grown partially on and coupling the source and the drain. The transistor also has a gate aligned with the SLG channel, and a gate insulator between the gate and the SLG channel. Integrated circuits and other apparati having a device substrate, a thin film growth substrate formed directly on at least a portion of the device substrate, and graphene formed directly on at least a portion of the thin film growth substrate are also disclosed.Type: ApplicationFiled: July 21, 2010Publication date: July 5, 2012Applicant: CORNELL UNIVERSITYInventors: Jiwoong Park, Carlos Ruiz-Vargas, Mark Philip Levendorf, Lola Brown
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Patent number: 8187982Abstract: The invention permits a plurality of strips of resin adhesive film having a desired width and unwound from a single feeding reel to be simultaneously pasted on a solar cell. For this purpose, the invention comprises the steps of: unwinding a resin adhesive film sheet from a reel on which the resin adhesive film sheet is wound; splitting the unwound resin adhesive film into two or more film strips in correspondence to lengths of wiring material to bond; pasting the strips of resin adhesive film on an electrode of the solar cell; and placing the individual lengths of wiring material on the electrode of the solar cell having the plural strips of resin adhesive film pasted thereon and thermally setting the resin adhesive film by heating so as to fix together the electrode of the solar cell and the wiring material.Type: GrantFiled: March 22, 2010Date of Patent: May 29, 2012Assignee: Sanyo Electric Co., Ltd.Inventors: Yousuke Ishii, Shingo Okamoto
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Patent number: 8183879Abstract: The invention relates to a measuring arrangement, a semiconductor arrangement and a method for operating a reference source, wherein at least one semiconductor component and a voltage source are connected to a measuring unit and the measuring unit provides a measured value that is proportional to the number of defects.Type: GrantFiled: March 6, 2009Date of Patent: May 22, 2012Assignee: Infineon Technologies AGInventors: Ralf Brederlow, Roland Thewes
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Patent number: 8178443Abstract: Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about ?600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of SixByCz, SixByNz, SixByCzNw, BxCy, and BxNy. In some embodiments, a hardmask film includes a germanium-rich GeNx material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.Type: GrantFiled: December 4, 2009Date of Patent: May 15, 2012Assignee: Novellus Systems, Inc.Inventors: Vishwanathan Rangarajan, George Andrew Antonelli, Bart van Schravendijk
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Publication number: 20120108041Abstract: A technique for forming nanostructures including a definition of a charge pattern on a substrate and introduction of charged molecular scale sized building blocks (MSSBBs) to a region proximate the charge pattern so that the MSSBBs adhere to the charge pattern to form the feature.Type: ApplicationFiled: January 10, 2012Publication date: May 3, 2012Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGYInventors: Joseph M. Jacobson, David Kong, Vikas Anant, Ashley Salomon, Saul Griffith, Will DelHagen, Vikrant Agnihotri
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Publication number: 20120108040Abstract: A vaporizing spray deposition device for forming a thin film includes a processing chamber, a fluid line, and a spray head coupled to the fluid line proximate the processing chamber. The fluid line is configured to transfer a polymer fluid and solvent mixture to the spray head. The spray head is configured to receive the polymer fluid and solvent mixture and to atomize the polymer fluid and solvent mixture to emit it in a substantially vaporized form to be deposited on a surface and thereby forming a thin film of the polymer on the surface after evaporation of the solvent. In an embodiment, the vaporizing spray deposition device may include a heating device to perform a hard bake process on the polymer. In an embodiment, the vaporizing spray deposition device may be configured to provide a post deposition solvent spray trim process to the thin film polymer.Type: ApplicationFiled: November 1, 2010Publication date: May 3, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Yu Chang, Kuei-Liang Lu, Ming-Feng Shieh
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Patent number: 8163634Abstract: A method includes an act of providing a crystalline substrate with a diamond-type lattice and an exposed substantially (111)-surface. The method also includes an act of forming a graphene layer or a graphene-like layer on the exposed substantially (111)-surface.Type: GrantFiled: July 19, 2010Date of Patent: April 24, 2012Assignee: Alcatel LucentInventors: Jorge Manuel Garcia, Loren N. Pfeiffer
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Patent number: 8138064Abstract: A method for producing a silicon film-transferred insulator wafer is disclosed. The method includes a surface activation step of performing a surface activation treatment on at least one of a surface of an insulator wafer and a hydrogen ion-implanted surface of a single crystal silicon wafer into which a hydrogen ion has been implanted to form a hydrogen ion-implanted layer; a bonding step that bonds the hydrogen ion-implanted surface to the surface of the insulator wafer to obtain bonded wafers; a first heating step that heats the bonded wafers; a grinding and/or etching step of grinding and/or etching a surface of a single crystal silicon wafer side of the bonded wafers; a second heating step that heats the bonded wafers; and a detachment step to detach the hydrogen ion-implanted layer by applying a mechanical impact to the hydrogen ion-implanted layer of the bonded wafers thus heated at the second temperature.Type: GrantFiled: October 29, 2009Date of Patent: March 20, 2012Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Makoto Kawai, Kouichi Tanaka, Yuji Tobisaka, Yoshihiro Nojima
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Patent number: 8138086Abstract: A method of manufacturing a flash memory device and devices thereof, which may be capable of preventing damage to a gate. A method of manufacturing a flash memory device may include preparing a semiconductor substrate having an active region defined by a device separator. A method of manufacturing a flash memory device may include forming a floating gate, a oxide-nitride-oxide (ONO) layer and/or a control gate layer on and/or over a substrate. A method of manufacturing a flash memory device may include forming a low temperature oxide (LTO) film on and/or over a control gate, etching a LTO film to expose a desired part of a control gate, using a LTO film as a mask to etch a desired part of each of a floating gate layer, a ONO layer and/or a control gate to form a gate pattern, and/or substantially removing a LTO film by wet etching.Type: GrantFiled: December 11, 2009Date of Patent: March 20, 2012Assignee: Dongbu HiTek Co., Ltd.Inventor: Chung-Kyung Jung
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Patent number: 8129284Abstract: A semiconductor wafer in which a carbon thin film is formed on a surface of a silicon substrate implanted with impurities is irradiated with flash light emitted from flash lamps. Absorbing the flash light causes the temperature of the carbon thin film to increase. The surface temperature of the silicon substrate implanted with impurities is therefore increased to be higher than that in a case where no thin film is formed, and the sheet resistance value can be thereby decreased. When the semiconductor wafer with the carbon thin film formed thereon is irradiated with flash light in high concentration oxygen atmosphere, since the carbon of the thin film is oxidized to be vaporized, removal of the thin film is performed concurrently with flash heating.Type: GrantFiled: March 26, 2010Date of Patent: March 6, 2012Assignee: Dainippon Screen Mfg. Co., Ltd.Inventor: Shinichi Kato