Abstract: Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer over the substrate, and a stacked gate structure of SiGe and/or Si:C having stresses produced at the interfaces of SSi (strained Si)/SiGe or SSi/Si:C in the stacked gate structure. The stacked gate structure has a first stressed film layer of large grain size Si or SiGe over the gate dielectric layer, a second stressed film layer of strained SiGe or strained Si:C over the first stressed film layer, and a semiconductor or conductor such as p(poly)-Si over the second stressed film layer.

Abstract: A method for producing quantum dots embedded in a matrix on a substrate includes the steps of: depositing a precursor on the substrate, the precursor including at least one first metal or a metal compound; contacting the deposited precursor and uncovered areas of the substrate with a gas-phase reagent including at least one second metal and/or a chalcogen; and initiating a chemical reaction between the precursor and the reagent by raising a temperature thereof simultaneously with or subsequent to the contacting so that the matrix consists exclusively of elements of the reagent.

Abstract: It is an object of the present invention to provide a method for manufacturing an SOI substrate having an SOI layer that can be used in practical applications with high yield even when a flexible substrate such as a glass substrate or a plastic substrate is used. Further, it is another object of the present invention to provide a method for manufacturing a thin semiconductor device using such an SOI substrate with high yield. When a single-crystal semiconductor substrate is bonded to a flexible substrate having an insulating surface and the single-crystal semiconductor substrate is separated to manufacture an SOI substrate, one or both of bonding surfaces are activated, and then the flexible substrate having an insulating surface and the single-crystal semiconductor substrate are attached to each other.

Abstract: It is an object of the present invention to provide a crystal silicon element emitting a desired visible light at high efficiency, by markedly enhancing the crystallinity of the nano Si. A p-type single crystal silicon substrate 10, a thick silicon oxide film 17a and a thin silicon oxide film 17b are disposed on the one surface of the silicon substrate 10. On the thin silicon oxide film 17b, plural nano Si 15 having the same crystal axis as the silicon substrate 10 are formed. In addition, a thin silicon oxide film 16 that is disposed in a manner that the thin silicon film 16 covers the upper and side faces of the nano Si 15, and a transparent electrode (for example ITO) 19 that is disposed in a manner that the transparent electrode 19 covers at least the upper face of the nano Si 15 are formed. Further, a metal electrode 18 (for example, aluminum) is formed in a manner that the metal electrode 18 has an ohmic contact with the other surface of the silicon substrate 10.

Abstract: Method for manufacturing a semiconductor optical device includes forming an epitaxial structure containing at least an active layer which can emit light, of a III-V group semiconductor material; forming an insulating layer over the epitaxial structure, which prevents the V group element from escaping from the epitaxial structure during heat treatment; heat treating the epitaxial structure at at least 800 degrees C.; and removing the insulating layer, thereby enhancing the reliability of the device.

Abstract: This invention relates to a method for producing group IB-IIA-VIA quaternary or higher alloy semiconductor films wherein the method comprises the steps of (i) providing a metal film comprising a mixture of group IB and group IIIA metals; (ii) heat treating the metal film in the presence of a source of a first group VIA element (said first group VIA element hereinafter being referred to as VIA1) under conditions to form a first film comprising a mixture of at least one binary alloy selected from the group consisting of a group IB-VIA1 alloy and a group IIIA-VIA1 alloy and at least one group IB-IIIA-VIA1 ternary alloy (iii) optionally heat treating the first film in the presence of a source of a second group VIA element (said second group VI element hereinafter being referred to as VIA2) under conditions to convert the first film into a second film comprising at least one alloy selected from the group consisting of a group IB-VIA1-VIA2 alloy and a group IIIA-VIA1-VIA2 alloy; and the at least one group IB-III-VI

Abstract: Memory cells, and methods of forming such memory cells, are provided that include a carbon-based reversible resistivity switching material. In particular embodiments, methods in accordance with this invention form a memory cell by forming a layer of carbon material above a substrate, forming a barrier layer above the carbon layer, forming a hardmask layer above the barrier layer, forming a photoresist layer above the hardmask layer, patterning and developing the photoresist layer to form a photoresist region, patterning and etching the hardmask layer to form a hardmask region, and using an ashing process to remove the photoresist region while the barrier layer remains above the carbon layer. Other aspects are also provided.

Abstract: The present invention provides a superior method for the removal of nitride semiconductor thin films, thick films, heterostructures, and bulk material from initial substrates and/or templates. The method utilizes specially patterned mask layers between the initial substrates/templates and the nitride semiconductors to decrease adhesion between the nitride semiconductor and underlying material. Thermal stresses generated upon cooling the nitride semiconductor from its deposition temperature trigger spontaneous separation of the nitride semiconductor from the initial substrate or template at the mask layer. The invention remedies deficiencies in the prior art by providing a simple, reproducible, and effective means of removing initial substrates and templates from a variety of nitride semiconductor layers and structures.

Abstract: The invention relates to a process for fabricating a heterostructure. This process is noteworthy in that it comprises the following steps: a) a strained crystalline thin film is deposited on, or transferred onto, an intermediate substrate; b) a strain relaxation layer, made of crystalline material capable of being plastically deformed by a heat treatment at a relaxation temperature, at which the material constituting the thin film deforms by elastic deformation is deposited on the thin film; c) the thin film and the relaxation layer are transferred onto a substrate; and d) a thermal budget is applied at at least the relaxation temperature, so as to cause the plastic deformation of the relaxation layer and the at least partial relaxation of the thin film by elastic deformation, and thus to obtain the final heterostructure.

Abstract: A method of growing a p-type nitride semiconductor material by molecular beam epitaxy (MBE) uses bis(cyclopentadienyl)magnesium (Cp2Mg) as the source of magnesium dopant atoms. Ammonia gas is used as the nitrogen precursor for the MBE growth process. To grow p-type GaN, for example, by the method of the invention, gallium, ammonia and Cp2Mg are supplied to an MBE growth chamber; to grow p-type AlGaN, aluminum is additionally supplied to the growth chamber. The growth process of the invention produces a p-type carrier concentration, as measured by room temperature Hall effect measurements, of up to 2 1017 cm?3, without the need for any post-growth step of activating the dopant atoms.

Abstract: A method of manufacturing a semiconductor substrate includes a growing step of growing a second single crystalline semiconductor on a first single crystalline semiconductor, a blocking layer forming step of forming a blocking layer on the second single crystalline semiconductor, and a relaxing step of generating crystal defects at a portion deeper than the blocking layer to relax a stress acting on the second single crystalline semiconductor. The blocking layer includes, e.g., a porous layer, and prevents the crystal defects at the portion deeper than the blocking layer from propagating to the surface of the second single crystalline semiconductor.

Abstract: A silicon single crystal is grown by the CZ method. A silicon melt from which the crystal is grown is added with dopant such that the crystal has a resistivity of 0.025 to 0.08 ?cm. As well as the dopant, carbon is added to the silicon melt. The crystal is pulled in a hydrogen-bearing inert atmosphere.

Abstract: A process for fabricating doped crystalline semiconductors is provided using layer by layer deposition of semiconductors and the corresponding dopants.

Abstract: In accordance with aspects of the invention, a method of forming a memory cell is provided, the method including forming a steering element above a substrate, and forming a memory element coupled to the steering element, wherein the memory element comprises a carbon-based material having a thickness of not more than ten atomic layers. The memory element may be formed by repeatedly performing the following steps: forming a layer of a carbon-based material, the layer having a thickness of about one monolayer, and subjecting the layer of carbon-based material to a thermal anneal. Other aspects are also described.

Abstract: Example embodiments include micro-heater arrays including first and second micro-heaters disposed perpendicular to or parallel with each other on a substrate and methods of fabricating pn junctions between first and second heating portions using the heat generated from the first and second heating portions, respectively, when applying a voltage to the micro-heater array. Accordingly, when forming pn junctions using micro-heaters, a high-quality pn junction may be fabricated on a glass substrate over a large area.

Abstract: It is an object to provide a method for manufacturing an SOI substrate in which crystal defects of a single crystal semiconductor layer are reduced even when a single crystal semiconductor substrate in which crystal defects exist is used. Such an SOI substrate can be manufactured through the steps of forming a single crystal semiconductor layer which has an extremely small number of defects over a single crystal semiconductor substrate by an epitaxial growth method; forming an oxide film on the single crystal semiconductor substrate by thermal oxidation treatment; introducing ions into the single crystal semiconductor substrate through the oxide film; bonding the single crystal semiconductor substrate into which the ions are introduced and a semiconductor substrate to each other; causing separation by heat treatment; and performing planarization treatment on the single crystal semiconductor layer provided over the semiconductor substrate.

Abstract: An apparatus for manufacturing a semiconductor device, including in a reaction chamber: a rotor provided with a holding member holding a wafer thereon and a heater heating the wafer therein; a rotation drive mechanism; a gas supply mechanism; a gas exhaust mechanism; and a rectifying plate for rectifying the supplied process gas to supply the rectified gas, and including: an annular rectifying fin mounted on a lower portion of the plate, having a larger lower end inside diameter than an upper end inside diameter thereof and downward rectifying gas exhausted in an outer circumferential direction from above the wafer; and a distance control mechanism controlling a vertical distance between the plate and the wafer and a vertical distance between the fin and the rotor top face to be predetermined distances, respectively, thereby providing higher film formation efficiency.

Abstract: A method of manufacturing a silicon substrate includes: growing a silicon single crystal having a carbon concentration in the range of 1.0×1016 atoms/cm3 to 1.6×1017 atoms/cm3 and an initial oxygen concentration in the range of 1.4×1018 atoms/cm3 to 1.6×1018 atoms/cm3 using a CZ method; slicing the silicon single crystal; forming an epitaxial layer on the sliced silicon single crystal; and performing a heat treatment thereon as a post-annealing process at a temperature in the range of 600° C. to 850° C.

Abstract: The growing surface of a material such as InGaN is exposed to a small diameter laser beam that is directed to controlled locations, such as by scanning mirrors. Material characteristics may be modified at the points of exposure. In one embodiment, mole fraction of selected material is reduced where laser exposure takes place. In one embodiment, the material is grown in a MBE or CVD chamber.

Abstract: For manufacture of a semiconductor device using a low heat resistant substrate such as a glass substrate, a method of heat treatment for activating an impurity element that is used to dope a semiconductor film and for performing gettering on the semiconductor film in a short period of time without deforming the substrate, is provided. Also provided is a heat treatment apparatus for carrying out the above heat treatment. The heat treatment method of the present invention involves irradiating an object with light emitted from a lamp light source, and is characterized in that the lamp light source emits light for 0.1 to 20 seconds at a time and that light from the lamp light source irradiates the object several times. The method is also characterized in that the irradiated region is subjected to pulsating light from the lamp light source such that the irradiated region holds the temperature to its highest for 0.5 to 5 seconds.

Abstract: A wafer structure and epitaxial growth method for growing the same. The method may include forming a mask layer having nano-sized areas on a wafer, forming a porous layer having nano-sized pores on a surface of the wafer by etching the mask layer and a surface of the wafer, and forming an epitaxial material layer on the porous layer using an epitaxial growth process.

Abstract: Disclosed herein is a method for production of a thin-film semiconductor device which includes, a first step to form a gate electrode on a substrate, a second step to form a gate insulating film of silicon oxynitride on the substrate in such a way as to cover the gate electrode, a third step to form a semiconductor thin film on the gate insulating film, and a fourth step to perform heat treatment in an oxygen-containing oxidizing atmosphere for modification through oxygen binding with oxygen-deficient parts in the silicon oxynitride film constituting the gate insulating film.

Abstract: Methods are disclosed of fabricating a compound nitride semiconductor structure. A substrate is disposed over a susceptor in a processing chamber, with the susceptor in thermal communication with the substrate. A group-III precursor and a nitrogen precursor are flowed into the processing chamber. The susceptor is heated with a nonuniform temperature profile to heat the substrate. A nitride layer is deposited over the heated substrate with a thermal chemical vapor deposition process within the processing chamber using the group-III precursor and the nitrogen precursor.

Abstract: The present invention includes a first step of forming a nitride semiconductor layer by metal organic chemical vapor deposition by using a first carrier gas containing a nitrogen carrier gas and a hydrogen carrier gas of a flow quantity larger than that of the nitrogen carrier gas to thereby supply a raw material containing Mg and a Group V raw material containing N, and a second step of lowering a temperature by using a second carrier gas to which a material containing N is added, and hence solves the problems.

Abstract: A method of cooling a complex electronic system includes preventing system air from passing through a front side and a rear side of a server system main board, organizing a plurality of electronic segments of the server system main board, providing cool air horizontally to the server system main board through a cool air intake provided at a position located underneath the front side and at a bottom side of the server system main board, using the cool air intake to provide the cool air to a plurality of cooling segments that redirect the cool air vertically at a 90° angle, and using a hot air exhaust after the hot air reaches the top side of the server system main board to redirect the hot air horizontally at a 90° angle and exhaust the hot air.

Abstract: A laser-annealing method includes the steps of a first step of cleaning a non-monocrystal silicon film formed on a substrate, and a second step of laser-annealing the non-monocrystal silicon film in an atmosphere containing oxygen therein, wherein the first and second steps are conducted continuously without being exposed to the air. Also, a laser-annealing device includes a cleaning chamber, and a laser irradiation chamber, wherein a substrate to be processed is transported between the cleaning chamber and the laser irradiation chamber without being exposed to the air.

Abstract: A vertical CVD apparatus is arranged to process a plurality of target substrates all together to form a silicon germanium film. The apparatus includes a reaction container having a process field configured to accommodate the target substrates, and a common supply system configured to supply a mixture gas into the process field. The mixture gas includes a first process gas of a silane family and a second process gas of a germane family. The common supply system includes a plurality of supply ports disposed at different heights.

Abstract: Methods and apparatus for producing a gallium nitride semiconductor on insulator structure include: bonding a single crystal silicon layer to a transparent substrate; and growing a single crystal gallium nitride layer on the single crystal silicon layer.

Abstract: A strained Si-SOI substrate, and a method for producing the same are provided, wherein the method includes the steps of growing a SiGe mixed crystal layer 14 on an SOI substrate 10 having an Si layer 13 and a buried oxide film 12; forming protective films 15, 16 on the surface of the SiGe mixed crystal layer 14; implanting light element ions into a vicinity of the interface between the Si layer 13 and the buried oxide film 12; performing a first heat treatment at a temperature in the range of 400 to 1000° C.; performing a second heat treatment at a temperature not lower than 1050° C. under an oxidizing atmosphere; performing a third heat treatment at a temperature not lower than 1050° C. under an inert atmosphere; removing the Si oxide film 18 formed on the surface; and forming a strained Si layer 19.

Abstract: A semiconductor substrate having recesses filled with heteroepitaxial silicon-containing material with different portions having different impurity concentrations. Strained layers can fill recessed source/drain regions in a graded, bottom-up fashion. Layers can also line recess sidewalls with one concentration of strain-inducing impurity and fill the remainder to the recess with a lower concentration of the impurity. In the latter case, the sidewall liner can be tapered.

Abstract: A method for creating a Group IV semiconductor densified thin film is disclosed. The method includes applying a colloidal dispersion to a substrate, wherein the colloidal dispersion includes a plurality of Group IV semiconductor nanoparticles and an organic solvent. The method also includes removing the organic solvent by applying a first temperature for a first time period to form a Group IV semiconductor non-densified thin film; and heating the Group IV semiconductor non-densified thin film to a second temperature for a second time period, wherein the second temperature is a pre-heating target temperature. The method further includes heating the Group IV semiconductor non-densified thin film to a third temperature for a third time period with a flash lamp apparatus, wherein the third temperature is equal to or greater than a sintering temperature, wherein a Group IV semiconductor densified thin film is created.

Abstract: A method is provided for forming a Group IBIIIAVIA solar cell absorber layer including indium (In) and gallium (Ga) that are distributed substantially uniformly between the top surface and the bottom surface of the absorber layer. In one embodiment method includes forming a precursor by depositing a metallic layer including copper (Cu), indium (In) and gallium (Ga) on the base, and depositing a film comprising selenium (Se) and tellurium (Te) on the metallic layer. In the precursor, the molar ratio of Te to Ga is equal to or less than 1. In the following step, the precursor is heated to a temperature range of 400-600° C. to form the Group IBIIIAVIA solar cell absorber layer.

Abstract: A process can include forming a doped semiconductor layer over a substrate. The process can also include performing an action that reduces a dopant content along an exposed surface of a workpiece that includes the substrate and the doped semiconductor layer. The action is performed after forming the doped semiconductor layer and before the doped semiconductor layer is exposed to a room ambient. In particular embodiments, the doped semiconductor layer includes a semiconductor material that includes a combination of at least two elements selected from the group consisting of C, Si, and Ge, and the doped semiconductor layer also includes a dopant, such as phosphorus, arsenic, boron, or the like. The action can include forming an encapsulating layer, exposing the doped semiconductor layer to radiation, annealing the doped semiconductor layer, or any combination thereof.

Abstract: There is disclosed a method for forming a gallium nitride layer of which resistivity is 1×106?·cm or more, including steps of: forming a gallium nitride layer containing iron on a substrate; and heating said gallium nitride layer formed on said substrate.

Abstract: The invention relates to a method of forming a layer of elastically unstrained crystalline material intended for electronics, optics, or optronics applications, wherein the method is carried out using a structure that includes a first crystalline layer which is elastically strained under tension (or respectively in compression) and a second crystalline layer which is elastically strained in compression (or respectively under tension), with the second layer being adjacent to the first layer.

Abstract: A method for manufacturing wafers using a low EPD crystal growth process and a wafer annealing process is provided that results in GaAs/InGaP wafers that provide higher device yields from the wafer.

Abstract: Affords high-carrier-concentration, low-cracking-incidence gallium nitride substrates and methods of forming gallium nitride films. A gallium nitride film 52 in which the carrier concentration is 1×1017 cm?3 or more is created. Initially, a gallium nitride layer 51 including an n-type dopant is formed onto a substrate 50. Then, the gallium nitride layer 51 formed on the substrate 50 is heated to form a gallium nitride film 52.

Abstract: Methods of making nanometer-scale semiconductor structures with controlled size are disclosed. Semiconductor structures that include one or more nanowires are also disclosed. The nanowires can include a passivation layer or have a hollow tube structure.

Abstract: A method for manufacturing a free-standing substrate made of a semiconductor material. A first assembly is provided and it includes a relatively thinner nucleation layer of a first material, a support of a second material, and a removable bonding interface defined between facing surfaces of the nucleation layer and support. A substrate of a relatively thicker layer of a third material is grown, by epitaph on the nucleation layer, to form a second assembly with the substrate attaining a sufficient thickness to be free-standing. The third material is preferably a monocrystalline material. Also, the removable character of the bonding interface is preserved with at least the substrate being heated to an epitaxial growth temperature.

Abstract: Methods for formation of epitaxial layers containing n-doped silicon are disclosed. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. In specific embodiments, the formation of the n-doped epitaxial layer involves exposing a substrate in a process chamber to deposition gases including a silicon source, a carbon source and an n-dopant source. An epitaxial layer may have considerable tensile stress which may be created in a significant amount by a high concentration of n-dopant. A layer having n-dopant may also have substitutional carbon. Phosphorus as an n-dopant with a high concentration is provided. A substrate having an epitaxial layer with a high level of n-dopant is also disclosed.

Abstract: A semiconductor device with a superlattice and method of making same includes forming a layer of amorphous silicon over a substrate, and forming a layer of nanocrystals by laser thermal annealing the layer of amorphous silicon. A gate dielectric is formed between the layer of amorphous silicon and the substrate. A dielectric layer is formed on the layer of amorphous silicon. The steps of forming the layer of amorphous silicon and forming the dielectric layer can be repeated. The thickness of the dielectric layer is between about 25 to 40 angstroms, and the thickness of the amorphous silicon layer is between about 30 to 50 angstroms. The average diameter of the nanocrystals is less than 40 angstroms.

Abstract: A method of forming an epitaxial layer in a chamber is disclosed. The method includes positioning a Group IV semiconductor substrate in the chamber; and depositing a nanoparticle ink, the nanoparticle ink including a set of Group IV nanoparticles and a solvent, wherein a porous compact is formed. The method also includes heating the porous compact to a temperature of between about 100° C. and about 1100° C., and for a time period of between about 5 minutes to about 60 minutes with a heating apparatus, wherein the epitaxial layer is formed.

Abstract: Exemplary embodiments provide semiconductor devices with a high-quality semiconductor material on a lattice mismatched substrate and methods for their manufacturing using low temperature growth techniques followed by an insulator-capped annealing process. The semiconductor material can have high-quality with a sufficiently low threading dislocation (TD) density, and can be effectively used for integrated circuit applications such as an integration of optically-active materials (e.g., Group III-V materials) with silicon circuitry. In an exemplary embodiment, the high-quality semiconductor material can include one or more ultra-thin high-quality semiconductor epitaxial layers/films/materials having a desired thickness on the lattice mismatched substrate. Each ultra-thin high-quality semiconductor epitaxial layer can be formed by capping a low-temperature grown initial ultra-thin semiconductor material, annealing the capped initial ultra-thin semiconductor material, and removing the capping layer.

Abstract: This invention relates to field effect transistors having carbon nanotube contacts and to a method of making these field effect transistors. The field effect transistors have better contacts as the source and drains as well as the bridge are made of carbon nanotubes. The fabrication of the proposed embodiment becomes possible by using a fabrication process which involves exposing the structure to two different temperatures.

Abstract: A metallic, semiconductor, dielectric or oxide layer, such as a thin gate oxide, is formed by supplying a wafer in a processing chamber with thermal energy to heat the wafer and light energy, such as laser light at a selected wavelength, to improve the quality of the resulting layer. The laser light may be focused and/or scanned to control the depth and spatial extent of laser processing.

Abstract: A method for maintaining semiconductor manufacturing apparatus, semiconductor manufacturing apparatus, and a method for manufacturing a semiconductor that allow a component to be reused and contamination to a wafer to be suppressed without a need for replacement of the component, are provided. The method for maintaining semiconductor manufacturing apparatus includes, in a reactor in which a component having a base material covered with a first SiC film is installed so as to form a Si epitaxial film on a wafer, forming a second SiC film on a surface of the component with at least part of the first SiC film sublimated while repeating a process.

Abstract: A method of manufacturing a semiconductor device, includes the steps of: raising a temperature of a sapphire substrate which is included in the semiconductor device from a room temperature to a preheat temperature of 150° C. to 450° C. and keeping the preheat temperature for a first predetermined time, thereby preheating the semiconductor device; and subsequently raising a temperature of the sapphire substrate from the preheat temperature to a thermal reaction temperature of 500° C. or higher and keeping the thermal reaction temperature for a second predetermined time, thereby performing a thermal reaction treatment of the semiconductor device.

Abstract: Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.

Abstract: Impurity concentration (Nd(X)) in an n-drift layer in a diode is at a maximum at a position at a distance Xp from an anode electrode in a direction from the anode electrode to a cathode electrode, and gradually decreases from the position toward each of the anode electrode and the cathode electrode. A ratio of the peak impurity concentration Np to an averaged impurity concentration Ndm in the n-drift layer is in the range of 1 to 5. This provides a diode and a manufacturing method thereof by which oscillations in voltage and current at reverse recovery are inhibited to achieve enhancement both in high speed and low-loss characteristics and in soft recovery characteristics.

Abstract: A method for forming a SiGe epitaxial layer is described. A first SEG process is performed under a first condition, consuming about 1% to 20% of the total process time for forming the SiGe epitaxial layer. Then, a second SEG process is performed under a second condition, consuming about 99% to 80% of the total process time. The first condition and the second condition include different temperatures or pressures. The first and the second SEG processes each uses a reactant gas that includes at least a Si-containing gas and a Ge-containing gas.